TWI301588B - Semiconductor module and production method therefor and module for ic cards and the like - Google Patents

Semiconductor module and production method therefor and module for ic cards and the like Download PDF

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Publication number
TWI301588B
TWI301588B TW091134771A TW91134771A TWI301588B TW I301588 B TWI301588 B TW I301588B TW 091134771 A TW091134771 A TW 091134771A TW 91134771 A TW91134771 A TW 91134771A TW I301588 B TWI301588 B TW I301588B
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Taiwan
Prior art keywords
circuit board
printed circuit
semiconductor
semiconductor wafer
semiconductor module
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TW091134771A
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English (en)
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TW200301871A (en
Inventor
Nishikawa Masataka
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Sharp Kk
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Publication of TW200301871A publication Critical patent/TW200301871A/zh
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Publication of TWI301588B publication Critical patent/TWI301588B/zh

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    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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Description

1301588 ⑴ 玖、發明説明 (發明說明應敘明:發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) (1) 技術領域 本發明係關於有一 1C晶片配置其上的一種模組,以及其 組裝時的封裝技術。具體而言,本發明係關於一半導體模 組’其可縮減厚度而仍能提供其周邊零件對環境條件的高 4賴度,且係關於其生產方法以及IC卡與其類似物之模組。 (2) 先前技術 近來已出現各種配備半導體積體電路裝置的1〇卡,用於 諸如巴士、鐵路等大眾運輸工具之通勤票,以及包括銀行 ***之類金融卡或身分識別卡。由於_IC卡本身具有磁 卡所無的資料處理功能以及高度保全功能,故此優點使其 應用面更為寬廣。 ' 1C卡可分為 P接觸型、非接觸型以及同時呈有^ 述二型功能的組合型。就第一型(接觸型)IC卡而言;、在) 配備有 一 IC 晶片的一>fHi| ^ a lL a
乃旳側之月面具有一些電極,此類電極S 3 =巧取器/寫入器裝置進行機械接觸,並邮 A 」h子。反之,就第二型(非接觸型)1C卡而·! ’二一天線(諸如—捲繞型嵌入物或蝕刻線圈型嵌入物 ’並透過該天線接收電磁波’以非接觸方式自-讀^ 寫入盗裝置獲取供電並與之交換資料。 ° 情況下Ic卡皆係置於衣服口袋、皮夾、通勤 =㈣之中,故對其可攜性有極強烈需求。 攜性’則必須使IC卡模組變薄, ” ㈣卡才較易攜帶。為達成薄型㈣;肖於一 乂,寻生、σ構的要求,則必須使該 1301588
1C卡模組的組成要素(即其印刷線路板、IC晶片、焊接線( 尤其線環的南度)及密封樹脂)越薄越好。 然而,當已使該印刷電路板變薄,則安裝IC晶片後之處 理效能將在模組製造的封裝過程中惡化。結果,目前的生 產極限約為100 μπι(微米)。當使用諸如QFp(Quad Flat Package,四面平整包裝)、S0P(Slnall 0utline Package,小 型包裝)、CSP(Chip Size Package,晶片尺寸封裝)等的典型 半導體封裝之ic晶片時,其產品必然會變成最小約2〇〇 μπι 厚以上。線環形成的高度約離1〇晶片頂上15〇 ,故當以 樹脂密封該ic晶片與焊線時,必須形成由IC晶片表面算起 約200 μηι以上厚度的樹脂填料。 若企圖使這些元件變薄,則該1(:晶片將因彎折負載而斷 裂,並因此引起使該IC片之電路故障的嚴重缺陷。當縮減 密封樹脂的厚度時,若其環氧樹脂所含填充物量較低,則 整個模組將因樹脂中的應力而變得容易變形,因此將使一 接觸型1C卡的電氣端子表面呈現不平整光滑的現象,造成 其與項取盗/寫入器裝置之電性連接端子間的接觸失效。另 -方面,若該環氧樹脂包含大量填充物,則其將展現不良 的流動性,因而產生未填充部分。 在曰本專利申凊公開案號Hei i 以下稱為第一 項先前技術)以及日本專射請公開案號Hei 11 238744(以 下稱為第二項先前技術)等之中’已揭示用以產生具有必要 之機械強度的薄型職組的密封技術。具體而纟,日本專 J申請公開案號Hei 11 _296638(第-項先前技術)所揭示之 -6 - 1301588
(3) 技術,為在一凹陷之外殼内密封一 Ic晶片及其周邊零件, 並在其内保留一空洞。 圖1顯示此種技術的一模組之斷面結構。本圖中所示模組 具有一 1C晶片4,其係配置於一印刷線路板2〇之上,同時IC 曰曰片4的各電極係藉導線5與印刷線路板2〇的預設端子電性 連接,再由一凹陷的外殼17將其覆蓋,以隔離並保護…晶 片4與導線5避免其與外部空氣接觸。在此項技術中,凹陷 之外殼17係使用彈性係數較單結晶矽為高的材料,以保護 1C晶片4並強化該模組。 然而,在此項先前技術中,係僅將印刷線路板2〇與凹陷 之外殼17間的介面黏合以包裝該模組,而IC晶片4與導線5 則仍處於該空洞中。當此種結構的模組形成一…卡模組卡 ,並對其實施變形、扭轉及其他機械測試時,印刷線路板 20與凹陷知外殼17間的介面可能破裂,使水可輕易由裂縫 流入。另外,若係採用諸如玻璃環氧化物、聚醯亞胺 (polyimide)之類的一有機基板,則水氣吸收、環境溫度降 低以及内部空氣的凝結等的重複循環將導致水氣凝結:該 空洞空間内1C晶片4及其周邊零件的四周,因該有機基板I 身即易於讓水氣穿透。因此,為改善其機械強度,以對抗 彎折、變形、扭曲等,即必須提供一種機械強度夠高的結 構。 曰本專利申請公開案號Hei 11_238744(第二項先前技術) 中揭示了 一種密封技術,其中有一 c晶片4以一未固化密封 树月曰封I,並以一圓盤(稱為一頂箔(t〇pping f〇il) 1 8)覆蓋後 1301588 再予固化’該圓盤係藉一衝模工具由一環氧化物或聚醯亞 胺樹脂薄膜切割而得。圖2顯示此種先前技術模組結構的斷 面。本圖中所示的模組之建構方式為··在-印刷線路板20 上配置一1C晶片4 ;將印刷線路板20之各端子與1C晶片4的 預叹電極電性連接;於該晶片上塗佈一液態樹脂i 9然後放 置一薄片,即頂箱18,以獲得一光滑表面。 、依據此種技術,可藉放置頂箱18於液態樹脂19上,以改 善該模組厚度的可控制性。另外,頂箔18亦可作為一補強 疋件,從而改善對衝擊的抵抗能力。 在曰本專利申請公開案號Hei 11-296638(第一項先前技 峨揭示的方法中,在使用倒裝晶片裝配程】= (hip On board,晶片直接裝於基板)導線焊接程序將IC晶 =4裝配於印刷線路板20上之後,在該印刷線路板上的該IC 曰曰片4與其周邊零件係由凹陷之外殼丨7沿著其邊緣密封。 不過,雖然凹陷之外殼17係由具有極低滲透性之材料所 構成,但若凹陷之外殼17内部有一空洞,則水氣將透過黏 =表面或透過印刷線路板2〇(其通常係由玻璃環氧化物、聚 j亞fee或其他有機化合物構成)渗透,且該空洞中的溫度亦 ㈢^加。例如,若該模組係在30°C、相對濕度(RH)70%的 ^部環境下使用,則凹陷之外殼17内的水氣很快就會與外 部環境者相當。當由此種狀態冷卻時,其中的水氣將會凝 結,並造成1C晶片4表面互連電路以及印刷線路板2〇中的漏 電’導致操作錯誤。 在曰本專利申請公開案號Hei 11-238744(第二項先前技 1301588
(5) 術)中,頂箔1 8係由一衝模工具所切割,再將其置放並固化 以完成密封。此頂箔18係作為調整該IC卡模組樹脂密封的 间度並提供補強功能的用途,但並不會提供任何對外界環 境的防護。 發明内容 本發明係針對上述問題所設計,因此,本發明的一項目 標為提供一種半導體模組,其能防止當暴露於一嚴厲環境 (諸如高溫高濕之儲存環境、高溫高濕並有一偏壓之環境、 加壓洛Π裱境等,相當於對IC模組環境耐受試驗的條件) 時發生故障以及水氣滲透的狀況,並能在實際環境耐受試 f中減少故障的發生,從而改善產能並改善在實際使用環 ^中的信賴度。亦即,本發明之目標為提供此種半導體模 組及其生產方法,以及積體電路卡與其類似物之模組。 為達成以上目標,本發明之内容如下·· 依據本發明的第一項觀點,一半導體模組包括:由一絕 緣體,成且在其兩侧各有導體圖案形成的—印刷線路板, 以f安裝於該印刷線路板上且係由一樹脂所密封的一半導 體晶片,其特徵為,在該半導體晶片背對該印刷線路板一 側的表面上,黏接有一金屬片或水氣滲透阻擋片。 、曾-康本么月之苐一項觀點,具有上述第一項特徵的該半 導體模組進-步包括天線連接端子,其係配置於該印刷線 路板具有该半導體晶片之表面,及/或包括配置於安裝有該 半導體晶片表面的背面底下之電性連接電極。 依據本發明之第三項觀點,具有上述第一項特徵的該半 (6) 1301588
導體模組之特徵為, 銘或鋼所構成。 該金屬片係由不銹鋼、42鐵鎳合金、 依據本發明之第四項 . 導體握如—⑼ /、旁上迷弟一項特徵的该+ 成。”、徵為,水氣渗透阻擔片係由氧化銘陶究所構 依據本發明 導體之特徵為 或更薄。 之第五項觀點,具有上述第一項特徵的該半 ’該金屬片或水氣滲透阻擋片的厚度為1〇〇
導:? 二發明之第六項觀點,具有上述第-項特徵的該 該金屬二特徵為,有一黏接層用以黏接該半導體晶片 ^更薄玄水氣滲透阻擋片,且該黏接層的厚度為30 依據本發明之第 導體模組之特徵為 物所構成。 七項觀點,具有上述第一項特徵的該半 ’該金屬片未黏接之表面係凹口與突出
:本發明之第八項觀點,將一半導體晶片裝配於由一 :二-構成且兩側各有導體圖案形成的一印刷線路板,並 丰:配:该半導體晶片的該印刷線路板以一樹脂密封的一 ¥體杈、、且生產方法所包括步驟為··將該半導體晶片裝配 P刷線路板上;使用導線進行此二者間之電性連接; ^黏接層在一金屬片或一水氣滲透阻擋片與該半導體晶 表面之間黏接,然後在該印刷線路板裝配有該半導體晶 片的一側以一封膠樹脂覆蓋密封。 依據本發明之第九項觀點,將一半導體晶片裝配於由一 -10- 1301588
⑺ 絕緣體構成且兩側各有導體圖案形成的一印刷線路板,並 將裝配有該半導體晶片的該印刷線路板以一樹脂密封的一 半導體模組生產方法所包括步驟為··在黏接於該半導體晶 片表面上的該金屬片或水氣滲透阻擋片的一侧上形成凹口 與突出物,然後在該印刷線路板裝配有該半導體晶片的一 侧以一封膠樹脂覆蓋密封。 依據本發明之第十項觀點,具有上述第八項特徵的半導 體模組生產方法之特徵為,該印刷線路板與該半導體晶片 間的導線電性連接係經由正常導線焊接,或首先以球形焊 接(ball bonding)將導線焊接於該半導體晶片之各電極上, 然後再以汀合式焊接(stitch b〇nding)將各導線焊接於該印 刷線路板預設之端子上。 依=本發明之第十_項觀點,具有上述第九項特徵的半 導體杈組生產方法之特徵為,該印刷線路板與該半導體曰 片間的導線電性連㈣經由正常導線焊接,或首先以球: ^將導線焊接於該半㈣晶片之各電極上,^後再以訂 «式焊接將各導線焊接於該印刷線路板預設之端子上。 2本發明之第十二項觀點,具有上述第人項特徵的半 導體模組生產方法之姑^ μ & . 特徵為,该印刷線路板與該半導體晶 、、¥線電14連接係經由反向導線焊接,或首 铁$ =㈣接將‘線焊接於該印刷線路板預設之端子上, =再以訂合式焊接將各導線焊接於該半導體晶片之各電 依據本發明之第十三項觀點 具有上述第九項特徵的半 1301588
(8) 導體模組生產方法之特徵為,該印刷線路板與該半導體晶 片間的導線電性連接係經由反向導線焊接,或首先以球形 焊接將導線焊接於該印刷線路板預設之端子上,然後再以 訂合式焊接將各導線焊接於該半導體晶片之各電極上。 依據本發明的第十四項觀點,一種包含一半導體模組的 1C卡之類模組,其包括:由一絕緣體構成且在其兩侧各有 導體圖案形成的一印刷線路板,以及安裝於該印刷線路板 上且係由一樹脂所密封的一半導體晶片,其中在該半導體 晶片背對該印刷線路板一側的表面上,黏接有一金屬片或 水氣滲透阻擋片。 此處,該1C卡之類模組可能為一非接觸型、接觸型或同 時具有前述二型功能的組合型。該IC卡之類模組係主要用 於1C卡模組中,但其用途不應僅限於此,而可應用於其他 目的。 ’、 實施方式 接著請參考圖3及其他圖式,其中將說明依據本發明的半 導體模組和其生產方法以及一 IC卡之類模組等之各種較佳 具體實施例。 一雙面印刷線路板20包括用於聚醯亞胺雙面互連之一絕 緣層8,由玻璃環氧化物灌注以環氧樹脂製成,厚度為別 至100 μιη ,以及黏接於該絕緣體兩側諸如銅箔之類的一導 體’其可由#刻或其他程序圖案化(形成下述模組中的天線 連接端子7及印刷線路板20之預設端子11)(>此導體之特定 厚度為8至20 μπι。 -12- 1301588
在此項具體實施例中,係以兩面具有12 μπι厚度之導體層 的一玻璃環氧化物基板作為範例,但只要其落於上述範圍 ,即不應將該導體限制於特定厚度。 在印刷線路板20上鑽有若干貫通孔9以作兩側導體層間 的電性連接,並於兩側以電鍍形成1〇 μηι厚度的導體層。如 此形成的導體層再由蝕刻之類的方法圖案化,以完成印刷 線路板2 0。 在此項具體實施例中所示的印刷線路板20具有80 (^⑺厚 度的一絕緣層8。 由一典型晶圓製造程序處理的1C晶片4具有400至700 μηι 的厚度’但就圖9中所示的一 1C卡模組16而言,其晶圓底部 經過研磨,使所產生之1C晶片4具有50至200 μπι的厚度。以 下將以厚度研磨至80 μπι的一晶圓作為實例說明。在該晶圓 底部先以一厚度10至50 μηι的薄膜黏著劑1〇塗佈。以一鑽石 刀之類將該晶圓切割成個別晶片,再將包含黏著劑丨〇的每 一 1C晶片4裝配於印刷線路板2 0上。黏著劑1 〇可使用熱固化 樹脂、熱熔塑膠樹脂或二者之混合物,並於必要溫度及壓 力下塗敷。 用於1C晶片4的黏著劑10可事前塗敷於印刷線路板2〇之 預设位置上。此處用於1C晶片4的黏著劑1 〇之特定厚度為3 〇 μπι。 圖8之結構斷面圖顯示本發明的一半導體模組16,嵌入於 一 1C卡基板15内,圖9則為圖8所示之1C卡的一平面圖。 接著,使用直徑20至30 μηι的極細鋁或金質導線,將IC晶 1301588
片4的預設電極連接至印刷線路板2〇上的預設端子u。在圖 3所示之組態中,使用金質導線5的導線焊接係由一般稱作 「正常焊接」的方法所執行。在此方法中,係先將金質導 線5連接至1C晶片4的一預設電極處,再將導線5的另一端連 接至印刷線路板20的相關端子^上。當使用金質導線5時, 需先在1C晶片4的預設電極上形成金球。 當然,亦可使用反向焊接,即首先以球型焊接將導線5連 接至印刷線路板20之預設端子丨丨處,然後再以訂合式焊接 將導線5的另一端連接至…晶片4的預設電極4上。在此狀況 中,需先使金球形成於印刷線路板2〇之預設端子^上,以 讓该等導線連接。採用此種反向焊接程序,可降低導線5 的焊接高度(線環高度),如圖4中所示。由圖3與4比較可明 顯看出,由於1C晶片4的電極側並未配置任何金球,故可在 1C晶片4的整個表面上配置如下述的一薄片2以防止水氣滲 透。 ^ 接著,為達成本發明的主要目標,即防止外部水氣滲透 至内部,故使用厚度50 μπι以下的一黏著劑3將厚度等於或 小於100 μηι的一薄片2黏附於IC晶片4的表面上,然後,π 晶片4的安裝面再以一封膠樹脂(由代號丨表示)密封。此薄 片2可為由不銹鋼、42鐵鎳合金、鋁、銅或其他金屬所構成 之薄片,或可為氧化鋁陶瓷材料製成的一水氣滲透阻擋片 ,以防止水氣滲透。此處之薄片2的厚度設定為80 μπι,而 黏著劑3的厚度則設定為30 μηι 〇 接著,下文將參考圖5來說明本發明的第二項具體實施例 -14- 1301588
〇1) 。圖5中,薄片2的樹脂密封表面係以蝕刻、機械加工或其 他程序形成若干凹口及突出物。其餘組態係與上述具體實 施例相同,故在此省略其說明。 依據此項具體實施例,重複出現的凹口與突出物可大幅 提昇其黏著強度。 依據上述組態,因防止水氣滲透的薄片2係與形成有效電 路的1C晶片4之頂部表面緊密接觸,故可有效地阻擋水氣滲 透穿過作為密封樹脂的環氧樹脂〗之主體。換言之,應用不 銹鋼、42鐵鎳合金、鋁、鋼或氧化鋁陶瓷構成且厚度為% 以下的薄片2,將可完全阻斷穿過具有黏著劑3的lc晶片4 上方的水氣滲透,將1C晶片4與環氧樹脂i隔離,從而使任 何滲透水氣凝結物皆無法穿透環氧樹脂〗到達IC晶片4的介 面。 =將此模組加入IC卡模組16中時,本發明之模組較之僅 以裱氧樹脂1密封1C晶片4的組態擁有較佳結構,能提供改 良的機密性,因即使用具有樹脂溶解能力的化學藥劑(諸如 熱的濃硫酸、發煙硝酸等)解除環氧樹脂丨的密封,其内部 結構或1C晶片4表面上的電路形成面亦無法得見。另外,因 1C晶片4的電路一般皆係形成於一矽基板上,用來防止水氣 自外邠今透的该薄片2亦可提供加強功能以改善其強度,防 止變薄的1C晶片4彎折。
\/ 圖3至5中所示的丨〇卡模組16配置有一調諧電容器6。此調 諧電容器6與透過天線端子7連接的一天線結合,可構成用 於非接觸通訊的一調協電路,在將該模組當作非接觸型工C -15- 1301588
(12) 卡時使用。若該模組係專門用於接觸型1(:卡,則可省略該 元件。 如上所述’即可完成1C卡模組16,但對非接觸型1C卡或 供非接觸與接觸型使用的組合型1(:卡,則必須有一外部通 訊天線與該等連接端子一起形成。 圖6顯示一組合型1(:卡16的結構平面圖,其包含具有外部 端子的一調協晶片電容器6,安裝於共同樹脂密封區域内。 亦即’圖6中所示的結構包含用以連接至一天線及調協電容 器以供非接觸通訊用的端子,並包含四組用於接觸通訊的 電極14形成於如圖7中所示的底部。 詳細而言’薄片2係藉黏著劑3黏附於IC晶片4上,而IC晶 片4的^線^子13與包含絕緣層8的印刷線路板2〇之導線端 子12則係由導線5所焊接。整各結構由環氧樹脂丨所密封, 以覆蓋調協電容器6。另外,印刷線路板2〇上亦配置有傳送 /接收天線連接端子7。 此項具體實施例中之1C卡模組16成品的個別零件厚度如 下。印刷線路板20之絕緣層8的厚度係設定於8〇 μπ^由於 该導體(即銅)係預先加於印刷線路板2〇的絕緣層8之兩側 然後進行貝通孔9的電鍍以電性連接印刷線路板2〇之兩側 一者與後者二導體的厚度各為12(^111與1〇)11111。因此,在 貫通孔電鍍之後,印刷線路板2〇之絕緣層8兩側所形成導體 的厚度總計為:(12+10)χ2=44 μηι。因此,印刷線路板2〇 的厚度總計為124 μηι。1C晶片4為80 μηι厚,IC晶片4的黏 著劑10為30 4瓜厚,而薄片2則為80 μπι厚。因此,個別厚 -16- 1301588 度計算如下: 印刷線路板20包含導體的厚度=124 μηι。 1C晶片4+黏著劑10=110 μηι 薄片2 +黏著劑3 = 110 μηι 總厚度=344 μιη。 在上述結構以下注塑形(transfer molding)用環氧樹脂1密 封的情況中,如圖3至6所不’為讓樹脂獲得較佳的流動性 則另需100 μιη的厚度,因此所得的1C模組16總厚度成為344 μηι +100 μιη =444 μηι 〇 由於配置了薄片2以阻擔水氣渗透,故依據本發明之ι匸卡 模組16即可在處於嚴苛環境時防止因水氣渗透產生的操作 故I5早,此類嚴可%境包括一南溫高濕儲存環境(6〇〇C 9〇%rh 或8 5 C 8 5%RH)、尚溫尚濕並有一偏壓之儲存環境(在6〇 ο。 90%RH或85°C85%RH環境的偏壓測試時,施加有一兩倍 於最大額定之電壓),或加壓蒸汽環境(丨2丨t、2 atm及 100%RH)。因此,即可在1(:卡模組16的環境測試時降低故 障的發生率,從而改善生產量並改善使用環境中的信賴度。 毋庸贅吕,1C卡模組16的成品係就Ic晶片4的電氣特性加 以測試。 如前所述,依據上述具體實施例,能阻絕對lc卡模組16 之1C晶片4表面水氣滲透的薄片2係以甚小厚度之黏著劑3 黏附’然後再以下注塑形程序將環氧樹脂以入該㈣。因 此’即可建立-堅固的模組配置,並產生具有極佳之極端 ¥境耐受能力的IC卡模組16之結構。由於個別元件係依據 -17- 1301588 (14)
上述特疋厚度製造’故包含此種1c卡模組16的該1C卡即可 進一步改善其可攜性,並可容納於一極薄的組態中。 至於對特定環境的耐受性能,依據本發明之IC卡模組可 在相當於環境耐受試驗的嚴苛環境時消除因水氣滲透產生 的操作故障,此類嚴苛環境包括一高溫高濕儲存環境(6〇χ: 9〇%RH或85t:85%RH)、高溫高濕並有一偏壓之儲存環境( 在6〇C90%RH或85°C85%RH環境的偏壓測試時,施加有一 兩倍於最大額定之電壓),或加壓蒸汽環境(12rc、2 atm. 及l〇〇%RH)。此種對環境的高度耐受性使其可在出貨前的 環境耐受測試時降低故障的發生率,從而改善生產量並改 善實際使用環境中的信賴度。
另外’由於薄片2提供了強化功能以彌補 上的1C晶片4之變薄而降低的抗彎折強度, 在(例如)將該模組製作成甚薄的狀態時, 的方式維持其機械強度。 因安裝於該模組 故此種配置即使 亦能以明顯有效 再者 談及1C卡模組16結構上的一項重要特性 ^ W ,只里晋符性,即使 化學藥劑(諸如熱的濃硫酸、發煙確酸等)解除環氧樹月^ 封劑的密封,薄片2仍然難以溶解,故其能提供耐化學曰 的阻絕層的功能。因此,即無法輕易看見該模組之^晶」 的表面電路結構’故此種配置將能提供非凡的安全; 結果,即使將其應用於特重安全的ic卡中明 模組亦能提供無限的效用。 x月
如前所述,依據本發明,即使在該IC卡模組 試驗中經歷諸如-高溫高濕儲存環境、高溫高濕並有— -18- (15) (15)1301588 = 境、加壓蒸汽環境等,仍能防止伴隨水氣渗透 〜的㈣。另外,達到上述效用使其可在以上述條件進 際%境耐受測試時降低故障的發生率,從而改善生產 量並改善實際使用環境中的信賴度。 ^ 圖式簡單說明 圖1之斷面圖顯示第一項先前技術所揭示的傳統技術之 結構; 圖2之斷面圖顯示第二項先前技術所揭示的另一項傳統 技術之結構; 、、 圖3為本發明一項具體實施例的半導體模組結構的斷面 圖; 圖4為本發明另一項具體實施例的半導體模組結構的斷 面圖; 圖5為本發明另一項具體實施例的半導體模組結構的斷 面圖; 圖6為本發明一項具體實施例的半導體模組之平面圖; 圖7之平面圖顯示本發明之一半導體模組之一項具體實 施例’在其1C晶片安裝表面之背面上的電極部分; 圖8為一結構斷面圖,顯示本發明之一半導體模組嵌入於 一 1C卡基板中;以及 圖9為圖8所示之1C卡的平面圖。 -19- 1301588 (16) 圖式代表符號說明 1 封膠樹脂 2 薄片 3 黏著劑 4 1C晶片 5 導線 6 調諧電容器 7 天線連接端子 8 絕緣層 9 貫通孔 10 薄膜黏著劑 11 端子 12 導線端子 13 導線端子 14 電極 15 1C卡基板 16 1C卡模組 17 凹陷的外殼 18 頂箔 19 液態樹脂 20 印刷線路板 -20-

Claims (1)

13〇1挪&年_ F'-'n 拾、申請專利範圍 1 · 一種半導體模組,其包括: : 由一絕緣體製成之一印刷線路板,其兩面皆有導體 案形成;以及 ^ 安裝於該印刷線路板上並以一樹脂密封的一半導體 晶片, 其特徵為在該半導體晶片背對該印刷線路板的一側表 面上黏附有一金屬片。 、 2. 3. 5. 6. 7. 8. 如申請專利範圍第丨項之半導體模組,進一步包括天線 連接端子,其係配置於該印刷線路板配置有該半導體晶 片之表面,及/或包括配置於安裝有該半導體晶片之表面 的背面底下之電性連接電極。 如申請專利範圍第1項之半導體模組,其中該金屬片係 由不銹鋼、42鐵鎳合金、鋁或銅所形成。 如申請專利範圍第1項之半導體模組,其中非透明水氣 滲透阻擋片係由氧化鋁陶瓷所形成。 如申請專利範圍第1項之半導體模組,其中該金屬片或 非透明水氣滲透阻擋片之厚度為1〇〇 μιη或更薄。 如申請專利範圍第丨項之半導體模組,其中配置一黏著 劑層用以黏接該半導體晶片與該金屬片或非透明水氣 參透阻擋片,且該黏著劑層之厚度為3〇 或更薄。 如申請專利範圍第1項之半導體模組,其中該金屬片之 未黏接表面係形成若干凹口及突出物。 一種半導體模組生產方法’其中有一半導體晶片安裝於 81498-951215.doc
1301588 n緣體製成且兩面皆有導體圖案形成的—印刷線 路板上’然後將其上錢有該半導體晶片之印刷線路板 以一樹脂密封,該方法包括以下步驟: 將違半導體晶片安裝於該印刷線路板上; 以導線執行此二者間之電性連接;以及 黏接一金屬片於該半導體晶片表面,其間以_點著劑 層黏附,然後在該印刷線路板安裝有該半導體晶 側以一封膠樹脂覆蓋密封。 Βθ 、 9. -種半導體模組生產方法,其中有—半導體晶片安裝於 由-緣體製成且兩面皆有導體圖案形成的 路板上’然後將其上安裝㈣半導體晶片之印刷線路ί 以-樹脂密封’該方法包括以下步驟: %路板 在黏附於該半導體晶片表面的-金屬片之-側形成 凹口與突出物,然後在該印刷線路板安裝㈣半導艘^ 片的一側以一封膠樹脂覆蓋密封。 a:申j專利範圍第8項之半導體模組生產方法 導線在該印刷線路板與該半導體晶片間表 由正常導線焊接所執行’或首先以球形焊接將導 11 導線焊接於該印刷線路板預設之端子上。 妾將各 範圍第9項之半導體模組生產方法,其中以 導線在该印刷線路板與 ? ^ 由正常導線焊接所執行、 _、曰曰Β、電性連接係 於該半導體晶片之各電2 ^球形焊接將導線Μ 各電極上,然後再以訂合式焊接將 81498-95I215.doc 1301588 12. 13. 14.
^線烊接於該印刷線路板預設之各端子上。 如申請專利範圍第8項之半導體模組生產方法,I中以 導線在該印刷線路板與該半導體晶片間的電性連接係 由f向導線焊接所執行,或首先以球形焊接將導線焊接 於口亥印刷線路板預設之各端子上,然後再以訂合式焊接 將各導線焊接於該半導體晶片之各電極上。 :申請專利範圍第9項之半導體模組生產方法,其中以 導線在該印刷線路板與該半導體晶片間的電性連接係 由反向導線4接所執行,或首先以球形焊接將導線焊接 於該印刷線路板預設之久山工 攸頂叹之各ί而子上,然後再以訂合式焊接 將各導線焊接於料導體晶片之各電極±。 -種包含-半導體模組的IC卡之類模組,其包括:由— 、巴.,彖體製成之-印刷線路板,其兩面皆有導體圖案形成 :以及安裝於該印刷線路板上並以—樹脂密封的一半導 體晶片’其中在該半導轉日i 曰日片者對§亥印刷線路板的一側 表面上黏附有一金屬片。 81498-951215.doc
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Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6919646B2 (en) * 2002-03-12 2005-07-19 Nec Electronics Corporation Semiconductor device with contacting electrodes
WO2004042868A1 (en) * 2002-11-07 2004-05-21 Fractus, S.A. Integrated circuit package including miniature antenna
EP1594163A1 (en) * 2004-05-03 2005-11-09 Commissariat A L'energie Atomique A screened electrical device and a process for manufacturing the same
JP2005332158A (ja) * 2004-05-19 2005-12-02 Kyodo Printing Co Ltd Icモジュール及びicカード
US8330259B2 (en) * 2004-07-23 2012-12-11 Fractus, S.A. Antenna in package with reduced electromagnetic interaction with on chip elements
JP2007004775A (ja) * 2005-05-23 2007-01-11 Toshiba Corp 半導体メモリカード
JP4610613B2 (ja) * 2005-05-24 2011-01-12 富士通株式会社 Icタグの実装構造および実装用icチップ
JP2007073849A (ja) * 2005-09-08 2007-03-22 Sharp Corp 電子回路モジュールとその製造方法
US8196829B2 (en) * 2006-06-23 2012-06-12 Fractus, S.A. Chip module, sim card, wireless device and wireless communication method
JP2008171927A (ja) * 2007-01-10 2008-07-24 Renesas Technology Corp 半導体装置
US8018064B2 (en) * 2007-05-31 2011-09-13 Infineon Technologies Ag Arrangement including a semiconductor device and a connecting element
US20090115070A1 (en) * 2007-09-20 2009-05-07 Junji Tanaka Semiconductor device and method for manufacturing thereof
DE102008031231B4 (de) * 2008-07-02 2012-12-27 Siemens Aktiengesellschaft Herstellungsverfahren für planare elektronsche Leistungselektronik-Module für Hochtemperatur-Anwendungen und entsprechendes Leistungselektronik-Modul
CN102171816B (zh) * 2008-10-03 2013-09-25 松下电器产业株式会社 配线板、半导体装置及其制造方法
WO2010068511A1 (en) * 2008-11-25 2010-06-17 Kovio, Inc. Tunable capacitors
CN101847591B (zh) * 2009-03-27 2012-03-21 王海泉 一种在条带上实现多芯片封装的方法
TWI401773B (zh) * 2010-05-14 2013-07-11 Chipmos Technologies Inc 晶片封裝裝置及其製造方法
US8917511B2 (en) * 2010-06-30 2014-12-23 Panasonic Corporation Wireless power transfer system and power transmitting/receiving device with heat dissipation structure
CN102655715B (zh) * 2011-03-02 2016-05-11 三星半导体(中国)研究开发有限公司 柔性印刷电路板及其制造方法
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
JP6048910B2 (ja) * 2011-11-14 2016-12-21 住友電気工業株式会社 リアクトル、コイル成形体、コンバータ、及び電力変換装置
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
JP5951361B2 (ja) * 2012-05-31 2016-07-13 株式会社東芝 無線通信装置
DE102013205138A1 (de) * 2013-03-22 2014-09-25 Infineon Technologies Ag Halbleiterbauelement, Halbleitermodul sowie Verfahren zur Herstellung eines Halbleiterbauelements und eines Halbleitermoduls
JP6119664B2 (ja) * 2014-05-14 2017-04-26 株式会社オートネットワーク技術研究所 回路構成体および電気接続箱
TWI591707B (zh) * 2014-06-05 2017-07-11 東琳精密股份有限公司 薄型化晶片之封裝結構及其製造方法
CN105280572A (zh) * 2014-06-05 2016-01-27 东琳精密股份有限公司 薄型化芯片的封装结构及其制造方法
DE102015102453A1 (de) * 2015-02-20 2016-08-25 Heraeus Deutschland GmbH & Co. KG Bandförmiges Substrat zur Herstellung von Chipkartenmodulen, Chipkartenmodul, elektronische Einrichtung mit einem derartigen Chipkartenmodul und Verfahren zur Herstellung eines Substrates
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
DE102016106698A1 (de) * 2016-04-12 2017-10-12 Infineon Technologies Ag Chipkarte und Verfahren zum Herstellen einer Chipkarte
CN110600496A (zh) * 2019-09-20 2019-12-20 上海显耀显示科技有限公司 一种Micro-LED芯片封装结构
KR102345062B1 (ko) * 2019-11-20 2021-12-30 (주)에이티세미콘 반도체 패키지 및 그 제조 방법

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6076040A (ja) 1983-09-30 1985-04-30 Nec Home Electronics Ltd 対物レンズ支持装置
JPS60186985A (ja) * 1984-03-06 1985-09-24 Toshiba Corp Icカ−ド
JPS61159746A (ja) * 1985-01-08 1986-07-19 Kyodo Printing Co Ltd Icモジユ−ルのワイヤボンデイング方法
JPS61169746A (ja) 1985-01-23 1986-07-31 Sumitomo Metal Ind Ltd 赤外線式水分測定装置
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
JPH04280459A (ja) * 1991-03-08 1992-10-06 Matsushita Electron Corp 樹脂封止型半導体装置
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
JPH06163755A (ja) 1992-11-24 1994-06-10 Mitsubishi Electric Corp 樹脂封止型半導体装置
US5430331A (en) * 1993-06-23 1995-07-04 Vlsi Technology, Inc. Plastic encapsulated integrated circuit package having an embedded thermal dissipator
KR970005712B1 (ko) * 1994-01-11 1997-04-19 삼성전자 주식회사 고 열방출용 반도체 패키지
JPH07288263A (ja) * 1994-04-19 1995-10-31 Nitto Denko Corp 半導体装置の製造方法および金属箔材料
US5969414A (en) * 1994-05-25 1999-10-19 Advanced Technology Interconnect Incorporated Semiconductor package with molded plastic body
US5972736A (en) * 1994-12-21 1999-10-26 Sun Microsystems, Inc. Integrated circuit package and method
KR0119757Y1 (ko) * 1994-12-27 1998-07-01 문정환 반도체 패키지
US5786738A (en) * 1995-05-31 1998-07-28 Fujitsu Limited Surface acoustic wave filter duplexer comprising a multi-layer package and phase matching patterns
JP3210835B2 (ja) * 1995-06-07 2001-09-25 京セラ株式会社 半導体素子収納用パッケージ
US5705851A (en) * 1995-06-28 1998-01-06 National Semiconductor Corporation Thermal ball lead integrated package
WO1997002596A1 (fr) * 1995-06-30 1997-01-23 Kabushiki Kaisha Toshiba Composant electronique et son procede de fabrication
JP3007833B2 (ja) 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
US5736785A (en) * 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
JPH11102985A (ja) * 1997-09-26 1999-04-13 Mitsubishi Electric Corp 半導体集積回路装置
JPH11238744A (ja) * 1998-02-20 1999-08-31 Toppan Printing Co Ltd Icカード等用icモジュールの封止方法
JPH11296638A (ja) * 1998-04-10 1999-10-29 Nippon Telegr & Teleph Corp <Ntt> Icカード
JP4215886B2 (ja) 1999-02-03 2009-01-28 ソニー株式会社 半導体集積回路チップの封止方法、半導体集積回路カードの製造方法
JP2000155822A (ja) * 1998-11-19 2000-06-06 Toppan Printing Co Ltd 非接触型icカード
TW411595B (en) * 1999-03-20 2000-11-11 Siliconware Precision Industries Co Ltd Heat structure for semiconductor package device
JP4649688B2 (ja) * 1999-04-28 2011-03-16 凸版印刷株式会社 非接触式icカード
JP2001109860A (ja) 1999-10-05 2001-04-20 Toshiba Chem Corp データキャリアおよびその製法
FR2799883B1 (fr) 1999-10-15 2003-05-30 Thomson Csf Procede d'encapsulation de composants electroniques
TW452956B (en) * 2000-01-04 2001-09-01 Siliconware Precision Industries Co Ltd Heat dissipation structure of BGA semiconductor package
US6559525B2 (en) * 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
KR100522838B1 (ko) * 2000-10-23 2005-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조방법
US6734552B2 (en) * 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package

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