TWI287264B - Under bump metallization layer to enable use of high tin content solder bumps - Google Patents

Under bump metallization layer to enable use of high tin content solder bumps Download PDF

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Publication number
TWI287264B
TWI287264B TW094109496A TW94109496A TWI287264B TW I287264 B TWI287264 B TW I287264B TW 094109496 A TW094109496 A TW 094109496A TW 94109496 A TW94109496 A TW 94109496A TW I287264 B TWI287264 B TW I287264B
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TW
Taiwan
Prior art keywords
layer
tin
molybdenum
adjacent
barrier layer
Prior art date
Application number
TW094109496A
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English (en)
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TW200534404A (en
Inventor
John Barnak
Gerald B Feldewerth
Ming Fang
Kevin Lee
Tzuen-Luh Huang
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200534404A publication Critical patent/TW200534404A/zh
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Publication of TWI287264B publication Critical patent/TWI287264B/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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1287264 · ， (1) 九、發明說明 【發明所屬之技術領域】 本發明關於微電子製造，特別是關於允許純錫或高錫 成份倒裝晶片突塊使用的突塊下金屬化層。 【先前技術】 微電子裝置工業持續看得到技術上的大幅進展，使得 Φ 電路密度和複雜度增加，且對等地使得電力消耗和封裝尺 寸大幅減少。現行的半導體技術允許單一晶片微處理器具 有數百萬個電晶體，以每秒數十（甚至數百）個百萬指令 (MIPS : millions of instructions per second)的速率作 業，且封裝在相對小氣冷式微電子裝置封裝體內。微電子 裝置高密度和高功能的結果，就需要在微電子晶粒外部增 加外部電氣連接的數目，以將微電子晶粒連接於例如內插 板的其他組件。 φ 用於此種高密度連接的連接機構一般是球閘陣列，因 爲陣列之球或突塊的尺寸能做得比較小，以提供其高密度 ，且藉此創造從微電子晶粒的大數目連接。藉由在微電子 晶粒接合點上設置一數量的焊料，並將該焊料加熱置熔點 而形成球閘陣列。液體焊料的表面張力使得焊料形成焊料 球，當焊料球冷卻時，其形成固態的焊料球或突塊。 如圖8所示，例示的微電子封裝體包括組裝在基材 4 0 4上的一微電子晶粒4 0 2。該基材4 〇 4例如內插件、主 基板、和類似物’其作用在於藉由一系列的電氣傳導路徑 -5- 1287264 . ’ (2) (未不）’將微電子晶粒4 Ο 2連接於其他的電子組件（未 不）。所例不之將微電子晶粒4 0 2電性地組裝於基材4 0 4 的方法，稱爲覆晶結合。在此組裝方法中，使用焊料突塊 或球4 1 6，將微電子晶粒之活化表面4 〇 8上的電性傳導端 子或接合點406，直接附接於基材404之表面414上的對 應接點412。該等焊料突塊或球416被回流，以在接合點 4〇6和接點412之間形成附接。 φ 最常用於形成焊料突塊的材料是鉛/錫合金，但是需 要管制用於形成突塊的焊料中沒有鉛，因爲已知鉛對人類 有毒，因此已有從突塊的製造中移除鉛的行動。現今，大 致純的錫或高錫成份合金（9 0 %或更多的錫），例如錫/ 鉍、共晶錫/銀、三元錫/銀/銅、共晶錫/銅、和類似 物’是最適合做爲無鉛焊料突塊的材料。大致純的錫或高 錫成份合金被形成在突塊下金屬化層（U Μ Β )的上面，其 沉積在微電子晶粒接合點406上。突塊下金屬化層（UMB 鲁）提供微電子晶粒接合點4 0 6和焊料突塊4 1 6之間，可信 賴的電性和機構介面。用於含銅微電子晶粒接合點和鉛/ 錫焊料球之典型的突塊下金屬化層（UMB )包含三層：一 黏著層，供附接於微電子接合點；在該黏著層上方的一阻 擋層，以防止焊料球和微電子晶粒之間的污染；和在該阻 擋層與焊料突塊之間的一濕潤層，以濕潤或黏著於焊料突 塊材料。黏著層可包括鈦、鎳釩合金、和類似物。阻擋層 可包括鉻、氮化鈦、和類似物。濕潤層通常是鎳、銅、鈷 、金、或其合金。 -6 - 1287264 ， (3) 但是使用純錫或高錫成份合金仍然有問題，因爲錫會 和通常用於鉛/錫突塊方法的突塊下金屬化層發生反應， 且過度的反應載回流期間會導致突塊對基材污染，和/或 攻擊下方的銅構造（接合點和軌跡），此爲熟悉該項技藝 人士所了解。 解決錫對突塊下金屬化層反應的現行方法是將濕潤層 做得非常地厚（例如厚度大於5微米的鎳濕潤層），使得 φ 微電子封裝體在其後製造或使用期間必然要承受的熱應力 作用期間，濕潤層不會全部被消耗完。但是此方法和機械 性質脆的低介電常數中間層介電質材料（亦即介電常數在 二氧化矽以下的介電質材料）不相容，因爲封裝所導入的 應力傳輸到位於突塊底部之硬且厚的鎳材料，且又再導入 微電子晶粒。然後這些應力造成低介電常數中間層介電質 內聚破壞和/或低介電常數中間層介電質對蝕刻停止（ e t c h s t ο p )黏性破壞。 φ 此種和低介電常數之中間層介電質的不相容性是一個 大問題，因爲當積體電路變得越來越小時，就需要使用低 介電常數之中間層介電質材料來製成積體電路，以獲得各 互連之間的低電容。降低各互連之間的此電容產生一些優 點，包括減少RC延遲（RC delay )、降低電力消耗、和 降低各互連之間的串訊。 【發明內容】 因此，發展形成突塊下金屬化構造的裝置和技術是有 7 ⑧ 1287264 ， (4) 利的，因爲突塊下金屬化構造不會傳輸大幅的應力至鄰接 突塊下金屬化層的構造，所以可防止錫污染。 【實施方式】 在下列詳細說明中，參考了附圖。該等圖式係以例示 的方式顯示可執行本發明的特定實施例。這些實施例描述 得相當詳細，使得熟悉該項技藝人士能夠實施本發明。理 _ 應瞭解的是，本發明的各種實施例雖然不同，但不需互相 排斥。例如此處結合於一實施例所描述的形狀、構造、或 特徵，可在其他實施例中實施，而不會脫離本發明的精神 和範圍。此外，理應瞭解載所揭露之每一實施例中的個別 元件得位置和配置，可在不脫離本發明的精神和範圍內做 修正。因此，下列詳細的說明並無限制的意味，且本發明 的範圍只由適當解釋所附的申請專利範圍連同該申請專利 範圍的全部均等範圍所界定。在圖式中，類似的數字在各 φ 視圖中指相同或類似的功能。 圖1例示的倒裝晶片總成1 00包括形成傳導接合點 102的一突塊下金屬化構造120。傳導接合點102設置在 一互連構造1 〇 4內或上面，傳導接合點1 〇 2可由包括（但 不限於此）銅、鋁、和其合金等適當的傳導性材料製成。 互連構造104可爲例示成元件i〇6a、106b、106c的複數 中間介電層，且設置在一微電子晶粒（未示）上。中間介 電層106a、106b、106c可由包括（但不限於此）氧化矽 、氮化矽、和類似物及例如滲碳氧化物的低介電常數介電 -8 - ⑧ 1287264 ， (5) 質等任何適當的介電材料製成。 傳導接合點1 02經由一傳導孔1 1 2連接於一傳導軌跡 1 〇 8，如熟悉該項技藝人士所了解的，傳導軌跡1 〇 8的路 徑連接至微電子晶粒（未示）。例如氮化矽的一鈍化層 114可沉積互連構造104上，且具有圖案以暴露傳導接合 點102的至少一部份。 藉由形成一黏著層1 2 2、一阻擋層1 2 4、和一濕潤層 φ 126，突塊下金屬化構造120製成接觸於傳導接合點102 。黏著層122可形成在鈍化層1 14和傳導接合點1〇2的一 部份上面。選擇黏著層1 22以黏牢於傳導接合點1 02和鈍 化層1 1 4 ;該黏著層1 22可包括（但不限於此）鈦和其合 金。阻擋層124形成在黏著層122上面，以限制欲形成在 突塊下金屬化構造1 20上面之焊料突塊，擴散到黏著層 122、傳導接合點102、和互連構造104;該阻擋層124包 含鉬和其合金。在一實施例中，阻擋層1 24包含至少約 φ 90%的（原子）鉬。濕潤層126形成在阻擋層124上面， 以在組合期間對熔融焊料突塊提供容易濕潤的表面，以使 焊料牢固地結合阻擋層1 2 4 ;濕潤層1 2 6可包括（但不限 於）鎳、金、銅、鈷、和其合金。黏著層122、阻擋層 1 24、和濕潤層1 26可以習知技藝的任何方法形成，包括 (但不限於）磁控電子管濺鍍沉積、蒸鍍、和離子束沉積 〇 焊料栓1 2 8形成在濕潤層1 2 6上面，且焊料栓1 2 8可 包含大致純的錫或高錫成份的合金，例如錫/鉍、共晶錫 -9- ⑧ 1287264 ， (7) 圖4例示製造一金屬化層和焊料突塊之方法的示意圖 。步驟1 5 0包含提供具有至少一鄰接傳導接合點的至少一 中間層介電質。步驟1 5 2包含在至少一傳導接合點的至少 一部份上面形成一黏著層。步驟1 5 4包含在黏著層的至少 一部份上面形成一含鉬的阻擋層。步驟1 5 6包含在含鉬的 阻擋層的至少一部份上面形成一濕潤層。黏著層、阻擋層 、和濕潤層可以該技藝中任何習知的技術來形成，包括（ φ 但不限於）磁控電子管濺鍍（較佳）、蒸鍍、沉積（例如 離子束沉積）、和類似方法。步驟1 5 8包含在濕潤層的至 少一部份上面形成高錫成份的焊料栓。焊料栓可以該技藝 中任何習知的方式來形成，包括（但不限於）電鍍或網板 印刷。步驟1 60包含將焊料栓回流，以形成一焊料突塊。 圖5例示本發明之微電子封裝體170的例子，其包括 組裝在一基材174上的一微電子晶粒172。該基材174例 如內插板、主基板、和類似物，其藉由一體系的電傳導路 φ 徑（未示），將微電子晶粒1 72連接於其它的電子阻件（ 未示）。如前所述，在微電子晶粒176之活化表面176上 的傳導接合點1 02，具有設置於傳導接合點1 02上的突塊 下金屬化層120。使用焊料突塊136，突塊下金屬化層 12〇直接附接於基材174之表面184上的對應接點（land )1 82 ’該等焊料突塊1 3 6被回流以在突塊下金屬化層 120和接點（land) 182之間形成附接。 本發明所形成的封裝體可使用在如圖6所示的手持裝 置210中，例如手機或個人數位助理（Pda)。手持裝置 -11 - (8) 1287264 ' (8) 210可在一殻體240內包含具有至少一微電子裝置 2 3 0的一外部基材2 2 0 ;該微電子裝置總成2 3 0包括 不限於）一中央處理單元、晶片組、記憶裝置、特殊 積體電路（ASIC)、和類似物，且該微電子裝置總成 具有至少一個如上述的突塊下金屬化層1 20。外部 220可附接於各種周邊裝置，該等周邊裝置包括例如 250的輸入裝置、和例如液晶顯示器260的顯示裝置 g 以本發明形成的微電子裝置總成，也可用於如圖 示的電腦系統3 1 0。該電腦系統3 1 0可在一殼體或 340內包含一外部基材或主基板320，該主基板320 至少一微電子裝置總成3 3 0。該微電子裝置總成330 (但不限於）一中央處理單元、晶片組、記憶裝置、 應用積體電路（ASIC )、和類似物，且該微電子裝 成3 3 0具有至少一個如上述的突塊下金屬化層120。 基材或主基板320可附接於各種周邊裝置，該等周邊 φ 包括例如鍵盤3 5 0和/或滑鼠3 60的輸入裝置、與 CRT監視器3 70的顯示裝置。 本發明的各實施例已詳細說明。理應瞭解的是， 附之申請專利範圍所定義的本發明，並不受上述說明 載的特定細節所限制，因爲可在不脫離本發明的精神 圍下，做出許多顯然的變化。 【圖式簡單說明】 雖然說明書以申請專利範圍做結尾，該申請專利 總成 (但 應用 23 0 基材 鍵墊 D 7所 框架 具有 包括 特殊 置總 外部 裝置 例如 由所 所記 和範 範圍 -12· (9) 1287264 的請求項特別指出並請求所認爲的本發明，但是可從閱讀 下列說明連同附圖而更了解本發明的優點。附圖爲： 圖1是本發明之金屬化層的側剖視圖； 圖2是本發明之金屬化層的剖面掃描電子顯微圖； 圖3是本發明圖1之金屬化層在焊料回流後的側剖視 圖； 圖4是本發明用以製造突塊下金屬化層和微電子晶粒 上焊料的之方法的流程圖； 圖5是本發明附接於基材之微電子晶粒的側視圖； 圖6是具有本發明微電子組合體於其內之手持裝置的 斜角視圖； 圖7是具有本發明微電子組合體於其內之電腦系統的 斜角視圖；和 圖8是習知技術中附接於基材之微電子晶粒的側視圖 【主要元件符號說明】 1 〇 〇 :覆晶總成 102 :傳導接合點 104 :互連構造 1 0 6 a :中間介電層 106b:中間介電層 1 0 6 c :中間介電層 1 0 8 :傳導軌跡 -13- (10) (10)1287264 1 1 2 :傳導孔 1 1 4 :鈍化層 120:突塊下金屬化構造 122 :黏著層 124 :阻擋層 1 2 6 :濕潤層 1 2 8 :焊料栓 1 3 2 :金屬間化合物層 1 34 :介面 1 3 6 :焊料突塊 170 :微電子封裝體 172 :微電子晶粒 1 74 :基材 1 7 6 :活化表面 182 :接點 1 8 4 :表面 2 1 0 :手持裝置 2 2 0 :外部基材 23 0 :微電子裝置總成 240 :殼體 2 5 0 :鍵墊 2 6 0 :液晶顯不器 3 1 0 :電腦系統 3 2 0 :主基板 -14- (11) (11)1287264 3 3 Ο :微電子裝置總成 3 4 0 :框架 3 5 0 :鍵盤 3 6 0 :滑鼠 3 7 0 :監視器 402 :微電子晶粒 404 :基材 4 0 6 :晶粒接合點 4 0 8 :活化表面 4 1 2 :接點 4 1 4 :表面 4 1 6 :焊料突塊（球）

Claims (1)

  1. ―如曰修(更)正替· 圍 ,Ϊ287264 十、申請專利範 附件4A :第94 1 09496號專利申請案 中文申請專利範圍替換本| 民國9 5年8月 h 一種製造突塊下金屬化構造的裝置，@ 一黏著層，鄰接於一傳導接合點； 一含鉬阻擋層，鄰接該黏著層； 一濕潤層，鄰接該含鉬阻擋層·，和 筒錫成份焊接材料，鄰接該濕潤層，該高 材料具有至少75% (重量）的錫。 2 ·如申請專利範圍第1項所述的裝置， 阻擋層包含一含有至少9 0% (原子）鉬的材料 3 ·如申請專利範圍第1項所述的裝置， 成份焊接材料包含一含有至少90% (重量）的 4.如申請專利範圍第1項所述的裝置， 接合點鄰接至少一層低介電常數的介電質材料 5 ·如申請專利範圍第4項所述的裝置， 一層低介電常數的介電質材料，包含一層滲碳〖 6. 如申請專利範圍第1項所述的裝置， 層大致包攝在該高錫成份焊接材料內，且形成 合物層。 7. —種製造突塊下金屬化構造的方法，包 提供至少一中間層介電質，該中間層介電: 一鄰接傳導接合點； 23日修正 含： 錫成份焊接 其中該含鉬 〇 其中該局錫 錫。 其中該傳導 〇 其中該至少 的氧化物。 其中該濕潤 一金屬間化 含·· 質具有至少 1287264 在該至少一傳導接合點的至少一部份上形成一黏著層 9 在該黏著層的至少一部份上形成一含鉬的阻擋層； 在該含鉬的阻擋層的至少一部份上形成一濕潤層；和 在該濕潤層的至少一部份上形成一高錫成份焊料栓， 該高錫成份焊料栓具有至少75% (重量）的錫。 . 8 ·如申請專利範圍第7項所述的方法，其中形成該 含鉬阻擋層包含形成含有至少90% (原子）鉬的一含鉬 阻擋層。 9 ·如申請專利範圍第7項所述的方法，其中形成該 高錫成份焊料栓包含一含有至少9 0 % (重量）錫的高錫 成份焊料栓。 10·如申請專利範圍第7項所述的方法，更包含該傳 導接合點鄰接至少一層低介電常數的介電質材料。 11·如申請專利範圍第7項所述的方法，其中提供至 少一中間層介電質包含提供至少一層滲碳的氧化物。 12·如申請專利範圍第7項所述的方法，其中該更包 含回流該高錫成份焊料栓，以形成一焊料突塊。 13·如申請專利範圍第12項所述的方法，其中該濕 潤層在該回流期間’大致包攝在該高錫成份焊料突塊內。 14·如申請專利範圍第7項所述的方法，其中形成該 含鉬阻擋層，包含濺鍍沉積一含鉬材料。 1 5 · —種電子系統，包含： 在一殼體內的一外部基材；和 -2 - 1287264 附接於該外部基材的至少一微電子裝置封裝體，該封 裝體具有至少一突塊下金屬化層，該突塊下金屬化層包含 一黏著層，鄰接於一傳導接合點； 一含鉬阻擋層，鄰接該黏著層； 一濕潤層，鄰接該含鉬阻擋層；和 高錫成份焊接材料，鄰接該濕潤層，該高錫成份 焊接材料具有至少75% (重量）的錫；和 一輸入裝置，其與該外部基材形成介面；和 一顯示裝置，其與該外部基材形成介面。 16·如申請專利範圍第15項所述的系統，其中該含 鉬阻擋層包含一含有至少90% (原子）鉬的材料。 1 7 ·如申請專利範圍第1 5項所述的系統，其中該高 錫成份焊接材料包含一含有至少90% (重量）的錫。 1 8 ·如申請專利範圍第丨5項所述的系統，更包含該 傳導接合點鄰接至少一層低介電常數的介電質材料。 1 9·如申請專利範圍第丨8項所述的系統，其中該至 少一層低介電常數的介電質材料，包含至少一層滲碳的氧 化物。 20.如申請專利範圍第丨5項所述的系統，其中該濕 潤層大致包攝在該高錫成份焊接材料內，且形成一金屬間 化合物層。 -3-
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