TWI234827B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- TWI234827B TWI234827B TW091118453A TW91118453A TWI234827B TW I234827 B TWI234827 B TW I234827B TW 091118453 A TW091118453 A TW 091118453A TW 91118453 A TW91118453 A TW 91118453A TW I234827 B TWI234827 B TW I234827B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor wafer
- semiconductor
- wafer
- aforementioned
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 427
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000011347 resin Substances 0.000 claims abstract description 46
- 229920005989 resin Polymers 0.000 claims abstract description 46
- 239000011248 coating agent Substances 0.000 claims abstract description 33
- 238000000576 coating method Methods 0.000 claims abstract description 33
- 238000007789 sealing Methods 0.000 claims abstract description 26
- 235000012431 wafers Nutrition 0.000 claims description 376
- 239000000758 substrate Substances 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 23
- 239000007788 liquid Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 29
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 238000005452 bending Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 238000003825 pressing Methods 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005336 cracking Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 210000003625 skull Anatomy 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
1234827 五、發明說明(1) 技術領域 本發明係有關於一種半導體裝置,特別是有關於一種 具有彎曲之半導體元件之堆疊式多晶片封裝(Mcp)及多晶 片模組(MCM)之半導體裝置。 技術背景 為了使半導體裝置之集積度提升且為了使動作之速度 能高速化,一種將過去之平坦之半導體晶片變形成所需形 狀並搭載之技術正受到注目。由於半導體晶片不斷地朝薄 型化發展,故半導體晶片本身變得可輕易地變形(彎曲)。 特開2001-118982號公報及特開平η·345823號公報係揭 露一種將半導體元件變形(彎曲)後實裝之技術。 第1圖係顯示揭露於特開2001_118982號公報之經變 形之半導體晶片之透視圖。半導體晶片〗係捲附於圓筒形 之支持基板2上,以變形成圓筒狀。半導體晶片丨之電極 墊la則排列於圓筒之長方向,且可與其他同樣變形成圓筒 狀之半導體晶片相互連接。 第2圖係顯示揭露於特開平11-345823號公報之經變 形之半導體晶片之側面圖。半導體晶片3係以設置有作為 外部接續電極之錫凸塊3a之側向内彎曲,且錫凸塊3a與 承載基板4之配線部4a相接合。由於承載基板4即使熱變 形,半導體晶片亦可輕易變形(彎曲),故可緩和半導體晶 片3與承載基板4之間(即錫凸塊3a)產生之應力。 但是,第1圖所示之半導體晶片i,由於捲附於圓筒 基板2上,故會增加重量,且為了以晶片組合(將捲於筒 五、發明說明(2) 上之晶片置於上面)來連接相積層之晶片們,故須謀求晶 片之墊之最適化。為此,有必要重新設計晶片,無法使用 過去之半導體晶片。又,必須提出能將半導體晶片i精良 地捲附於圓筒基板2之方法。 第2圖所示之半導體晶片3,由於使半導體晶片彎曲 進灯覆晶實裝時,晶片相當薄且強度弱,故於連接承載基 板時或以樹脂等密封時,於半導體晶片會有發生龜裂之 虞。又,由於半導體晶片變形成圓弧狀,故承載基板與半 導體晶片之連接部之位置精度低。 發明之揭示 本發明之目的係提供一種可解決上述問題之經改良之 有用之半導體裝置及其製造方法。 本發明之更具體目的係提供一種利用極薄晶片,將半 導體晶片變形’使晶片更有效率及空間地配置之半導體裝 置。 本發明之另-目的係提供一種將複數之半導體晶片之 組合自由度增加,且傳送線路可縮短之半導體裝置。 為了達成上述目的,本發明係提供一種半導髏裝置, 包含有:至少-個半導趙晶片;固定元件,係形成於該半 導鱧晶片之表面’用以將該半導體元件固定於經變形為略 圓筒形狀或變㈣狀之狀態者;封裝基板,係覆晶連接該 經變形之半導體晶片者;密封樹脂,係將半導想晶片密封 於該封裝基板上者;及外部接續端子,係設置於該封裝基 板者。 1234827 五、發明說明(3) 依上述發明,由於半導體晶片係藉固定元件固定於經 變形之狀態,故可直接對封裝基板覆晶連接。固定元件亦 具有用以防止半導體晶片破裂之補強元件之功能。又,由 於半導體晶片變形成圓筒形或彎曲形,故相較於實裝平坦 狀態之半導體晶片,可使用較小之封裝基板,可縮小半導 體裝置之水平投影面積。又,藉著適當地組合複數個經變 形之半導體晶片,可有效利用封裝基板上之空間,提高半 導體裝置之實裝密度。進而,使半導體晶片變形後,可改 變外部接續用電極墊至適當位置,可縮短封裝基板上之配 線。藉此’可達成進行高速動作之半導體裝置。 於上述發明中,固定元件宜為形成於略圓筒形狀或彎 曲形狀之半導體晶片之内側面之樹脂層。又,為了可容易 變形’半導體晶片之厚度宜為5〇μίη以下。 又’本發明之半導體裝置宜具有相互覆晶連接之複數 之半導體晶片。複數之半導體晶片則宜包含有:略圓筒狀 之第1半導體晶片;及第2半導體晶片,係形成直徑較第 1半導體晶片大之略圓筒形狀,且包圍第丨半導體晶片之 外周地配置。第1半導體晶片之端部宜由前述第2半導體 晶片之端部突出延伸,且第丨半導體晶片與封裝基板覆晶 連接。又,複數之半導體晶片宜包含有:彎曲形狀之第t 半導體晶片;及第2半導體晶片,係形成較第丨半導體晶 片大之彎曲形狀,且沿著第丨半導體晶片之外周配置。第 2半導體晶片之端部宜由前述第丨半導體晶片之端部延 伸’且第2半導體晶片與封裝基板覆晶連接。 6 五、發明說明(4) 又,本發明之半導體裝置亦可具有尺寸不同之形成複 數個彎曲形狀之半導體晶片,且於較大尺寸之半導體晶片 之彎曲形狀形成之空間中,收容有較該較大尺寸之半導體 晶片尺寸小之半導體晶片。複數之半導體晶片可分別覆晶 連接於封裝基板。或者,複數個半導體晶片可構造成,較 該大尺寸之半導體晶片尺寸小之半導體晶片對大尺寸之半 導體晶片覆晶連接,而最大尺寸之半導體晶片則覆晶連接 於封裝基板。 又,於本發明之半導體裝置中,半導體晶片宜包含·· 複數之相積層之平坦半導體晶片及變形之半導體晶片,該 變形之半導體晶片係覆晶連接平坦之半導體晶片之電路形 成面朝上時之最上層位置之半導體晶片及封裝基板者。 又,依本發明之另一面,係提供一種半導體裝置之製 造方法,該半導體裝置之製造方法係具有變形之半導體晶 片之半導體裝置之製造方法,包含有以下各步驟··支持步 驟,係用以支持平坦狀態之半導體晶片者;塗布步驟,係 用以塗布液狀樹脂於平坦狀態之半導體晶片者;變形步 驟,係以該經塗布液狀樹脂之面為内侧,將半導體晶片變 形成者;固定步驟,係用以使液狀之樹脂硬化,將半導體 晶片固定於圓筒狀或彎曲狀者;及實裝步驟,係將半導體 晶片覆晶實裝於封裝基板上者。於上述半導體裝置之製造 方法中,用以塗布液狀樹脂之塗布步驟宜進行於該半導體 晶片變形之後。 本發明之其他目的、特徵及優點係藉著所附圖面及以 1234827
五、發明說明(5) 下詳細說明,可更進一步明白。 圖面之簡單說明 第1圖係經變形成圓筒形狀之半導體晶片之透視圖。 第2圖係以彎曲狀態搭載於基板之半導體晶片之侧面 圖。 第3圖係本發明第1實施例之半導體裝置之截面圖。 第4圖係使用於習知之記憶元件之半導體晶片之内部 電路之方塊圖。 第5圖係以圓筒形狀之半導體晶片作為記憶元件時之 内部電路之方塊圖。 第6圖係顯示形成第5圖所示之電路時之半導體晶片 之内部構造之圖。 第7圖係用以搭載第6圖所示之半導體晶片之承載基 板之平面圖。 第8圖係用以將半導體晶片形成圓筒狀之變形用夾具 之立體圖。 第9A圖、第9B圖及第9C圖係用以說明第8圖所示 之變形用夾具之動作之圖。 第10A圖、第10B圖及第10C圖係用以將半導體晶片 形成圓筒狀之變形用夾具之圖。 第11A圖〜第11E圖係用以說明使用第l〇A圖〜第10C 圖之變形用夾具將半導體晶片變形成圓筒狀之動作之圖。 第12圖係經組裝複數之圓筒狀之半導體晶片之半導 體裝置之截面圖。 1234827 , 五、發明說明(〇 第13圖係顯示經組裝複數之圓筒狀之半導體晶片之 半導體裝置之另一例之截面圖。 第14圖係顯示經組裝複數之圓筒狀之半導體晶片之 半導體裝置之另一例之截面圖。 第15圖係第14圖所示之半導體晶片之截面圖。
第1 ό圖係顯示經形成雙重圓筒形狀之半導體晶片之 端部之側面圖。 第17圖係本發明第2實施例之半導體裝置之截面圖。 第18圖係用以形成彎曲形狀之半導體晶片之變形用 夾具之截面透視圖。 第19Α圖、第19Β圖及第19C圖係用以說明以第18 圖所示之變形用夾具將半導體晶片形成彎曲狀之步驟之 圖。 第20圖係用以形成彎曲形狀之半導體晶片之另一變 形用夾具之截面圖。 第21A圖及第21B圖係用以說明使用第28圖之變形 用夾具將半導體晶片形成彎曲狀之步驟之圖。 第22圖用以說明密封複數之彎曲狀之半導體晶片時 之密封樹脂之流動之圖。 第23圖係藉著半導體晶片之彎曲而形成之空間中,收 容有小尺寸之半導體晶片之半導體裝置之截面圖。 第24圖係於第23圖所示之半導體裝置設置散熱器之 例之截面圖。 第25圖係藉著半導體晶片之彎曲而形成之空間中,收 9 1234827
五、發明說明(7) 容有小尺寸之半導體晶片之半導體裝置之另一例之截面 圖。 第26圖係顯示第25圖所示第2配線層之平面圖。 第27圖係於第25圖所示之半導體裝置設置散熱器之 例之截面圖。 第28圖係顯示經搭載複數之半導體晶片之另一半導 體裝置之截面圖。 第29圖顯示第28圖所示之半導體晶片内之配線之一 例之平面圖。 第30A圖〜第30D圖係用以說明將複數半導體晶片同 時變形,以形成半導體裝置之步驟之圖。 發明之最佳實施形態 以下,一面參照圖面,一面說明本發明之實施例。 第3圖係本發明第1實施例之半導體裝置之截面圖。 第3圖所示之半導體裝置係具有一彆曲成略圓筒狀之半導 體晶片10。該半導體晶片1〇則以作為外部接續端子之凸 塊10a朝外f曲。該凸塊i〇a係以錫或金等形成。配列於 半導體晶片10兩邊之周圍之凸塊l〇a則是成二列排列於圓 筒形狀之長方向。半導體晶片1〇之背面(圓筒形狀之内面) 則塗布有作為固定元件之樹脂等塗布材1〇,即形成硬化之 樹脂層。因此,半導體晶片可藉樹脂層固定於彎曲成圓筒 形狀之狀態。 半導體晶片10經由凸塊l〇a與封裝基板(承載基板)12 相接續。即,半導體晶片之凸塊10a相對於承載基板12 10 1234827
五、發明說明(〇 覆晶連接。半導體晶片藉著密封樹脂13密封於承載基板 12上。於承載基板12之背面則設有作為半導體裝置之外 部接續端子之錫球14。 如上所述,使半導體晶片10變形成圓筒形狀時,半導 體晶片10之厚度愈薄愈好,以5〇μιη以下為佳。
由於半導體晶片1 〇為圓筒形狀,故相較於半導體晶片 10以平坦狀態實裝於承載基板上,可使用較小尺寸之承載 基板。因此’半導體裝置之水平投影面積可較小。 於此’說明將半導體晶片1 0做成圓筒形狀時之其他優 點。第4圖係使用於習知記憶元件之半導體晶片之内部電 路之方塊圖。於習知之記憶元件用半導體晶片中,資料輸 入電路15及資料輸出電路16係連接於一個電極墊17。 又,於記憶胞元陣列18之兩側則分別設有記入電路19及 讀取電路20。此時,若資料輸出電路16設於讀取電路2〇 之附近,資料輸入電路15與記入電路19之間之距離會變 長,用以連接資料輸入電路15與記入電路19之間之晶片 内之配線21之長度變長。如此晶片内之長的配線將妨礙高 速之讀取動作。 本貫施例之半導體裝置可將上述晶片内之配線以形成 於承載基板上之短配線取代。以下說明其理由。 第5圖係將本實施例之圓筒形狀之半導體晶片1〇作為 記憶元件使用時之内部電路之方塊圖。第6圖係顯示形成 第5圖所示之電路時之半導體晶片1〇之内部構造之圖。此 時’資料輸入電路15設置於記入電路19之附近,資料輸 11 1234827 五、發明說明(9) 出電路16則設置於讀取電路2〇之附近。然後,資料輸入 端子22以排列於資料輸入電路15及記入電路19之附近之 狀態設置。另一方面,資料輸出端子23則以排列於資料輸 出電路16及讀取電路2〇之附近之狀態設置。 資料輸入端子22之列相當於配列於半導體晶片1〇之 一側邊之電極,資料輸出端子23之列則相當於配列於半導 體晶片10之反對側之邊之電極。進而,於資料輸入端子 22之列及資料輸出端子23之列則分別包含有時序(clk) 端子24。 半導體晶片10 —被變形成圓筒狀,資料輸入端子22 之列及資料輸出端子23之列就以近接狀態成二列平行延 伸。藉著將此半導體晶片1〇之電極接續於第7圖所示之承 載基板12之電極墊25,資料輸入端子22與相對應之資料 輸出端子23就可藉著經形成於承載基板12上之配線相連 接。 因此’可將形成於習知半導體晶片内之配線2〗(參照 第4圖)取代成承載基板12上之短配線,可實現高速之動 作。 以下,說明將半導體晶片形成圓筒狀之方法。 首先,說明將半導體晶片形成圓筒狀之第丨方法。第 8圖係用以以第1方法將半導體晶片形成圓筒狀之夾具之 透視圖。第8圖所示之變形用夾具3〇係由中央之支持部 31及可旋轉地設置於支持部31兩側之圓弧狀之可動部u 所構成。可動部32係一端支持於該支持部31成可旋轉狀。 12 1234827
支持部31具有真空吸引用之孔3 la,且可真空吸引平 坦狀之半導體晶片1G之中央部份。又,可動部32内則裝 有電熱線32a,以可於晶片10藉變形用夾具30變形時進 行加熱。
首先,如第9A圖所示,將平坦狀態之半.導體晶片ι〇 之經設置凸塊l〇a之面以支持部31真空吸引。此時,半導 體晶片10之背面塗布有塗布材11。而後,如第9B圖所示, 藉著旋轉可動部32,使半導體晶片1〇沿著可動部&之圓 弧狀緩緩變形。最後,如第9C圖所示,旋轉可動部32至 半導體晶片成略圓筒形狀。 如第9C圖所示,半導體晶圓呈略圓筒狀後,藉著可 動部32内之電熱線使半導鱧晶片1〇背面塗布之塗布材“ …、硬化。塗布材11完成硬化後,使可動部32回到原來狀 態,解除真空吸引,由變形用夾具3〇取下成為略圓筒狀之 半導體晶片10。此時,係以經硬化之塗布材u維持半導 體晶圓10之圓筒形狀。 又’於半導體晶圓經變形成圓筒狀後,再將塗布材塗 布於半導體晶片1 〇之背面(圓筒之内面),使硬化亦可。又, 亦可於半導體晶片10成為圓筒形狀之前之彆曲狀態,停止 可動部32之旋轉,藉著使塗布材u硬化,形成彎曲狀之 半導體晶片10。 使用於形狀固定用之塗布材i丨並無特別限制,可使用 速乾型之液狀之環氧樹脂等。又,由於半導體晶片10係以 世封樹脂密封,故藉著使用具有近似於密封樹脂13特性之 1234827 五、發明說明(ll) 特性之樹脂作為塗布材’可防止實裝半導體裝置時,因焊 接之應力而發生封裝内之剝離。 又,塗布材11之厚度愈薄,因塗布材之收縮而改變晶 片形狀之影響愈小。為此,塗布材11之厚度宜較晶片之厚 度薄,且愈薄愈好。又,考慮到對半導體晶片1〇之影響, 使塗布材11熱硬化時之溫度以200°c以下為佳。 又,依照塗布材11之特性,於晶圓狀態塗布塗布材 11,於使用上述變形用夾具30使半導體晶片變形後,再加 熱固定之方法亦可。 於本實施形態中,由於並不是將半導體晶片捲於圓筒 狀之基板,來使其變形,即不使用圓筒狀之構件,故可謀 求半導體晶片之輕量化。又,由於並非改變成將半導體晶 片之電極整等捲於筒上構件,而成可堆積狀,故即使是習 知設計之半導體晶片亦可使用。藉著以塗布材固定半導體 晶片之形狀,不僅可任意固定晶片形狀,且可增加半導體 晶片之強度,防止樹脂密封時或覆晶連接時之晶片龜裂。 以下’說明用以使半導體晶片形成圓筒形狀之第2方 法。第10A圖、第10B圖及第10C圖係用以藉第2方法將 半導禮晶片形成圓筒形狀之變形用夾具之圖。第11A圖至 第11E圖係藉第2方法使半導體晶片變形成圓筒形狀之動 作說明圖。 首先,如第11A圖所示,使第10A圖所示之支持夾具 35接觸半導體晶片背面(設置凸塊i〇a之面之反對面),經 由設置於支持夾具35上之孔35a真空吸引半導體晶片10。 14 1234827 五、發明說明(12)
然後’如第11B圖所示,將以支持夾具35支持之半 導體晶片10載置於彎曲夾具36上,以支持夾具35押壓。 聲曲夾具36為截面彎曲成略半圓狀之夾具,具有彈性。當 押壓支持夾具35使半導體晶片10變形時,如第11C圖所 示,半導體晶片10變形成沿著彎曲夾具36内面之形狀。 藉著於彎曲夾具36設置之真空吸引部,可將半導體晶片 10維持於沿著彎曲夾具之内面之狀態。又,於彎曲夾具36 宜預先安裝加熱用電熱線。 之後,如第11D圖所示,將支持夾具35由半導體晶 片10取下,以押壓夾具37(37A、37B)由左右押壓彎曲夾 具36。藉此,如第ΠΕ圖所示,押壓夾具36之截面由半 圓形狀進一步變形成近似於圓之形狀。因此,配置於彎曲 夾具36内側之半導體晶片1〇變形成略圓筒形狀。 進而,於第11D圖所示之狀態或第11E圖所示之狀態 中’可如上述第1方法般,藉著將塗布材11塗布於半導體 晶片背面,使其硬化,以固定半導體晶片之圓筒形狀。 以下,說明搭載經變形成上述圓筒形狀之半導體晶片 之半導體裝置。 第12圖係經組裝複數個圓筒形之半導體晶片之半導 體裝置之截面圖。於第12圖中,3個半導體晶片1〇覆晶 連接於封裝基板(承載基板)38,並以密封樹脂39密封。於 承載基板3 8之背面則設有作為外部接續端子之錫球4〇。 如此,藉著使用圓筒形之半導體晶片1〇,於組裝相同數目 之半導體晶片時,半導體裝置之水平投影面積相較於使用 15 1234827 五、發明說明(l3) 平坦之半導體晶片時可較小。又,可將複數之半導體晶片 全部採用覆晶連接。 第13圖係顯示經組裝複數個圓筒形之半導體晶片之 半導體裝置之另一例之截面圖。於第13圖所示之例中,於 承載基板41兩側分別覆晶連接3個,合計6個半導體晶片 10 ’且分別以岔封樹脂42密封。作為外部接續端子之錫球 43則配置於單側之密封樹脂42之外側,具有較密封樹脂 之厚度大之尺寸。第13圖中所示之半導體晶片1〇呈將圓 筒形再輕微壓扁之橢圓形狀。藉此,可降低密封樹脂42 之厚度。 第14圖係顯示經組裝複數個圓筒形之半導體晶片之 半導體裝置之又一例之截面圖。於第14圖之例中,係將半 導體晶片形成雙重圓筒形狀。第15圖為第14圖之半導體 晶片之截面圖。即,如第15圖所示,於形成圓筒形之半導 體晶片10A (内周晶片)之外側進而設有圓筒形之半導體 晶圓10B(外周晶片),藉此,一體形成複數之半導體晶圓。 半導體晶片10A及10B中,僅一個半導體晶片覆晶連接承 載基板45。半導體晶片10A及1〇B以密封樹脂扑密封於 承載基板45上。於承載基板45之背面則設有作為外部接 續端子之錫球47。 第16圖係顯示經形成雙重圓筒形狀之半導體晶片之 端部之側面圖。外侧之半導體晶片之凸塊形成之面(電路形 成面)係朝向内側之半導體晶片1〇B,成為圓筒形狀之内周 面。因此,無法於外側之半導體晶片1〇B設外部接績端子。 1234827 五、發明說明(Μ) 另一方面,内側之半導體晶片10A之凸塊形成之面(電路 形成面)’成為圓筒形狀之外周面,朝向外側。因此,使内 側之半導體晶片10A之端部由外側之半導體晶片10B之端 部突出,於突出部份設置作為外部接續端子之凸塊1〇Aa。 外侧之半導體凸塊10B則經由内側之半導體晶片i 0B内之 配線及凸塊l〇Aa與承載基板47連接。
如上所述,藉著將半導體晶片形成雙重之圓筒形狀, 可更有效率地空間配置複數個半導體晶片,提高半導體晶 片之密度。 以下,說明本發明第2實施例之半導體裝置。第17 圖係本發明第2實施例之半導體裝置之截面圖。第17圖所 示之半導體裝置具有一經f曲之半導體晶片50。半導體晶 片50係彎曲成經設置作為外部接續端子之凸塊5〇a之面 (電路形成面)成為内側之形狀。凸塊50a係以錫或金等形 成。於半導體晶片50之電路形成面則塗布有樹脂等塗布材 即形成硬化之樹脂層。半導體晶片50則藉樹脂層固定 於彎曲狀態。 半導體晶片50經由凸塊50a與封裝基板(承載基板)52 相接續。即,半導體晶片之凸塊50a相對於承載基板52 覆晶連接。半導體晶片50藉著密封樹脂53密封於承載基 板52上。於承載基板52之背面則設有作為半導體裝置之 外部接續端子之錫球54。 如上所述,使半導體晶片50彎曲時,半導體晶片5〇 之厚度愈薄愈好,以50μιη以下為佳。 17 1234827
五、發明說明(ι〇 由於半導體晶片50經彎曲,故相較於半導體晶片 以平坦狀態實裝於承載基板上,可使用較小尺寸之承載基 板。因此,半導體裝置之水平投影面積可較小。 以下,說明使半導體晶片彎曲之方法。 首先,使用上述第1實施例形成圓筒形狀之半導體晶 片10之方法,可形成彎曲形狀之半導體晶片5〇。例如, 使用第8圖所示之變形用夾具30,可形成變曲形狀之半導 體晶片50。此時,平坦之半導體晶片5〇,係與第8圖所示 之半導體晶片10表襄相反地固定於支持部31。即,以凸 塊50a向下之狀態固定於支持部31。然後,於第9b圖狀 態’使可動部停止旋轉,藉著使塗布材Η硬化,而得到經 固定於弩曲形狀之半導體晶片50。 又’使用第10Α圖及第10Β圖所示之變形用夾具35、 36亦可形成半導體晶片50。此時,平坦狀態之半導體晶片 5〇亦表裏相反,即,以凸塊50a作為下側地安裝於支持夾 具35。然後,藉著於第11C圖所示狀態塗布塗布材u, 並使其硬化,而得到經固定於彆曲形狀之半導體晶片5〇。 第18圖係用以形成彎曲形狀之半導體晶片之變形用 失具之截面透視圖。第18圖所示之變形用夾具55係於底 部之中央部分設有凹部55a,即形成有一空間之塊狀夾 具。於底部空間之中央開有真空吸引用之孔55b。又,於 底部之空間則形成用以注入塗布材之注入通路55c。又, 於變形用夾具之底部附近則埋設有加熱用之電熱線55d。 首先’如第19A圖所示,將變形用夾具55之底部配
-18 - 五、發明說明(1(5 ) 置於平坦狀態之半導體晶片50背面。此時,凹部“a之空 間位置於半導體晶片50之中央部分。半導體晶片5〇之電 路形成面預先塗布有塗布材…之後,經由真空吸引用孔 55b真空吸引半導體晶片5〇,如第⑽圖所示,半導體晶 片50成為考曲狀態。於此,如第19C圖所示,由注入通 路注入塗布材於半導體晶片50與變形用夹具之凹部之底 面之間’再以電熱線加熱硬化。藉此,半導體晶片5〇藉著 電路形成面側之塗布材56及背賴之塗布材被固定於變 曲形狀。 第20圖係用以形成彎曲形狀之半導體晶片之另一變 形用夾具之截面圖。第20圖所示之變形用夾具6〇由一用 以支持半導體晶片50中央部分之中央支持部6〇A及用以 分別支持半導體晶片50之兩端部之端部支持部6〇B、6〇c 構成。中央支持部60A及端部支持部6〇B、6〇c係經由真 空吸引用孔60a真空吸引平坦狀態之半導體晶片5〇。第2〇 圖係顯示平坦狀態之半導體晶片5〇被真空吸引於變形用 夾具60之狀態。 由第20圖所示狀態使中央支持部6〇A相對於端部支 持部60B、60C移動至第21A圖所示之半導體晶片5〇之中 央部彎曲變形之狀態。藉此,半導體晶片5〇係成為中央部 分及端部仍維持平面,但中央部分及端部之間變形之彎曲 狀態。 然後’如第21B圖所示,於半導體晶片5〇之電路形 成面及背面塗布塗布材56並使其硬化。藉著,半導體晶片 19 1234827 五、發明說明(l7 ) 50被固定於彎曲形狀。 將本實施例之半導體晶片複數個並排搭載於承載基板 上時,則如第22圖所示,藉著半導體晶片彎曲而形成之空 間之開口方向,宜排列於密封樹脂之流動方向(圖中箭頭方 向)。即,為了使密封樹脂易流入形成於半導體晶片5〇與 承載基板52之間之空間,以容易充填空間,可調整用以注 入密封樹脂之閘65之位置。此構造亦可應用於上述第J 實施例之圓筒形半導體晶片1〇。 以下,說明組合複數個f曲之半導體晶片於一個封裝 艘之半導體裝置。第23圖係於藉著半導體晶片之彎曲而形 成之空間中,收容有較小尺寸之半導體晶片之半導體裝置 之截面圖。於第23圖之例中,較大尺寸之半導體晶片5〇a 形成弩曲狀,其内側則配置一較小之經形成彎曲形狀之半 導體晶片50B,該半導體晶片5〇B内側則進一步配置平坦 之半導體晶片50C。半導體晶片50A、5〇B、5〇c則分別對 承載基板52覆晶連接,並以密封樹脂53密封。 第23圖所示之構造,雖然同樣是積層半導體晶片,但 部可將全部之半導體晶片覆晶連接於一片承載基板Μ 上。進而,由於半導體晶片之實裝密度上昇而擔心有發熱 問題時,可如第24圖所示,於密封樹脂53上面設置由金 屬板等構成之散熱器66。 進而,欲積層第23圖所示之構造時,亦可採用由較小 之半導體晶片開始堆疊,同時使全部之半導體晶片變形(彎 曲),-起覆晶連接之方法。此方法雖然可減少製程步驟, 1234827 五、發明說明(is ) 但考量到承載基板與半導體晶片之接續密度,或因積層半 導體晶片,晶片過厚而難以使其變形等,故仍以各別將晶 片變形進行覆晶連接為佳。 第25圖係於藉著半導體晶片之彎曲而形成之空間 中,收容有較小尺寸之半導體晶片之半導體裝置之另一例 之截面圖。於第25圖所示之半導體裝置中,半導體晶片 50B呈上下相反配置,且對半導體晶片5〇A覆晶接合。然 後,半導體晶片50C配置於半導體晶片50A與半導體晶片 50B之間所形成之空間。於第25圖所示之例中,半導體晶 片50C對半導體晶片5〇B覆晶連接。 於第25圖所示之構造中,由於半導體晶片50B之背 面係面對承載基板52,故如第26圖所示,於承載基板52 形成銅等之第2配線層67,可促進半導體晶片50B之散 熱。又’如第27圖所示,於密封樹脂53上面設置由金屬 板等構成之散熱器66,可更進一步促進散熱。進而,為了 促進散熱,亦可採用放入散熱球或使用散熱性佳之密封樹 脂等,以降低熱阻等方法。 第25圖之構造之半導體裝置,由於半導體晶片間經覆 晶連接,且晶片間之連接配線長度較短,故可實現高速動 作0 第28圖係顯示經搭載複數之半導體晶片之又一半導 體裝置之截面圖。於承載基板52上以平坦狀態連接有複數 個半導體晶片,最上層之晶片與承載基板之連接係藉著形 狀經變化之晶片進行。於第2 8圖所示之例中,半導體晶片 1234827
五、發明說明(19) 70A與70B背朝背積層,半導體晶片7〇A覆晶連接於承載 基板52。因此,半導體晶片70B成為電路形成面朝上之狀 態。 於半導體晶片70B之上進而覆晶連接有半導體晶片 70C。於此,於習知之MCP型半導體裝置中,一般是以打 線方式連接半導體晶片70B與承載基板52,但於第28圖 之例中係取代打線,而使用經變形之半導體晶片7〇d、7〇e。 藉此,即使積層於封裝體内之晶片之厚度不同,藉著 使用以接續之半導體晶片70D、70E之形狀改變以取代打 線’積層之半導體晶片之厚度變成無限制。又,即使是電 極墊數目較多之半導體晶片或相積層之晶片數目多時,亦 不須各別連接電極墊,可使用經變形之晶片,將最上面之 半導體晶片與承載基板之接續以覆晶一起進行。為此,半 導體晶片與承載基板可於短時間内連接。 用以連接最上面之半導體晶片與承載基板或下面之半 導體晶片之半導體晶片70D、70E之種類,並無特別限制, 具有半導體電路亦可,僅形成配線圖案亦可。 第29圖係顯示半導體晶片7〇d内之配線之一例之平 面圖。於半導體晶片7〇D中,用以連接半導體晶片7〇B之 電極塾之電極墊71係配置於其一邊之附近,而用以連接承 載基板52之電極墊之電極墊72則配置於另一邊之附近。 圖案配線73用以連接電極墊71與電極墊72,將半導 體晶片70B與承載基板52相連接。圖案配線74用以連接 半導體70D内之電路與承載基板52。圖案配線75用以連 22 1234827 五、發明說明(20) 接半導體70D内之電路與半導體晶片7〇B。圖案配線% 用以同時連接半導體晶片70B、半導體晶片7〇D及承載基 板52 〇 如此,藉著使用變形之半導體晶片取代打線,可將多 數之電極墊同時連接,且可輕易形成各種配線路徑。 第30A圖至第30D圖係用以說明將複數之半導體晶片 一起變形,以形成半導體裝置之步驟之圖。首先,如第3〇A 圖所示,將複數之半導體晶片8〇A、8〇B、8〇c之間覆晶連 接,再如第30B圖所示,於半導體晶片間填充底膠81,以 固定。然後,如第30C圖所示,以上述任一種方法使經固 定成一體之半導體晶片80A、80B、80C變形(彎曲),再於 半導體晶片80A' 80B、80C之間填充作為固定元件之樹脂 82,並使其硬化。然後,如第3〇D圖所示,將經變形之半 導體晶片80A、80B、80C覆晶連接於承載基板52,再以 密封樹脂53密封。 藉著上述之變形方法,可將複數之半導體晶片一起變 形。又,即使是單獨時不易變形之尺寸小之半導體晶片(此 時為半導體晶片80A)亦可輕易變形。 於第30A圖至第30D圖所示之例中,雖然是使用3個 半導體晶片,但將半導體晶片80B、80C視為一個大的半 導體晶片亦可。 本發明並不限定於上述具體揭露之實施例,於本發明 之範圍内具有種種變形例及改良例。 元件標號說明 23 1234827 五、發明說明(21) 1.. .半導體晶片 la...電極墊 2…支持基板 3.. .半導體晶片 3a···凸塊 4.. .承載基板 4a·.·配線部 10…半導體晶片 10 a…凸塊 10A…半導體晶片 10Aa…凸塊 10B…半導體晶片 11.. .塗布材 12.. .封裝基板 13…密封樹脂 14…錫球 15…資料輸入電路 16.. .資料輸出電路 17.. .電極墊 18.··記憶胞元陣列 19.. .記入電路 20.. .讀取電路 21·.·配線 22.. .資料輸入端子 23.. .資料輸出端子 24.. .時序端子 25.. .電極墊 2 6…配線 30…變形用夾具 31.. .支持部 31 a...孑L 32.. .可動部 32a...電熱線 35…支持夾具 35a…孔 36…彎曲夾具 37…押壓夾具 37A··.押壓夾具 37B…押壓夾具 38…封裝基板 39…密封樹脂 40.. .錫球 41…承載基板 42…密封樹脂 43.. .錫球 45.. .承載基板 47…錫球 50.. .半導體晶片 24 1234827
五、發明說明(22) 50A…半導體晶片 70E··.半導體晶片 50B…半導體晶片 71...電極墊 50C··.半導體晶片 72...電極墊 50a···凸塊 73…圖案配線 52...承載基板 74…圖案配線 53...密封樹脂 75…圖案配線 5 4...錫球 76...圖案配線 55...變形用夾具 80A...半導體晶片 55a."凹部 80B.··半導體晶片 55b···孔 80C···半導體晶片 55c...注入通路 81…底膠 55d...電熱線 82…樹脂 56...塗布材 60...變形用夾具 60a··.孑 L 60A…中央支持部 60B...端部支持部 65···閘 66...散熱器 67…第2配線層 70A··.半導體晶片 70B...半導體晶片 70C.··半導體晶片 70D…半導體晶片 25
Claims (1)
- 申請專利範圍 双爾彭h卜 h一種半導體裝置,包含有: 至少一個半導體晶片; ^固定元彳,係形成於該半導體晶片之表δ,用以將 5亥半導體晶片固定於經變形為略圓筒形狀或彎曲形狀之 狀態者; 封裝基板’係覆晶連接該經變形本曰 密封樹脂,係將前述半導體晶片密封:=板 上者,及 外。卩接績端子,係設置於該封裝其 2. 如申請專利範圍第W之半導體裳置,其中前述固定元 件為形成於略圓筒形狀或彎曲形狀之半導體晶片之 側面之樹脂層。 3. 如申請專利範圍第1之半導體裝置,其中前述半導 晶片之厚度為50μιη以下。 4. ^申請專利範圍第"員之半導體裝置,其係具有相互 晶連接之複數之前述半導體晶片。 5·如申請專利範圍第4項 ^ 半導體晶片包含有:+導體裝置’其中前述複數之 略圓筒狀之第1半導體晶片;及 之二!半導體晶片’係形成直徑較第1半導體晶片 “:固同形狀,且包圍第1半導體晶片之外周地配置 專利範圍第5項之半導《置,其中前述第? 紅日曰片之端部由前述第2半導 伸,日二、+、〜 令月且日日片之端部突出 ^ 1半導體晶片與前述《基板覆晶連接 内 體 覆 大 半 延 26 1234827 · 夂、申請專利範圍 7·如申請專利範圍第4項之半暮 泠體凌置,其中前述複數之 +導體晶片包含有·· 彎曲形狀之第1半導體晶片;及 Λ第2半導體晶片,係形成較第1半導體晶片大之彎 曲形狀’且沿著第1半導體晶片之外周配置。 8. 如申請專利範圍第7項之半導體裝置,其中前述第2半 Ρ晶片之端部由前述第1半導體晶片之端部延伸,且 前述第2半導體晶片與前述封裝基板覆晶連接。 9. 如申請專利範圍第1項之半導體裝置,其係具有尺寸不 同之形成複數個f㈣狀之前述何體晶片,且於較大 ^寸之半導體晶片之.f曲形狀所形成之”中,收容有 車乂趙大尺寸之半導體晶片尺寸小之半導體晶片。 10. 如申請專利範圍第9項之半導體裝置,其中前述複數 之半導體晶片分別覆晶連接於前述封裝基板。 η·如申請專利範圍第9項之半導體袭置,其中前述複數 個半導體晶片中,較該較大尺寸之半導體晶片尺寸小之 半導體晶片對大尺寸之半導體晶片覆晶連接,而最大尺 寸之半導體晶片則覆晶連接於前述封裝基板。 12·如申請專利範圍第丨項之半導體裝置,其中前述半導 體晶片包含有: 複數之相積層之平坦半導體晶片;及 變形之半導體晶片,係覆晶連接平坦之半導體晶片 之電路形成面朝上時之最上層位置之半導體晶片及前述 封裝基板者。 27 1234827 六、申請專利範圍 3·種半導體裝置之製造方法,係具有變形之半導體晶 片之半導體裝置之製造方法,包含有以下各步驟·· 支持步驟’係用以支持平坦狀態之半導體晶片者; 乂布步驟,係用以塗布液狀樹脂於平坦狀態之半導 體晶片者; k形步驟,係以該經塗布液狀樹脂之面為内側,使 該半導體晶片變形者; 固定步驟,係用以使前述液狀之樹脂硬化,將該半 導體日曰片固疋於圓筒形狀或彎曲形狀者;及 板上:裝步驟’係將前述半導體晶片覆晶實裝於封裝基 14·如^請專利範圍第13項之半導體裝置之製造方法,其 中前述用以塗布液狀樹脂之塗布步 / '、 體晶片變形之後。 i驟係進行於該半導 28
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2002/008193 WO2004015758A1 (ja) | 2002-08-09 | 2002-08-09 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TWI234827B true TWI234827B (en) | 2005-06-21 |
Family
ID=31513601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091118453A TWI234827B (en) | 2002-08-09 | 2002-08-15 | Semiconductor device and manufacturing method thereof |
Country Status (8)
Country | Link |
---|---|
US (1) | US7138723B2 (zh) |
EP (1) | EP1528593B1 (zh) |
JP (1) | JP4299783B2 (zh) |
KR (1) | KR100630588B1 (zh) |
CN (1) | CN100401486C (zh) |
DE (1) | DE60233077D1 (zh) |
TW (1) | TWI234827B (zh) |
WO (1) | WO2004015758A1 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007058096A1 (ja) * | 2005-11-18 | 2007-05-24 | Nec Corporation | 実装基板および電子機器 |
KR100780691B1 (ko) * | 2006-03-29 | 2007-11-30 | 주식회사 하이닉스반도체 | 폴딩 칩 플래나 스택 패키지 |
US8530265B2 (en) | 2010-10-27 | 2013-09-10 | National Tsing Hua University | Method of fabricating flexible artificial retina devices |
US9114004B2 (en) | 2010-10-27 | 2015-08-25 | Iridium Medical Technology Co, Ltd. | Flexible artificial retina devices |
US8954156B2 (en) | 2010-10-27 | 2015-02-10 | National Tsing Hua University | Methods and apparatuses for configuring artificial retina devices |
KR101912928B1 (ko) * | 2011-05-06 | 2018-10-29 | 이리듐 메디칼 테크놀로지 컴퍼니 리미티드 | 비평면 집적 회로 디바이스 |
US8613135B2 (en) | 2011-05-06 | 2013-12-24 | National Tsing Hua University | Method for non-planar chip assembly |
US9155881B2 (en) | 2011-05-06 | 2015-10-13 | Iridium Medical Technology Co, Ltd. | Non-planar chip assembly |
TWI507182B (zh) * | 2011-10-26 | 2015-11-11 | Iridium Medical Technology Co Ltd | 用以製造可撓性人工視網膜裝置的方法 |
TWI473220B (zh) * | 2012-01-10 | 2015-02-11 | Xintec Inc | 半導體堆疊結構及其製法 |
CN106030781B (zh) * | 2013-12-19 | 2019-06-14 | 英特尔公司 | 柔软包裹的集成电路管芯 |
US10446728B2 (en) * | 2014-10-31 | 2019-10-15 | eLux, Inc. | Pick-and remove system and method for emissive display repair |
CN107112317B (zh) * | 2014-12-24 | 2019-07-05 | 日本精工株式会社 | 功率半导体模块以及使用其的电动助力转向装置 |
KR20170060372A (ko) * | 2015-11-24 | 2017-06-01 | 에스케이하이닉스 주식회사 | 휘어진 칩을 이용한 플렉서블 패키지 |
US12020972B2 (en) * | 2020-04-29 | 2024-06-25 | Semiconductor Components Industries, Llc | Curved semiconductor die systems and related methods |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01244625A (ja) * | 1988-03-26 | 1989-09-29 | Mitsubishi Electric Corp | 半導体装置 |
JP3227589B2 (ja) * | 1992-12-24 | 2001-11-12 | 株式会社日立製作所 | 半導体装置 |
US6255599B1 (en) * | 1997-08-18 | 2001-07-03 | Ibm | Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination |
US6448665B1 (en) * | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
JPH11186326A (ja) * | 1997-12-24 | 1999-07-09 | Shinko Electric Ind Co Ltd | 半導体装置 |
JPH11345823A (ja) * | 1998-05-29 | 1999-12-14 | Sony Corp | 半導体チップのフリップチップ実装方法及び実装治具 |
JP3168987B2 (ja) * | 1998-07-09 | 2001-05-21 | 日本電気株式会社 | 表面実装型半導体装置の実装構造 |
WO2000021121A1 (fr) * | 1998-10-05 | 2000-04-13 | Seiko Epson Corporation | Dispositif semi-conducteur et son procédé de production |
TW460927B (en) * | 1999-01-18 | 2001-10-21 | Toshiba Corp | Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device |
JP4321926B2 (ja) * | 1999-10-19 | 2009-08-26 | 富士通株式会社 | 半導体装置並びに半導体集積装置及びその製造方法 |
JP3414342B2 (ja) * | 1999-11-25 | 2003-06-09 | 日本電気株式会社 | 集積回路チップの実装構造および実装方法 |
JP3265301B2 (ja) * | 2000-06-05 | 2002-03-11 | 株式会社東芝 | 半導体装置とその製造方法 |
JP4126891B2 (ja) * | 2001-08-03 | 2008-07-30 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2003051568A (ja) * | 2001-08-08 | 2003-02-21 | Nec Corp | 半導体装置 |
US20040104463A1 (en) * | 2002-09-27 | 2004-06-03 | Gorrell Robin E. | Crack resistant interconnect module |
US6949404B1 (en) * | 2002-11-25 | 2005-09-27 | Altera Corporation | Flip chip package with warpage control |
US6888238B1 (en) * | 2003-07-09 | 2005-05-03 | Altera Corporation | Low warpage flip chip package solution-channel heat spreader |
-
2002
- 2002-08-09 KR KR1020047021035A patent/KR100630588B1/ko not_active IP Right Cessation
- 2002-08-09 EP EP02758823A patent/EP1528593B1/en not_active Expired - Fee Related
- 2002-08-09 WO PCT/JP2002/008193 patent/WO2004015758A1/ja active Application Filing
- 2002-08-09 DE DE60233077T patent/DE60233077D1/de not_active Expired - Lifetime
- 2002-08-09 JP JP2004527308A patent/JP4299783B2/ja not_active Expired - Fee Related
- 2002-08-09 CN CNB028292510A patent/CN100401486C/zh not_active Expired - Fee Related
- 2002-08-15 TW TW091118453A patent/TWI234827B/zh not_active IP Right Cessation
-
2004
- 2004-12-08 US US11/006,664 patent/US7138723B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1528593B1 (en) | 2009-07-22 |
US20050082684A1 (en) | 2005-04-21 |
US7138723B2 (en) | 2006-11-21 |
DE60233077D1 (de) | 2009-09-03 |
JPWO2004015758A1 (ja) | 2005-12-02 |
EP1528593A4 (en) | 2008-02-27 |
CN1633704A (zh) | 2005-06-29 |
KR100630588B1 (ko) | 2006-10-04 |
JP4299783B2 (ja) | 2009-07-22 |
WO2004015758A1 (ja) | 2004-02-19 |
CN100401486C (zh) | 2008-07-09 |
EP1528593A1 (en) | 2005-05-04 |
KR20050009759A (ko) | 2005-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10170458B2 (en) | Manufacturing method of package-on-package structure | |
TWI234827B (en) | Semiconductor device and manufacturing method thereof | |
TWI331382B (en) | Stacked package structure and method for manufacturing the same | |
TWI332258B (en) | Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices | |
TWI333270B (en) | Flip chip contact (fcc) power package | |
KR100442880B1 (ko) | 적층형 반도체 모듈 및 그 제조방법 | |
US20040135243A1 (en) | Semiconductor device, its manufacturing method and electronic device | |
US20020096781A1 (en) | Semiconductor device and liquid crystal module using the same | |
TW407365B (en) | Semiconductor device with reduced thickness | |
TWI378545B (en) | Chip stacked package having single-sided pads on chips | |
JP2000323603A (ja) | 半導体回路装置及びその製造方法 | |
TW200421587A (en) | Multi-chip module | |
TW200805587A (en) | Semiconductor package, method of production of same, printed circuit board, and electronic apparatus | |
US20080179726A1 (en) | Multi-chip semiconductor package and method for fabricating the same | |
JPH10335577A (ja) | 半導体装置及びその製造方法 | |
JP2002176135A (ja) | 積層型の半導体装置とその製造方法 | |
JP3628991B2 (ja) | 半導体装置及びその製造方法 | |
JP3332555B2 (ja) | 半導体装置およびその製造方法 | |
CN112614830A (zh) | 一种封装模组及电子设备 | |
JP4174008B2 (ja) | 半導体装置 | |
TWI261326B (en) | IC three-dimensional package | |
KR100666990B1 (ko) | Bga 패키지 및 그 제조방법 | |
TWI226116B (en) | Multi-chip package with outer leads and outer contact pads | |
US7759791B2 (en) | High density IC module | |
JP2002110839A (ja) | 半導体装置、半導体装置の製造方法及び半導体実装装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |