TWI226381B - Deposition of silicon oxide films - Google Patents

Deposition of silicon oxide films Download PDF

Info

Publication number
TWI226381B
TWI226381B TW091103494A TW91103494A TWI226381B TW I226381 B TWI226381 B TW I226381B TW 091103494 A TW091103494 A TW 091103494A TW 91103494 A TW91103494 A TW 91103494A TW I226381 B TWI226381 B TW I226381B
Authority
TW
Taiwan
Prior art keywords
gas mixture
patent application
deposition chamber
scope
item
Prior art date
Application number
TW091103494A
Other languages
English (en)
Inventor
Kevin Mukai
Srinivas Nemani
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of TWI226381B publication Critical patent/TWI226381B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Chemical Vapour Deposition (AREA)

Description

1226381
、發明說明( 經濟部智慧財產局員工消費合作社印製 積率提高。 參照第2b圖’氧化矽濕蝕刻率（WERR)(被稱為熱氧 化硬）被畫成氮流率及TEOS流率為UOOsccm的函數的 二維圖。如第2b圖所示，與傳統上使用氮或氦來作為載
負氣體比較起來’使用氦、氮混合的氣體來作為TEOS 的載負氣體以及提高氦流率與降低氮流率可降低被沉積 的氧化碎層的濕蚀刻率。降低被沉積的氧化矽層的濕蝕 刻率被認為是較佳的氧化物品質如，較高密度的膜層）的 指標。 溝渠隔鏟封y 第3a-3c圖顯示一基材200在一具有一氧化矽層作 為一溝渠隔離材質的積體電路製程的不同階段中的示意 剖面圖。通常，基材200係指將被實施處理的任何工件， 且一基材結構250被用作為統稱基材以及被形成於該基 材200上的其它材質層。依據處理的特定階段，基材2〇〇 將會對應於一矽基材，或已經被形成於該基材上的其它 材質層。 例如’第3a圖顯示一溝渠結構250的一剖面圖。該 溝渠結構包括主動的半導體區域203及溝渠區域2〇4。 該等溝渠區域204具有2-3微米的深度以供淺溝槽元件 之用及5-10微米的深度以供深溝槽元件之用。 第3b圖顯示形成在第3a圖的溝渠結構25〇上的氧 化碎層205。氧化矽層205填充該溝渠結構25〇的溝渠 第11頁 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) —— ——0^.......Γ訂.........0. (請先閲讀背面之注意事項再填寫本頁) 1226381 A7 B7 五、發明說明（） 區域204。該氧化矽層204係依據上述的處理參數而被 >成於該基材結構250上的。該氧化矽層的厚度係隨著 將破填充之溝渠區域2〇4的深度而異的。之後，參照第 3c圖，形成於該等主動半導體區域203上的氧化矽層2〇5 的—部分可藉由一化學機械研磨（CP)而被去除掉。 雖然運用了本發明的教導的數個較佳實施例已被顯 示及詳細的說明，但熟悉此技藝者可以輕易地想出其它 利用本發明的教導之變化實施例。 ——，………鬢： (請先閲讀背面之注意事項再填寫本頁} 、一· 經濟部智慧財產局員工消費合作社印製 第12頁 規 4 A S) N C 標 家 國 國 中 用 適 度 尺 張 紙 本

Claims (1)

  1. 利範圍 A8 B8 C8 D8 第 年7月修正 1.一種形成氧化石夕層於一基材上的方法，該方法至少包 含： 將一基材置於一沉積室中； 提供一第一氣體混合物及一第二氣體混合物至該 沉積室，其中該第一氣體混合物包含四乙氧基矽，氦 及氮，及其中該第二氣體混合物包含臭氧；及 讓該第一氣體混合物與該第二氣體混合物在該沉 積室内起反應用以形成氧化矽層於該基材上。 2 ·如申請專利範圍第1項所述之方法，其中在該第一氣體 混合物中的氦與氮是以1 : 1至1 : 3的氦：氮的流率 比例範圍而被提供至該沉積室的。 3.如申請專利範圍第1項所述之方法，其中該第二氣體混 合物更包含氧。 4 ·如申請專利範圍第1項所述之方法，其中該沉積室被保 持在150°C至850°C範圍内的溫度。 請 先 閱 讀 背 Φ 之 注 意 事 項 填零·ί裝 頁 I 訂 經濟部智慧財產局員工消費合作社印製 5 ·如申請專利範圍第1項所述之方法，其中該沉積室被保 持在1托爾（torr)至600托爾範圍内的壓力。 6.如申請專利範圍第3頊所述之方法，其中在第二氣體混 合物中的臭氧濃度12.5wt.%。 第1頂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A8 B8 C8 D8 1226381
    六、申請專利範圍 7. —種製造一元件的方法，其炱少包含： -------------β 裝 (請先閱讀背面之注意事項寫本頁) 形成氧化矽層於一基材上’其中該氧化矽層是藉由 讓包含四乙氧基矽，氦及氮的第一氣體混合物與包含 臭氧的第二氣體混合物在/沉積室内起反應而形成 的。 8·如申請專利範圍第7項所述之方法，其中在該第一氣體 混合物中的氦與氮是以1 : 1至1 : 3的氦：氮的流率 比例範圍而被提供至該沉積室的。 9·如申請專利範圍第7項所述之方法，其中該第二氣體混 合物更包含氧。 1 0 ·如申請專利範圍第7項所述之方法，其中該沉積室被 保持在1 5 0 °C至8 5 0 °C範圍内的溫度。 1 1 ·如申請專利範圍第7項所述之方法，其中該沉積室被 保持在1托爾（t〇rr)至600托爾範圍内的壓力。 經濟部智慧財產局員工消費合作社印製 1 2 ·如申請專利範圍第9項所述之方法，其中在第二氣體 混合物中的臭氧濃度12.5wt·%。 1 3 ·如申請專利範圍第2項所述之方法，其中該四乙氧基 石夕是以500mgm(毫克/分鐘）至1500mgm的流率被提供 第14頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1226381 驾 D8 六、申請專利範圍 至該沉積室，氦是以lOOOsccm至3000sccm的流率被 提供至該沉積室，氮是以lOOOsccm至3000sccm的流 室積沉該 至供提被率 (請先閱讀背面之注意事項3寫本頁) 裂--------：訂—>-------' 經濟部智慧財產局員工消費合作社印製 頁 5 節 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
TW091103494A 2001-04-20 2002-02-26 Deposition of silicon oxide films TWI226381B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/839,337 US6511924B2 (en) 2001-04-20 2001-04-20 Method of forming a silicon oxide layer on a substrate

Publications (1)

Publication Number Publication Date
TWI226381B true TWI226381B (en) 2005-01-11

Family

ID=25279464

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091103494A TWI226381B (en) 2001-04-20 2002-02-26 Deposition of silicon oxide films

Country Status (7)

Country Link
US (1) US6511924B2 (zh)
EP (1) EP1253630B1 (zh)
JP (1) JP2003031573A (zh)
KR (1) KR20020082139A (zh)
CN (1) CN1228823C (zh)
DE (1) DE60218924T2 (zh)
TW (1) TWI226381B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6730619B2 (en) * 2000-06-15 2004-05-04 Samsung Electronics Co., Ltd. Method of manufacturing insulating layer and semiconductor device including insulating layer
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
JP4796066B2 (ja) * 2004-09-16 2011-10-19 エス．オー．アイ．テック シリコン オン インシュレータ テクノロジーズ 二酸化ケイ素層を製造する方法
CN101680089A (zh) * 2007-06-15 2010-03-24 应用材料股份有限公司 用于图案加载应用的低温sacvd工艺
CN102446897A (zh) * 2011-11-28 2012-05-09 上海华力微电子有限公司 一种金属-绝缘层-金属型电容
CN102446711A (zh) * 2011-11-28 2012-05-09 上海华力微电子有限公司 一种mim电容中绝缘层的制作方法
CN103305808A (zh) * 2013-06-13 2013-09-18 林嘉佑 二氧化硅薄膜的生产设备及其生产方法
JP2015117156A (ja) * 2013-12-18 2015-06-25 東京エレクトロン株式会社 基板処理装置及びオゾンガス濃度の異常検出方法
KR102381344B1 (ko) 2015-09-18 2022-03-31 삼성전자주식회사 캠형 가스 혼합부 및 이것을 포함하는 반도체 소자 제조 장치들
US10858727B2 (en) 2016-08-19 2020-12-08 Applied Materials, Inc. High density, low stress amorphous carbon film, and process and equipment for its deposition

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4892753A (en) 1986-12-19 1990-01-09 Applied Materials, Inc. Process for PECVD of silicon oxide using TEOS decomposition
JPH05506836A (ja) 1989-06-05 1993-10-07 住友精密工業株式会社 オゾン発生装置用誘電体と誘電体への成膜方法
US5316639A (en) 1989-06-05 1994-05-31 Sachiko Okazaki Dielectric material used for an ozone generator and a method of forming a film to the dielectric material
KR0179554B1 (ko) 1995-11-30 1999-04-15 김주용 반도체 소자의 소자분리절연막 형성방법
US5869394A (en) 1996-10-29 1999-02-09 Mosel Vitelic, Inc. Teos-ozone planarization process
US5817566A (en) 1997-03-03 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration
US6551665B1 (en) 1997-04-17 2003-04-22 Micron Technology, Inc. Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
US5726090A (en) 1997-05-01 1998-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Gap-filling of O3 -TEOS for shallow trench isolation
US6121164A (en) * 1997-10-24 2000-09-19 Applied Materials, Inc. Method for forming low compressive stress fluorinated ozone/TEOS oxide film
US6149987A (en) 1998-04-07 2000-11-21 Applied Materials, Inc. Method for depositing low dielectric constant oxide films
US6245691B1 (en) * 1998-05-29 2001-06-12 Taiwan Semiconductor Manufacturing Company Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
TW429576B (en) * 1998-10-14 2001-04-11 United Microelectronics Corp Manufacturing method for metal interconnect
US6197705B1 (en) 1999-03-18 2001-03-06 Chartered Semiconductor Manufacturing Ltd. Method of silicon oxide and silicon glass films deposition
US6090675A (en) 1999-04-02 2000-07-18 Taiwan Semiconductor Manufacturing Company Formation of dielectric layer employing high ozone:tetraethyl-ortho-silicate ratios during chemical vapor deposition
US6180490B1 (en) 1999-05-25 2001-01-30 Chartered Semiconductor Manufacturing Ltd. Method of filling shallow trenches
KR100340207B1 (ko) * 2000-06-15 2002-06-12 윤종용 절연막 및 그의 제조 방법

Also Published As

Publication number Publication date
EP1253630B1 (en) 2007-03-21
JP2003031573A (ja) 2003-01-31
KR20020082139A (ko) 2002-10-30
DE60218924T2 (de) 2007-12-06
CN1228823C (zh) 2005-11-23
US6511924B2 (en) 2003-01-28
US20020155730A1 (en) 2002-10-24
DE60218924D1 (de) 2007-05-03
EP1253630A1 (en) 2002-10-30
CN1383194A (zh) 2002-12-04

Similar Documents

Publication Publication Date Title
TW559862B (en) Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask
US6197658B1 (en) Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity
TWI226381B (en) Deposition of silicon oxide films
US5741740A (en) Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer
US6100163A (en) Gap filling of shallow trench isolation by ozone-tetraethoxysilane
TWI248160B (en) Manufacturing method of shallow trench isolation
US7528078B2 (en) Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
JPWO2002082554A1 (ja) 半導体装置及びその製造方法
TW306023B (zh)
TW416136B (en) DRAM capacitor strap
TW400615B (en) The structure process of Shallow Trench Isolation(STI)
JP2007194239A (ja) 半導体装置の製造方法
TWI242032B (en) CMP slurry for metal and method for manufacturing metal line contact plug of semiconductor device using the same
TW506048B (en) Method of forming cob type cylindrical shaped storage nodes
TWI235407B (en) Wafer and the manufacturing and reclaiming method therefor
TW463222B (en) Semiconductor wafer, manufacturing method of semiconductor wafer and semiconductor apparatus
US7135422B2 (en) Methods of forming a multi-layered structure using an atomic layer deposition process and methods of forming a capacitor of an integrated circuit device
US6992020B2 (en) Method of fabricating semiconductor device
TW317027B (zh)
TW478099B (en) Shallow trench isolation manufacture method
CN111900075A (zh) 一种氮化硅膜及其沉积方法、半导体器件
JP2006156516A (ja) 金属シリケート窒化膜の製造方法および半導体装置の製造方法
JP2006093242A (ja) 半導体装置の製造方法
US6399494B1 (en) Method of making a semiconductor device
JP2006147896A (ja) 薄膜の製造方法および半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees