TWI223391B - Semiconductor device manufacturing method and electronic equipment using same - Google Patents
Semiconductor device manufacturing method and electronic equipment using same Download PDFInfo
- Publication number
- TWI223391B TWI223391B TW092107728A TW92107728A TWI223391B TW I223391 B TWI223391 B TW I223391B TW 092107728 A TW092107728 A TW 092107728A TW 92107728 A TW92107728 A TW 92107728A TW I223391 B TWI223391 B TW I223391B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- support plate
- electrode
- manufacturing
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001117828 | 2001-04-17 | ||
JP2002113368A JP4020367B2 (ja) | 2001-04-17 | 2002-04-16 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200401400A TW200401400A (en) | 2004-01-16 |
TWI223391B true TWI223391B (en) | 2004-11-01 |
Family
ID=26613682
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092107728A TWI223391B (en) | 2001-04-17 | 2003-04-04 | Semiconductor device manufacturing method and electronic equipment using same |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP4020367B2 (ja) |
TW (1) | TWI223391B (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3829736B2 (ja) * | 2002-02-28 | 2006-10-04 | 凸版印刷株式会社 | チップサイズパッケージの製造方法 |
TWI272683B (en) * | 2004-05-24 | 2007-02-01 | Sanyo Electric Co | Semiconductor device and manufacturing method thereof |
JP4773697B2 (ja) | 2004-06-30 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | Soi基板およびその製造方法ならびに半導体装置 |
JP4795677B2 (ja) | 2004-12-02 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法 |
JP5025922B2 (ja) * | 2005-06-30 | 2012-09-12 | オンセミコンダクター・トレーディング・リミテッド | 回路基板、回路基板の製造方法および半導体装置 |
JP4743631B2 (ja) * | 2006-10-23 | 2011-08-10 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP5550076B2 (ja) * | 2007-07-05 | 2014-07-16 | オー・アー・セー・マイクロテック・アクチボラゲット | 低抵抗のウエハ貫通ビア |
KR100887479B1 (ko) * | 2007-10-09 | 2009-03-10 | 주식회사 네패스 | 내균열성 반도체 패키지 및 그 제조 방법 |
US8168458B2 (en) * | 2008-12-08 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices |
JP2011151138A (ja) * | 2010-01-20 | 2011-08-04 | Panasonic Corp | 半導体装置の製造方法 |
JP5609144B2 (ja) * | 2010-02-19 | 2014-10-22 | ソニー株式会社 | 半導体装置および貫通電極のテスト方法 |
US8426946B2 (en) * | 2010-06-28 | 2013-04-23 | Headway Technologies, Inc. | Laminated semiconductor substrate, laminated chip package and method of manufacturing the same |
US8426948B2 (en) | 2010-08-02 | 2013-04-23 | Headway Technologies, Inc. | Laminated semiconductor wafer, laminated chip package and method of manufacturing the same |
US8552534B2 (en) | 2011-11-01 | 2013-10-08 | Headway Technologies, Inc. | Laminated semiconductor substrate, semiconductor substrate, laminated chip package and method of manufacturing the same |
CN103187398B (zh) * | 2011-12-30 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔检测结构及检测方法 |
-
2002
- 2002-04-16 JP JP2002113368A patent/JP4020367B2/ja not_active Expired - Fee Related
-
2003
- 2003-04-04 TW TW092107728A patent/TWI223391B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200401400A (en) | 2004-01-16 |
JP4020367B2 (ja) | 2007-12-12 |
JP2003007909A (ja) | 2003-01-10 |
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