TW565884B - Method for forming salicide - Google Patents

Abstract

A method for forming a self-aligned silicide (salicide) comprises: forming an isolation region, a transistor gate structure, and a lightly doped source/drain region on a semiconductor substrate; forming a gate spacer on the sidewall of the gate structure, which includes a silicon oxide layer and a silicon nitride layer formed thereon; forming a heavily doped source/drain region; and during the salicide process, forming a barrier layer on the metal layer prior to performing an annealing process to form a silicide. The present invention uses the silicon nitride layer of the gate spacer and the barrier layer to separately isolate the silicon atoms and the oxygen atoms from diffusing to the sidewall on the gate spacer, thereby avoiding the occurrence of short circuit while maintaining the properties of the component.

Description

565884 五、發明說明α) 發明領域： 本發明係有關一種形成自行對準金屬石夕化物（S e 1 f -aligned Silicide，SALICIDE)之方法，特別是關於一種 可避免因閘極間隙壁所造成的短路現象的形成自行對準金 屬矽化物之方法。 發明背景： 按，當半導體元件的生產進入到深次微米製程，且積 體電路的積集度愈來愈高，元件的尺寸愈來愈小，使得閘 極與源/沒極區域之面積亦等同縮小，而為了降低元件串 接電阻值、減少金屬接觸窗數目及增加後續連接導線佈局 (Layout)之方便性，進而縮小整個元件擺列面積，自動 對準金屬矽化物技術之使用已逐漸廣泛應用在半導體製程 中 〇 在深次微米之半導體製程中’習知技術在形成自行對 準金屬石夕化物之製程步驟如第一（a)圖至第一（c)圖所示。 首先’如第一（a)圖所示，在一半導體基底1〇中係已依序 形成有淺溝渠隔離區域1 2、電晶體閘極結構丨4、輕摻雜源 /波極區域1 6、閘極間隙壁（spacer) 1 8及重摻雜源/汲 極區域2 0等元件；當電晶體之主動元件均完成後，即可進 行自行對準金屬石夕化物的製作。此時，在半導體基底1 〇上 先沈積一層2 0 0至6 0 0微米鈦金屬層22，如第一圖所示 :’然後’對該欽金屬層22進行第一次快速回火（rta)， 使鈦金屬層2 2與下方之閘極結構1 4與源/汲極區域2 〇上之 矽反應生成鈦金屬矽化物（T i S i X) 2 4。在形成鈦金屬石夕565884 V. Description of the invention α) Field of the invention: The present invention relates to a method for forming a self-aligned metal silicide (SALICIDE), in particular to a method capable of preventing the gate gap The method of forming a short-circuit phenomenon by self-aligning metal silicide. Background of the invention: As the production of semiconductor devices enters the deep sub-micron process, and the integration degree of integrated circuits is getting higher and higher, the size of the components is getting smaller and smaller, so that the area of the gate and source / inverter regions is also Equivalent reduction, and in order to reduce the series resistance value of components, reduce the number of metal contact windows, and increase the convenience of subsequent connection wire layout (Layout), and then reduce the entire component arrangement area, the use of automatic alignment metal silicide technology has gradually been widely used In the semiconductor manufacturing process, in the deep sub-micron semiconductor manufacturing process, the conventional manufacturing process steps of forming self-aligned metal oxide compounds are shown in the first (a) to the first (c) diagrams. First, as shown in the first (a) diagram, a shallow trench isolation region 1 has been sequentially formed in a semiconductor substrate 10 2. The transistor gate structure 4 and the lightly doped source / wave region 1 6 , Gate spacers (spacer) 18 and heavily doped source / drain region 20 and other components; after the transistor's active components are completed, the self-aligned metal can be produced. At this time, a 200 to 600 micron titanium metal layer 22 is first deposited on the semiconductor substrate 10, as shown in the first figure: 'then' the first rapid tempering of the metal layer 22 (rta ), Causing the titanium metal layer 22 to react with the underlying gate structure 14 and silicon on the source / drain region 20 to generate titanium silicide (T i S i X) 2 4. In the formation of titanium metal stone eve

565884 五、發明說明（2) 化物2 4之後，利用濕蝕刻法之化學溶液去除部份未反應成 欽金屬石夕化物之鈦金屬層2 2或反應後殘留之氧化鈦，如第 一（c )圖所示，只留下金屬石夕化物2 4於閘極結構1 4與源/ 汲極區域2 0上；最後對此鈦金屬矽化物2 4進行第一次快速 回火處理，以降低鈦金屬矽化物2 4之電阻值，如此即可得 到完整的自行對準金屬矽化物。 在整個整個自行對準金屬矽化物的製程中，係牽涉到 半導體基底之石夕表面自生氧化矽之清除，金屬薄膜之沈積 技術，兩次快速回火處理之溫度、時間、氣氛控制及選擇 性餘刻溶液之清除效果等，均會影響到整個製程的成功與 否。然而，在上述之習知製程中，閘極結構或源/汲極區 域之石夕原子係會擴散到閘極間隙壁上而形成如石夕化鈦 (T i S i Ο之金屬矽化物，或氧原子因高溫擴散經過鈦金 屬層到閘極間隙壁之側壁上形成導電的氧化鈦，抑或是因 為自行對準金屬石夕化反應（saiicidation)之溫度不當造 成欽金屬與二氧化矽反應產生矽化鈦等之各種其他原因； 由於此些因素，將造成閘極結構到源/汲極區域之間的閘 極間隙壁之側壁上形成導電不純物，且此導電不純物係無 ^ =選擇性化學溶液去除，因而造成閘極結構與源/汲極 品〆間的短路（bridging)現象，進而導致元件失效。 祛的T此’本發明係在針對上述之習知缺失’提出一種較 /自行對準金屬矽化物的形成步驟，以解決在閘極間隙 壁上所造成的短路現象。 發明目的與概述：565884 V. Description of the invention (2) After the compound 24, the chemical solution of the wet etching method is used to remove a part of the titanium metal layer 22 that has not been reacted to form a metal oxide compound or the titanium oxide remaining after the reaction, such as the first (c As shown in the figure, only the metal oxide compound 24 is left on the gate structure 14 and the source / drain region 20; finally, the titanium metal silicide 24 is subjected to the first rapid tempering treatment to reduce The resistance value of the titanium metal silicide 24 can thus obtain a complete self-aligned metal silicide. Throughout the entire process of self-aligning metal silicide, it involves the removal of in-situ silicon oxide on the surface of the semiconductor substrate, the deposition technology of metal films, and the temperature, time, atmosphere control and selectivity of two rapid tempering processes The removal effect of the solution in the remaining moment will affect the success of the entire process. However, in the above-mentioned conventional manufacturing process, the stone structure of the gate structure or the source / drain region will diffuse to the gate gap to form a metal silicide such as titanium oxide (TiSiSi, Or oxygen atoms diffuse through the titanium metal layer and form conductive titanium oxide on the side wall of the gate gap due to high-temperature diffusion, or due to improper alignment of the temperature of the metal saiicidation, which causes the reaction between the metal and silicon dioxide. Various other reasons such as titanium silicide; Due to these factors, conductive impurities will be formed on the side wall of the gate gap between the gate structure and the source / drain region, and the conductive impurities are not ^ = selective chemical solution Removal, thus causing a short circuit (bridging) phenomenon between the gate structure and the source / drain pin, and thus causing the component to fail. The present invention 'proposes a relatively / self-aligning metal for the lack of known knowledge' The step of forming silicide to solve the short circuit phenomenon caused by the gate gap. The purpose and summary of the invention:

化物之方』之目的係在提供一種形成自行對準金屬矽 求的閘極盥75 )糸可避免閘極間隙壁上之導電不純物所造 與源/汲極區域間發生短路之現象。 化物之方法另了目的係在提供一種形成自行對準金屬矽 上，故。。’其係可阻絕導電不純物形成於間隙壁之側壁 可保持元件特性，而不會造成元件失效。 有隔雜，到上述之目的’本發明係在一半導體基底上形成 區域、電晶體閘極結構及一輕摻雜源/汲極區域； 1閑極結構侧壁形成有閘極間隙壁，其係包含下層之氧 Λ γ* Tun J^L yy m 回 火處 .理 使 閘 極 結 構 與 源 / ί及極 L區 域 上 形 成 金 屬 矽 化 物， 最 後去 .除 該 阻 障 層 及 未 反 應 之金 ‘屬 層 並 對 該 金 屬 矽 化物 進 行熱 ί回 火 處 理 〇 Μ ‘下 藉 由 具 體 實 施 例 配 合戶/1 一附 的 圖 式 詳 加 說 明 當更 容 易瞎 ，解 本 發 明 之 因 的 技 術内 容 特 點 及 其 所 達 成 之功 效 〇 圖 號說明 • 10 半 導 體 基 底 12 淺 溝 渠 隔 離 區 域 14 閘 極 結 構 16 輕 摻 雜 源 / 汲 極 區 域 18 閘 極 間 隙 壁 20 重 摻 雜 源 / 汲 極 區 域 22 鈦 金 屬 層 24 鈦 金 屬 矽 化 物 30 半 導 體 基 底 32 淺 溝 渠 隔 離 區 域 θ /上層之氮化矽層，並以閘極結構與閘極間隙壁為 、、’形成重摻雜源/汲極區域；經過熱回火處理之後， 声半導體基底上依序形成一金屬層及一阻障層；進行一熱The purpose of the method is to provide a self-aligned metal silicon gate (75), which can avoid short circuit between the source / drain region caused by conductive impurities on the gate gap wall. The purpose of the chemical method is to provide a method for forming self-aligned metal silicon. . ’It prevents the conductive impurities from being formed on the side walls of the gap and maintains the characteristics of the component without causing component failure. There are impurities. To the above purpose, the present invention forms a region, a transistor gate structure, and a lightly doped source / drain region on a semiconductor substrate. A gate gap is formed on the sidewall of the idler structure. It contains the lower layer of oxygen Λ γ * Tun J ^ L yy m tempering place. The metal structure is formed on the gate structure and the source / ί and L area, and finally go. In addition to the barrier layer and unreacted gold 'Belong to the layer and heat-tempering the metal silicide 0M', the specific examples will be used in conjunction with the user / 1 a attached drawing to explain in detail when it is easier to blind, to explain the technical content of the reasons for the present invention And the effect it achieves. 0 Description of figure number • 10 semiconductor substrate 12 shallow trench isolation region 14 gate structure 16 lightly doped source / drain region 18 gate spacer 20 heavily doped source / drain region 22 titanium metal layer 24 titanium silicide 30 semiconductor Body substrate 32 Shallow trench isolation region θ / upper silicon nitride layer, and the gate structure and gate spacer are used to form a heavily doped source / drain region; after thermal tempering, the acoustic semiconductor substrate A metal layer and a barrier layer are sequentially formed on the substrate;

第6頁 565884 五、發明說明（4) 3 4 2閘極氧化層 36輕摻雜源/汲極區域 3 8 2氧化矽層 40重摻雜源/汲極區域 44 氮化鈦阻障層 3 4 閘極結構 344多晶矽層 38 閘極間隙壁 3 8 4氮化矽層 42 鈦金屬層 46 鈦金屬矽化物 詳細說明： Η技ί習知製作自行對準金屬矽化物之製程中’極易造成 甲1極…構到源/汲極區域之間的閘極間隙壁側壁上有導電 =物，其係會造成短路現象，導致元件失效，而本發 月所提出之方法係可有效克服習知技術之該等缺失。 第二（a)圖至第二（U圖分別為本發明之較佳實施例在 ，作自行對準金屬矽化物的各步驟構造剖視圖。首先，如 =二（a)圖所示，在一半.導體基底3〇中先形成淺溝渠隔離 區域（shallow trench isolation， STI) 32，以用來隔 絕半導體基底3 0中的主動元件及被動元件；再於半導體美 底3 0表面形成一電晶體閘極結構3 4，其係由一閘極氧化層 342及其上方之多晶矽層344所組成；然後以閘極結構 罩幕’對半導體基底30進行一低濃度的第一次離子佈植了 \吏其在半導體基底30内形成輕摻雜源/汲極區域36 ;再於 問f結構3 4之二側壁旁形成有閘極間隙壁3 8，其係由下層 之氧化矽層3 8 2及上層之氮化矽層3 8 4所組成。 θ 其中’形成該閘極間隙壁3 8之方式，係以化學氣相沈 積方式在該半導體基底上先沈積一氧化矽層後（圖中未示 565884 五、發明說明（5) )，再沈積一氮化石夕層於該氧化矽層上；然後利用反應性 離子#刻（Reactive I〇n Etch，RIE)之乾蝕刻技術對該 半導體基底進打一全面性蝕刻，直至去除該閘極結構及源 /汲極區域上的該氮化矽層及氧化矽層為止，僅留下在閘 極結構3 4側壁之部份該氮化石夕層3 8 4及氧化石夕層3 8 2，以作 為該閘極間隙壁3 8。 θ 在形成閘極間隙壁38之後，再以閘極結構34與閘極間 隙壁3 8為罩幕’對該半導體基底3 0進行一較高濃度之第二 離子佈植’以便在該半導體基底3 0内形成重摻雜源/汲極 區域40，隨即進行熱回火處理，以重整該半導體基底3〇表 面包含源/沒極區域40在内之矽原子，使之恢復成原有的 晶格結構；隨後即可進行自行對準金屬矽化物的製程。 接續參考第二（b )圖所示’利用化學氣相沈積方式或 金屬濺鍍（sputter)方式，在半導體基底3〇表面形成一 鈦金屬層4 2，本實施例係以鈦金屬作為較佳材質，除此之 外，亦可以鈷金屬，或是其它可行的金屬材質取代之。接 著’在該鈦金屬層4 2表面形成一氮化鈇阻障層44，如第二 (c )圖所示，若該鈦金屬層4 2係以化學氣相沈積方式所形 成者，氮化鈦阻障層4 4之形成方式係為對該鈦金屬層4 2進 行一氮離子佈值，以使部分之鈦金屬層42轉變成該氮化鈦 阻障層44 ;若鈦金屬層42係以金屬濺鍍方式所形成者，則 在形成鈦金屬層42時，同時於濺鍍真空室中通入含有氮氣 之混合氣體，例如氬/氮（Ar/N 2)混合氣體，使部分之 鈦金屬層4 2轉變成該氮化鈦阻障層4 4。Page 6 565884 V. Description of the invention (4) 3 4 2 Gate oxide layer 36 lightly doped source / drain region 3 8 2 Silicon oxide layer 40 heavily doped source / drain region 44 Titanium nitride barrier layer 3 4 Gate structure 344 Polycrystalline silicon layer 38 Gate spacer 3 8 4 Silicon nitride layer 42 Titanium metal layer 46 Titanium metal silicide Detailed description: Technical know-how in the process of making self-aligned metal silicide is very easy to cause A1 pole ... There is a conductive material on the side wall of the gate gap between the source / drain region, which will cause a short circuit phenomenon and cause the component to fail. The method proposed in this month can effectively overcome the conventional These shortcomings of technology. The second (a) to the second (U diagrams are cross-sectional views of the steps for constructing self-aligned metal silicide in the preferred embodiment of the present invention. First, as shown in the second (a) diagram, in half A shallow trench isolation (STI) 32 is first formed in the conductor substrate 30 to isolate the active and passive components in the semiconductor substrate 30; then a transistor is formed on the surface of the semiconductor substrate 30 The gate structure 34 is composed of a gate oxide layer 342 and a polycrystalline silicon layer 344 above it; then, a low-concentration first ion implantation is performed on the semiconductor substrate 30 with a gate structure mask \ A lightly doped source / drain region 36 is formed in the semiconductor substrate 30; and a gate spacer 38 is formed next to the side wall of the second structure 34, which is composed of a lower silicon oxide layer 3 8 2 and an upper layer. The silicon nitride layer 3 8 4 is formed. Θ The method of forming the gate spacer 3 8 is to deposit a silicon oxide layer on the semiconductor substrate by chemical vapor deposition (not shown in the figure 565884). 5. Description of the invention (5)), and then depositing a nitrided layer on the On the silicon oxide layer; and then use the reactive ion etching (Reactive Ion Etch, RIE) dry etching technology to perform a comprehensive etching on the semiconductor substrate until the gate structure and the source / drain region are removed. As far as the silicon nitride layer and the silicon oxide layer, only a part of the sidewall of the gate structure 34 is left. The nitride layer 3 8 4 and the oxide layer 3 8 2 are used as the gate spacer 3 8. Θ After the gate gap wall 38 is formed, the gate structure 34 and the gate gap wall 38 are used as a mask to 'implement a high-concentration second ion implantation of the semiconductor substrate 30' to the semiconductor substrate 30. A heavily doped source / drain region 40 is formed in the substrate 30, and then thermal tempering is performed to reform the silicon atoms on the surface of the semiconductor substrate 30 including the source / inverted region 40 to restore the original The self-aligned metal silicide process can then be performed. Continue to refer to the second (b) figure 'using chemical vapor deposition or metal sputtering, on the surface of the semiconductor substrate 30 A titanium metal layer 42 is formed. In this embodiment, titanium metal is used as In addition, it can be replaced by cobalt metal or other feasible metal materials. Then, a hafnium nitride barrier layer 44 is formed on the surface of the titanium metal layer 42, as shown in FIG. 2 (c). As shown, if the titanium metal layer 4 2 is formed by a chemical vapor deposition method, the titanium nitride barrier layer 44 is formed by performing a nitrogen ion distribution value on the titanium metal layer 4 2 so that Part of the titanium metal layer 42 is transformed into the titanium nitride barrier layer 44; if the titanium metal layer 42 is formed by a metal sputtering method, when the titanium metal layer 42 is formed, it is simultaneously passed in a sputtering vacuum chamber. A mixed gas containing nitrogen, such as an argon / nitrogen (Ar / N 2) mixed gas, converts a portion of the titanium metal layer 4 2 into the titanium nitride barrier layer 4 4.

565884 五、發明說明（6) 繼續如第二（c )圖所示’利用一溫度大於5 0 0°C之快速 回火（RTP)製程，對該半導體基底進行熱回火處理， 使鈦金屬層4 2與該閘極結構3 4與源/汲極區域4 0相接觸之 部份轉變成鈦金屬矽化物4 6。然後，利用溼餘刻技術去除 未反應成鈦金屬矽化物46之該鈦金屬層4 2及其上之氮化鈦 阻障層4 4，即可得到如第二（d )圖所示之構造；最後，以 一溫度大於7 〇 〇°C之快速回火製程對該鈦金屬矽化物4 6進 行高溫熱回火處理，以降低鈦金屬矽化物4 6之電阻值。 其中，該閘極間隙壁3 8上的氮化矽層3 8 4係可作為阻 絕之用，阻止矽原子從閘極結構3 4上多晶矽層3 4 4和源/ 沒極區域4 0擴散至閘極間隙壁3 8的側壁上，防止閘極間隙 壁3 8上形成導電的石夕化鈦（TiSi)。另一方面，在鈦金 屬層4 2上直接形成之氣化欽阻障層4 4 一具有阻擋作用，阻 止氧原子於第一次高溫熱回火時，擴散至閘極間隙壁3 8側 壁上而形成導電的不純物，例如氧化鈦等。由於這些導電 不純物無法由、屋钱刻等方式去除，所以本發明利用閘極間 隙壁38之氮化矽層384及氮化鈦阻障層44來阻絕導電不純 物之形成。 因此，本發明係可有效阻絕導電不純物形成於閘極間 隙壁之側壁上，故可避免閘極結構與源/汲極區域間發生 短路之現象，並同時保持元件特性，而不會造成任何元件 失效。 •r 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内565884 V. Description of the invention (6) Continue to use the rapid tempering (RTP) process with a temperature greater than 500 ° C as shown in the second (c) diagram to thermally temper the semiconductor substrate to make titanium metal The portion of the layer 42 that is in contact with the gate structure 34 and the source / drain region 40 is converted into a titanium silicide 46. Then, the wet metallization technique is used to remove the titanium metal layer 4 2 and the titanium nitride barrier layer 4 4 which have not reacted into the titanium metal silicide 46 to obtain the structure shown in the second (d) diagram. ; Finally, the titanium metal silicide 46 is subjected to a high-temperature thermal tempering process in a rapid tempering process with a temperature greater than 700 ° C to reduce the resistance value of the titanium metal silicide 46. Among them, the silicon nitride layer 3 8 4 on the gate spacer 38 can be used as a barrier to prevent silicon atoms from diffusing from the polycrystalline silicon layer 3 4 4 and the source / inverted region 40 on the gate structure 34. On the side wall of the gate gap wall 38, a conductive titanium oxide (TiSi) is prevented from being formed on the gate gap wall 38. On the other hand, the gasification barrier layer 4 4 formed directly on the titanium metal layer 4 2 has a blocking effect, preventing oxygen atoms from diffusing to the gate gap wall 38 during the first high-temperature thermal tempering. Impurities are formed on the surface, such as titanium oxide. Since these conductive impurities cannot be removed by means of engraving, etc., the present invention uses the silicon nitride layer 384 and the titanium nitride barrier layer 44 of the gate gap wall 38 to prevent the formation of the conductive impurities. Therefore, the present invention can effectively prevent the conductive impurities from being formed on the side walls of the gate gap wall, thus avoiding a short circuit between the gate structure and the source / drain region, and at the same time maintaining the characteristics of the element without causing any element Failure. • The embodiments described above are only for explaining the technical ideas and features of the present invention, and their purpose is to enable those skilled in the art to understand the present invention.

565884 五、發明說明（7) 容並據以實施，當不能以之限定本發明之專利範圍，即大 凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵 蓋在本發明之專利範圍内。565884 V. Description of the invention (7) Content and implementation based on it, when the scope of the patent of the present invention cannot be limited, that is, any equal change or modification made in accordance with the spirit disclosed by the present invention should still be covered by the patent scope of the present invention Inside.

第10頁 565884 圖式簡單說明 第一（a)圖至第一（c)圖為習知製作自行對準金屬矽化物之 各步驟構造剖視圖。 第二（a)圖至第二（d)圖為本發明製作自行對準金屬矽化物 之各步驟構造剖視圖。Page 10 565884 Brief description of the drawings The first (a) to the first (c) are cross-sectional views of the steps in the conventional process of making self-aligned metal silicide. The second (a) to the second (d) diagrams are cross-sectional structural views of the steps of manufacturing self-aligned metal silicide according to the present invention.

(II 第11頁(II p. 11

Claims (1)

565884 六、申請專利範圍 1 · 一種形成自行對準金屬矽化物之方法，包括下列步驟 提供一半導體基底，其内係形成有隔離區域； 在該半導體基底上形成一電晶體閘極結構，包含一閘 氧化層及其上方之多晶矽層； 以該閘極結構為罩幕，進行一低濃度的離子佈植，在 該半導體基底内形成輕摻雜源/汲極區域； 於該閘極結構側壁形成有閘極間隙壁，包含下層之氧 化石夕層及上層之氮化石夕層；565884 6. Scope of patent application1. A method for forming self-aligned metal silicide, including the following steps: providing a semiconductor substrate with an isolation region formed therein; forming a transistor gate structure on the semiconductor substrate, including: A gate oxide layer and a polycrystalline silicon layer above the gate structure; using the gate structure as a mask, a low-concentration ion implantation is performed to form a lightly doped source / drain region in the semiconductor substrate; formed on the side wall of the gate structure There are gate gap walls, including a lower oxide stone layer and an upper nitride stone layer; 以該閘極結構與閘極間隙壁為罩幕，對該半導體基底 進行一高濃度離子佈植，以形成重摻雜源/汲極區 域； 進行熱回火處理，以重整該半導體基底表面之矽原子 j 於該半導體基底上形成一金屬層； 形成一阻障層於該金屬層表面； 對該半導體基底進行熱回火處理，使該金屬層與該閘 極結構與源/汲極區域相接觸部份轉變成金屬矽化 物；Using the gate structure and the gate gap wall as a mask, a high-concentration ion implantation is performed on the semiconductor substrate to form a heavily doped source / drain region; and a thermal tempering process is performed to reform the surface of the semiconductor substrate. A silicon atom j forms a metal layer on the semiconductor substrate; a barrier layer is formed on the surface of the metal layer; the semiconductor substrate is thermally tempered to make the metal layer and the gate structure and the source / drain region The contact parts are transformed into metal silicide; 去除該阻障層及未反應成金屬矽化物之該金屬層；以 及 對該金屬矽化物進行熱回火處理。 2 ·如申請專利範圍第1項所述之形成自行對準金屬矽化 物之方法，其中形成該閘極間隙壁之方法係包括下列Removing the barrier layer and the metal layer which has not reacted into a metal silicide; and thermally tempering the metal silicide. 2 · The method for forming a self-aligned metal silicide as described in item 1 of the scope of the patent application, wherein the method for forming the gate spacer includes the following 第12頁 565884Page 12 565884 六、申請專利範圍 3 4 6 7 8 步驟： 在該半導體基底上沈積一氧化矽層； 再沈積一氮化矽層於該氧化矽層上；以及 對該半導體基底進行一全面性蝕刻，去除該 及源/汲極區域上的該氮化矽層及氧化矽 下该閘極結構側壁之部份該氮化矽層及氧 以作為該閘極間隙壁。 如申請專利範圍第2項所述之形成自行對準 物之方法，其中該氧化矽層及氮化矽層係利 相沈積方式沈積在該半導體基底上。 如申請專利範圍第2項所述之形成自行對準 物之方法’其中去除該閘極結構及源/汲極 該氣化石夕層及氧化矽層之步驟係利用反應性 之乾#刻技術對該半導體基底進行一全面性 如申请專利範圍第1項所述之形成自行對準 物之方法’其中該金屬層之材質係可為鈦金 屬，或是其它可行的金屬材質。 如申請專利範圍第1項所述之形成自行對準 物之方法，其中形成該金屬層之步驟係利用 方式形成者。 如申請專利範圍第i項所述之形成自行對準 物之方法，其中形成該金屬層之步驟係利用 沈積方式形成者。 如申凊專利範圍第1項所述之形成自行對準 閘極結構 層，以留 化石夕層， 金屬化 用化學氣 金屬矽化 區域上的 離子餘刻 餘刻。 金屬矽化 屬、始金 金屬矽化 金屬濺鍍 金屬矽化 化學氣相 金屬矽化 ❿6. The scope of patent application 3 4 6 7 8 Steps: depositing a silicon oxide layer on the semiconductor substrate; depositing a silicon nitride layer on the silicon oxide layer; and performing a comprehensive etching on the semiconductor substrate to remove the silicon oxide layer And the silicon nitride layer on the source / drain region and a part of the silicon nitride layer and oxygen on the side wall of the gate structure under silicon oxide serve as the gate spacer. The method for forming a self-aligned object as described in item 2 of the scope of patent application, wherein the silicon oxide layer and the silicon nitride layer are deposited on the semiconductor substrate by a phase deposition method. The method of forming a self-alignment object as described in item 2 of the scope of the patent application, wherein the step of removing the gate structure and the source / drain electrode, the gasified stone layer and the silicon oxide layer is performed using a reactive dry etching technique The semiconductor substrate performs a comprehensive method for forming a self-alignment object as described in item 1 of the scope of the patent application, wherein the material of the metal layer can be titanium metal or other feasible metal materials. The method for forming a self-aligned object as described in item 1 of the scope of patent application, wherein the step of forming the metal layer is formed by a method. The method for forming a self-aligned object as described in item i of the patent application scope, wherein the step of forming the metal layer is formed by a deposition method. The self-aligned gate structure layer is formed as described in item 1 of the scope of Shenying's patent to retain the fossil evening layer, and the chemical gas is used for metallization. Metal silicide Metal, silicide Metal sputter metal Sputter metal Silicide chemical vapor Metal silicide ❿ 第13頁 565884Page 13 565884 物之方法，其中該阻障層係由一氮化金屬層所構成者 〇 9 ·如申請專利範圍第8項所述之形成自行對準金屬矽化 ^之方法，其中該氮化金屬層之形成方式係為對該金 屬層進行一氮離子佈值，以使部分之該金屬層轉變成 該氮化金屬層。 1〇如申請專利範圍第8項所述之形成自行對準金屬矽化 物之方法，其中該氮化金屬層之形成方式係在形成該 金屬層時，同時於真空室中通入含有氮氣之混合氣體 ’使部分之該金屬層轉變成該氮化金屬層。 如申請專利範圍第1 0項所述之形成自行對準金屬矽化 12· 13 · 物之方法，其中該混合氣體係為氬/氮（Ar/N混合 氣體者。 ，申請專利範圍第1項所述之形成自行對準金屬矽化 今Λ 、 法’其中形成金屬石夕化物之熱回火處理步驟係 ·、、、一溫度大於5 0 0°C之快速回火製程。 物申凊專利範圍第1項所述之形成自行對準金屬矽化 方法，其中對該金屬矽化物進行熱回火處理之步 糸為一溫度大於7 0 0°C之快速回火製程。Method, wherein the barrier layer is composed of a nitrided metal layer. The method of forming a self-aligned metal silicide as described in item 8 of the scope of patent application, wherein the nitrided metal layer is formed. The method is to perform a nitrogen ion cloth value on the metal layer, so that a part of the metal layer is transformed into the nitrided metal layer. 10. The method for forming a self-aligned metal silicide as described in item 8 of the scope of the patent application, wherein the nitrided metal layer is formed in a manner that a nitrogen-containing mixture is passed into the vacuum chamber at the same time as the metal layer is formed. The gas' converts part of the metal layer into the metal nitride layer. The method for forming a self-aligned metal silicide 12 · 13 · as described in item 10 of the scope of the patent application, wherein the mixed gas system is an argon / nitrogen (Ar / N mixed gas.) The method of forming self-aligned metal silicidation and the method of thermal tempering in which metal oxides are formed is described as a rapid tempering process at a temperature greater than 500 ° C. The self-aligned metal silicidation method described in item 1, wherein the step of thermally tempering the metal silicide is a rapid tempering process with a temperature greater than 700 ° C.