KR20030013882A - Method for manufacturing a silicide layer of semiconductor device - Google Patents
Method for manufacturing a silicide layer of semiconductor device Download PDFInfo
- Publication number
- KR20030013882A KR20030013882A KR1020010048124A KR20010048124A KR20030013882A KR 20030013882 A KR20030013882 A KR 20030013882A KR 1020010048124 A KR1020010048124 A KR 1020010048124A KR 20010048124 A KR20010048124 A KR 20010048124A KR 20030013882 A KR20030013882 A KR 20030013882A
- Authority
- KR
- South Korea
- Prior art keywords
- spacer
- silicon
- gate electrode
- silicide
- substrate
- Prior art date
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 abstract description 3
- 229910008486 TiSix Inorganic materials 0.000 abstract description 2
- 239000010936 titanium Substances 0.000 description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 11
- 229910021341 titanium silicide Inorganic materials 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- -1 nitrogen (N 2 ) ions Chemical class 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
Abstract
Description
본 발명은 반도체 제조방법에 관한 것으로서, 특히 실리사이드가 형성되지 않는 영역에 실리사이드반응이 일어나는 것을 방지하는 반도체소자의 실리사이드막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for manufacturing a silicide film of a semiconductor device for preventing a silicide reaction from occurring in a region where no silicide is formed.
현재, 반도체 소자의 집적도가 증가함에 따라 배선의 폭이 감소하여 배선의 면저항(sheet resistance)이 증가한다. 배선의 면저항이 증가하면, 집적회로 내에서 소자의 신호 전송 시간이 지연된다. 이를 방지하고자, 비저항이 낮으면서도 고온에서 안정한 고융점의 실리사이드(silicide) 물질을 트랜지스터의 게이트 전극뿐만 아니라 소오스/드레인 접합 부분에 추가함으로써 배선의 면저항 및 접촉 저항을 낮추었다. 이러한 실리사이드 물질은 주로 실리콘과 반응하는 희토류 금속을 이용한다. 실리사이드의 예를 들면, 텅스텐 실리사이드(WSi2), 티타늄 실리사이드(TiSi2), 코발트 실리사이드(CoSi2) 등이 있다.At present, as the degree of integration of semiconductor devices increases, the width of the wiring decreases, thereby increasing the sheet resistance of the wiring. As the sheet resistance of the wiring increases, the signal transmission time of the device in the integrated circuit is delayed. To prevent this, the sheet resistance and contact resistance of the wiring were lowered by adding a high melting silicide material having a low specific resistance and stable at high temperature to the source / drain junction portion as well as the gate electrode of the transistor. Such silicide materials mainly utilize rare earth metals that react with silicon. Examples of the silicide include tungsten silicide (WSi 2 ), titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), and the like.
한편, 종래 기술에 의한 반도체 소자의 실리사이드막 제조 방법은 다음과 같다.On the other hand, the silicide film manufacturing method of the semiconductor element by a prior art is as follows.
반도체기판으로서 실리콘 기판에 소자분리막을 형성하고, 기판 전면에 게이트산화막을 형성하고 그 위에 폴리실리콘이 패터닝된 게이트전극을 형성한다. 그리고나서 소정의 도전형 불순물을 저농도로 이온 주입하여 게이트전극의 에지에 셀프얼라인(self-align)된 LDD 영역을 형성한다. LDD 영역을 형성한 후에, 절연물질을 기판 전체에 형성하고, 이를 건식 식각 공정으로 식각하여 게이트전극의 측벽에 스페이서를 형성한다. 이어서, 결과물 전면에 LDD 영역과 동일한 도전형 불순물을 이온주입함으로써 스페이서에 셀프얼라인된 소오스/드레인 접합을 형성함으로써 LDD 구조의 모스 트랜지스터를 완성한다.A device isolation film is formed on a silicon substrate as a semiconductor substrate, a gate oxide film is formed on the entire surface of the substrate, and a polysilicon patterned gate electrode is formed thereon. Then, a predetermined conductivity type impurity is implanted at low concentration to form a self-aligned LDD region at the edge of the gate electrode. After the LDD region is formed, an insulating material is formed over the entire substrate, and the substrate is etched by a dry etching process to form spacers on sidewalls of the gate electrode. Subsequently, a MOS transistor having an LDD structure is completed by forming a self-aligned source / drain junction in the spacer by ion implantation of the same conductivity type impurity as the LDD region over the entire surface of the resultant.
그 다음, LDD 구조의 모스 트랜지스터에 실리사이드 공정을 적용하는데, 이는 다음과 같다. 먼저 결과물 전면에 실리사이드 반응을 일으키는 금속으로서, 티타늄(Ti)을 증착하고 어닐링 공정을 실시하여 게이트전극 및 소오스/드레인 접합의 표면에서 티타늄이 해당 영역의 실리콘과 반응을 하여 실리사이드막을 형성한다. 이때, 스페이서의 질소는 티타늄과 반응을 잘 하지 않는다. 그러므로, 어닐링 공정시 스페이서 표면에만 티타늄이 남아 있게 된다. 그리고나서 게이트전극 및 소오스/드레인 접합의 표면에 형성된 실리사이드막을 제외한 미반응된 스페이서 표면의 티타늄을 제거한다. 이때 티타늄의 제거는 습식 식각 공정으로 한다.Next, a silicide process is applied to the MOS transistor of the LDD structure, which is as follows. First, as a metal causing a silicide reaction on the entire surface of the resultant, titanium (Ti) is deposited and annealing is performed to form a silicide film by titanium reacting with silicon in a corresponding region on the surface of the gate electrode and the source / drain junction. At this time, the nitrogen of the spacer does not react well with titanium. Therefore, titanium remains only on the spacer surface during the annealing process. Then, titanium on the surface of the unreacted spacer except for the silicide film formed on the surface of the gate electrode and the source / drain junction is removed. At this time, the removal of titanium is a wet etching process.
상술된 종래 기술의 실리사이드막 제조 방법은 게이트전극 및 소오스/드레인 접합 표면에 각각 실리사이드막을 형성함으로써 게이트전극의 비저항과 소오스/ 드레인의 접촉저항을 낮출 수 있었다.In the above-described method of manufacturing a silicide film, a silicide film is formed on the gate electrode and the source / drain junction surfaces, respectively, to lower the specific resistance of the gate electrode and the contact resistance of the source / drain.
그러나, 실리사이드 반응을 위한 어닐링 공정시, LDD 영역을 정의하는 스페이서의 절연물질내의 실리콘 또는 스페이서와 게이트전극/ 기판이 접하는 모트(moat) 부분에서의 실리콘이 금속과 반응하여 불필요한 영역에 실리사이드막을 형성하게 된다. 이러한 스페이서의 모트 부분에 생성된 실리사이드막은 미반응된 금속막의 제거시 제거되지 않고 남아 있게 된다. 이렇게 스페이서의 모트 부분에 남아 있는 실리사이드막은 소자 작동시 게이트전극과 소오스/드레인 접합의 누설 전류를 야기시키는 원인으로 작용하게 된다.However, in the annealing process for the silicide reaction, silicon in the insulating material of the spacer defining the LDD region or silicon in the moat portion where the spacer and the gate electrode / substrate contact with the metal react with the metal to form the silicide film in the unnecessary region. do. The silicide film formed in the mote portion of the spacer remains unremoved upon removal of the unreacted metal film. The silicide film remaining in the mote portion of the spacer acts as a cause of leakage current between the gate electrode and the source / drain junction during device operation.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 리모트 플라즈마 어닐링 공정을 이용하여 스페이서 표면에 실리콘 확산을 억제하는 실리콘 확산방지막을 얇게 형성함과 동시에 게이트전극 및 소오스/드레인 접합 표면에 금속 실리사이드막을 형성하므로써 스페이서 표면의 실리콘 확산방지막에 의해 스페이서의 모트 부분에 발생하는 실리사이드막의 생성을 미연에 방지할 수 있는 반도체소자의 실리사이드막 제조방법을 제공하고자 한다.An object of the present invention is to solve the problems of the prior art by using a remote plasma annealing process to form a thin silicon diffusion barrier to suppress the diffusion of silicon on the spacer surface and at the same time metal silicide on the gate electrode and the source / drain junction surface By forming a film, a method of manufacturing a silicide film of a semiconductor device capable of preventing generation of a silicide film generated in a mote portion of a spacer by a silicon diffusion barrier film on the surface of the spacer.
이러한 목적을 달성하기 위하여 본 발명은 실리사이드막을 갖는 반도체소자의 제조 방법에 있어서, 실리콘 기판에 폴리실리콘으로 게이트전극을 형성하고, 게이트전극 측벽에 질화물질로 스페이서를 형성하는 단계와, 게이트전극 및 스페이서를 마스크로 삼아 기판내에 도전형 불순물을 주입하여 소오스/드레인 접합을 형성하는 단계와, 기판 전면에 금속막을 증착하는 단계와, 기판 전면에 리모트 플라즈마 어닐링으로 스페이서의 표면 및 모트 부분에 실리콘 확산방지막을 형성함과 동시에 게이트전극 및 소오스/드레인 접합 표면에 금속 실리사이드막을 형성하는 단계와, 실리콘과 미반응된 금속을 제거하면서 실리콘 확산방지막을 제거하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device having a silicide film, the method comprising: forming a gate electrode with polysilicon on a silicon substrate, and forming a spacer with a nitride material on the sidewall of the gate electrode; Forming a source / drain junction by implanting a conductive impurity into the substrate using a mask as a mask, depositing a metal film on the entire surface of the substrate, and depositing a silicon diffusion barrier on the surface of the spacer and the mote by remote plasma annealing on the entire surface of the substrate. And forming a metal silicide film on the gate electrode and the source / drain junction at the same time, and removing the silicon diffusion barrier layer while removing silicon and unreacted metal.
도 1 내지 도 5는 본 발명에 따른 반도체소자의 실리사이드막 제조 방법을 설명하기 위한 공정순서도.1 to 5 are process flowcharts for explaining a silicide film manufacturing method of a semiconductor device according to the present invention.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 반도체소자의 실리사이드막 제조 방법을 설명하기 위한 공정순서도이다.1 to 5 are process flowcharts for explaining a silicide film manufacturing method of a semiconductor device according to the present invention.
도 1에 도시된 바와 같이 종래 기술과 동일하게 반도체기판으로서 실리콘 기판(10)에 소자의 활성 영역과 비활성 영역을 분리하는 소자분리막(12)을 형성하고, 기판에 LDD 구조의 모스 트랜지스터(20)를 형성한다. 즉, 모스 트랜지스터(20)의 제조 과정은 기판(10) 전면에 게이트산화막(미도시함)을 형성하고 그 위에 폴리실리콘이 패터닝된 게이트전극(22)을 형성한다. 그리고나서 소정의 도전형 불순물을 저농도로 이온 주입하여 게이트전극(22)의 에지에 셀프얼라인(self-align)된 LDD 영역(24)을 형성한다. LDD 영역(24)을 형성한 후에, 절연물질로서 질화물을 기판 전체에 증착하고, 이를 건식 식각 공정으로 식각하여 게이트전극(22)의 측벽에 스페이서(26)를 형성한다. 이어서, 결과물 전면에 LDD 영역(24)과 동일한 도전형 불순물을 이온주입함으로써 스페이서(26)에 셀프얼라인된 소오스/드레인 접합(28)을 형성한다.As shown in FIG. 1, a device isolation film 12 is formed on the silicon substrate 10 as a semiconductor substrate to separate active and inactive regions of a device, and a MOS transistor 20 having an LDD structure is formed on the substrate. To form. That is, in the manufacturing process of the MOS transistor 20, a gate oxide film (not shown) is formed on the entire surface of the substrate 10, and the gate electrode 22 having the polysilicon patterned thereon is formed thereon. Then, a predetermined conductivity type impurity is implanted at low concentration to form a self-aligned LDD region 24 at the edge of the gate electrode 22. After the LDD region 24 is formed, nitride is deposited on the entire substrate as an insulating material, which is etched by a dry etching process to form spacers 26 on sidewalls of the gate electrode 22. Subsequently, the self-aligned source / drain junction 28 is formed on the spacer 26 by ion implantation of the same conductivity type impurity as the LDD region 24 on the entire surface of the resultant.
이와 같은 LDD 구조의 모스 트랜지스터(20)에 본 발명에 따른 실리사이드 공정을 실시한다.The silicide process according to the present invention is performed on the MOS transistor 20 having such an LDD structure.
도 2에 도시된 바와 같이, 트랜지스터(20)가 형성된 기판(10) 전면에 실리사이드 반응을 일으키는 금속(30)으로서, 티타늄(Ti)을 증착한다.As shown in FIG. 2, titanium (Ti) is deposited as the metal 30 causing the silicide reaction on the entire surface of the substrate 10 on which the transistor 20 is formed.
그 다음 도 3에 도시된 바와 같이, 기판 전면에 리모트 플라즈마 어닐링(Remote Plasma Annealing)을 실시하여 스페이서(26)의 표면 및 모트(moat) 부분에 얇은 실리콘 확산방지막(32)을 형성함과 동시에 게이트전극(22) 및 소오스/드레인 접합(28) 표면에 티타늄 실리사이드막(TiSix)(34)을 형성한다. 이때, 본 발명의 리모트 플라즈마 어닐링 조건은 700℃∼780℃의 온도에서 압력을 5∼15Torr로 한다. 플라즈마에 의해 주입되는 이온은 질소, 아르곤, 산소 중에서 어느 하나인 것이 바람직하나, 본 실시예에서는 질소(N2) 이온을 사용하였다.Next, as shown in FIG. 3, a remote plasma annealing is performed on the entire surface of the substrate to form a thin silicon diffusion barrier 32 on the surface and the moat portion of the spacer 26. A titanium silicide layer (TiSix) 34 is formed on the surface of the electrode 22 and the source / drain junction 28. At this time, the remote plasma annealing condition of the present invention sets the pressure to 5 to 15 Torr at a temperature of 700 ° C to 780 ° C. The ion implanted by the plasma is preferably any one of nitrogen, argon, and oxygen. In this embodiment, nitrogen (N 2 ) ions are used.
본 발명은 이와 같은 리모트 플라즈마 어닐링 공정에 의해 스페이서(26) 표면 및 모트 부분에 질소(N2)가 풍부한 실리콘 확산방지막(32)이 형성된다. 이때, 실리콘 확산방지막(32)은 질소(N2) 이온이 하부 티타늄(Ti)과 반응한 티타늄질화막(TiN)이다. 그리고, 리모트 플라즈마 어닐링 공정에 의해 생성된 티타늄 실리사이드막(34)은 비저항이 높은 C49 형태를 갖는다.According to the present invention, a silicon diffusion barrier 32 rich in nitrogen (N 2 ) is formed on the surface of the spacer 26 and the mote portion by the remote plasma annealing process. In this case, the silicon diffusion barrier 32 is a titanium nitride film (TiN) in which nitrogen (N 2 ) ions react with the lower titanium (Ti). The titanium silicide film 34 produced by the remote plasma annealing process has a C49 shape with high specific resistance.
그러므로, 본 발명은 스페이서(26)의 표면 및 모트 부분에 형성된 실리콘 확산방지막(32)에 의해 스페이서(26)의 실리콘(Si) 원자가 티타늄막(30) 쪽으로 확산되는 것을 막아 스페이서(26)의 모트 부분에서 발생하는 실리사이드막의 반응이 억제된다.Therefore, the present invention prevents the silicon (Si) atoms of the spacer 26 from diffusing toward the titanium film 30 by the silicon diffusion barrier 32 formed on the surface and the mote portion of the spacer 26. The reaction of the silicide film occurring at the portion is suppressed.
그 다음 도 4에 도시된 바와 같이, 게이트전극(22) 및 소오스/드레인 접합(28) 표면에 있는 실리사이드막(34)을 제외하고 실리콘과 미반응한 스페이서(26) 표면의 티타늄(30)을 제거하면서 실리콘 확산방지막(32)을 함께 제거한다. 이때, 티타늄(30) 및 실리콘 확산방지막(32)의 제거는 습식 식각공정으로 진행한다.Next, as shown in FIG. 4, except for the silicide layer 34 on the gate electrode 22 and the source / drain junction 28, titanium 30 on the surface of the spacer 26 that is not reacted with silicon is removed. While removing, the silicon diffusion barrier 32 is removed together. At this time, the removal of the titanium 30 and the silicon diffusion barrier 32 proceeds to a wet etching process.
추가적으로 본 발명은 도 5에 도시된 바와 같이, 기판(10) 전면에 급속 열처리 어닐링(Rapid Thermal Annealing)을 910℃의 온도에서 실시함으로써 티타늄 실리사이드막(34)의 상변태를 일으켜서 실리사이드막의 비저항을 낮춘다. 이로 인해, 티타늄 실리사이드막(34)은 이전 어닐링에 의해 비저항이 높은 C49상을 갖지만, 후속 급속 열처리 어닐링 공정에 의해 비저항이 낮은 C54로 상 변태가 일어난다.In addition, as shown in FIG. 5, rapid thermal annealing is performed on the entire surface of the substrate 10 at a temperature of 910 ° C. to cause phase transformation of the titanium silicide layer 34 to lower the specific resistance of the silicide layer. For this reason, the titanium silicide film 34 has a high specific resistance C49 phase by the previous annealing, but the phase transformation occurs to a low specific resistance C54 by the subsequent rapid heat treatment annealing process.
이상 설명한 바와 같이, 본 발명은 리모트 플라즈마 어닐링에 의해서 스페이서의 표면 및 모트 부분에 발생하는 실리콘의 확산을 억제하여 실리사이드막의 생성을 최대한 방지한다. 이로 인해 본 발명은 실리사이드화되지 않은 금속막 제거시 스페이서의 모트 부분에 잔류하는 금속(또는 실리사이드막)을 모두 제거하여 이후 스페이서의 모트 부분에 잔류하는 실리사이드막에 의해 발생하는 게이트전극과 소오스/드레인 접합의 누설 전류 효과를 방지할 수 있다.As described above, the present invention suppresses the diffusion of silicon generated on the surface and the mote portion of the spacer by remote plasma annealing to prevent the generation of the silicide film as much as possible. Accordingly, the present invention removes all metal (or silicide film) remaining in the mote portion of the spacer when the non-silicided metal film is removed, and then gate electrode and source / drain generated by the silicide film remaining in the mote portion of the spacer. The leakage current effect of the junction can be prevented.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010048124A KR100588686B1 (en) | 2001-08-10 | 2001-08-10 | Method for manufacturing a silicide layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010048124A KR100588686B1 (en) | 2001-08-10 | 2001-08-10 | Method for manufacturing a silicide layer of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030013882A true KR20030013882A (en) | 2003-02-15 |
| KR100588686B1 KR100588686B1 (en) | 2006-06-13 |
Family
ID=27718599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010048124A KR100588686B1 (en) | 2001-08-10 | 2001-08-10 | Method for manufacturing a silicide layer of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100588686B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100621835B1 (en) * | 2005-03-08 | 2006-09-19 | (주)무선스포트 | Controller used in a fire engine |
| KR100666660B1 (en) * | 2005-05-10 | 2007-01-10 | 주식회사 한우티엔씨 | Automatic check device of fire truck with aerial ladder |
| KR100763898B1 (en) * | 2003-08-02 | 2007-10-05 | 삼성전자주식회사 | Fabrication method of semiconductor device and semiconductor device fabricated using the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100842669B1 (en) * | 2006-12-15 | 2008-06-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and the Fabricating Method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2682410B2 (en) * | 1993-12-13 | 1997-11-26 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR100403321B1 (en) * | 1996-06-05 | 2004-02-14 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100190060B1 (en) * | 1996-07-16 | 1999-06-01 | 윤종용 | Silicide forming method |
| KR100455367B1 (en) * | 1997-06-10 | 2005-01-17 | 삼성전자주식회사 | Formation method of self-aligned silicide layer using ammonia plasma |
-
2001
- 2001-08-10 KR KR1020010048124A patent/KR100588686B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763898B1 (en) * | 2003-08-02 | 2007-10-05 | 삼성전자주식회사 | Fabrication method of semiconductor device and semiconductor device fabricated using the same |
| KR100621835B1 (en) * | 2005-03-08 | 2006-09-19 | (주)무선스포트 | Controller used in a fire engine |
| KR100666660B1 (en) * | 2005-05-10 | 2007-01-10 | 주식회사 한우티엔씨 | Automatic check device of fire truck with aerial ladder |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100588686B1 (en) | 2006-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6777275B1 (en) | Single anneal for dopant activation and silicide formation | |
| KR20040029119A (en) | Improved high k-dielectrics using nickel silicide | |
| US7468303B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6258682B1 (en) | Method of making ultra shallow junction MOSFET | |
| KR100588686B1 (en) | Method for manufacturing a silicide layer of semiconductor device | |
| JP3129867B2 (en) | Method for manufacturing semiconductor device | |
| KR100395776B1 (en) | Method for manufacturing a silicide layer of semiconductor device | |
| KR100313089B1 (en) | Method for manufacturing semiconductor device | |
| JP3362722B2 (en) | Method for manufacturing semiconductor device | |
| KR100355868B1 (en) | manufacturing method of semiconductor device | |
| JPH07201777A (en) | Manufacture of semiconductor device | |
| KR100192537B1 (en) | Method of manufacturing semiconductor device | |
| KR100628253B1 (en) | Method for Forming Self-Aligned Silcide of Semiconductor Device | |
| KR100604496B1 (en) | Method for fabricating semiconductor device | |
| JP3094914B2 (en) | Method for manufacturing semiconductor device | |
| KR100255008B1 (en) | Manufacture method of semiconductor apparatus | |
| KR100486649B1 (en) | Method for forming salicide of a semiconductor device | |
| KR100276876B1 (en) | How to compensate silicide lost after contact etching | |
| KR100580770B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR20000055596A (en) | Method for forming gate electrode with polycide structure | |
| KR100348310B1 (en) | method for manufacturing of semiconductor device | |
| JP2636787B2 (en) | Method for manufacturing semiconductor device | |
| KR100628214B1 (en) | method for manufacturing of semiconductor device | |
| KR19980040671A (en) | Salicide Formation Method of Semiconductor Device | |
| KR100444720B1 (en) | Method for manufacturing salicide layer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100518 Year of fee payment: 5 |
|
| LAPS | Lapse due to unpaid annual fee |