TW531795B

TW531795B - Self-aligned metal silicide process using cobalt silicide

Info

Publication number: TW531795B
Application number: TW91103637A
Authority: TW
Inventors: Chi-Kang Liu; Tien-Chi Ke; Hsin-Li Cheng
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-02-27
Filing date: 2002-02-27
Publication date: 2003-05-11

Abstract

A self-aligned metal silicide process using cobalt silicide is provided and is suitable for semiconductor substrate. First, form a gate structure that is composed by gate insulated layer, gate conductor layer and gate spacer layer on the substrate. Second, form source/drain area on the substrate on both sides of the gate structure. Deposit a cobalt metal layer on the gate structure and source/drain area. Then execute a first thermal process to form first cobalt silicide (Co-Si2) on the surfaces of the gate conductor layer and source/drain area. Remove the other cobalt layer un-reacted into the first cobalt silicide. Third, implant silicon ions into the gate conductor layer and source/drain area. Finally, execute a second thermal process to react the first cobalt silicide, Co-Six into the second cobalt silicide.

Description

531795 五、發明說明（1) --- 本發明係有關於一種自行對準金屬矽化物 (self-aligned silicidation or SALICIDE)製程，特別有關1一種使用矽化鈷之自行對準金屬矽化物製程。 ^政著電子裝置之漸趨複雜，積體電路如金氧半（M〇s) 電晶體的尺寸也日愈縮小，因此，就電晶體之通道區而令，源/汲極的阻值亦相對提高。有鑑於此，為了降低阻值。並保持金屬層與M0S電晶體間的淺接面，傳統技術揭露了一種自行對準金屬矽化物製程，如第丨A至丨E圖所示。首先依據第1A圖，一基本M0S結構係形成於一半導體基底10上，例如先以場氧化層n隔離出一主動區，傳統積，電路製程如沈積、微影及姓刻步驟於主動區形成 /一/Ifrt化層12、複晶矽閘極14、閘極絕緣間隔層20和源 /沒極區1 6。然後如第1B圖所* ’沈積一金屬層3 鑛製程全面性沈積一具有良好以…ii 】在=,銘或翻層’在此以金屬鈦層為例，其特性 ίίΐ:开之！能與石夕產生反應形成石夕化鈦，並藉由之化合物…，在石夕和鈦介面間可形成良好之歐姆接觸。其-人’如第1 C圖所示，實你一笛 .. Γ製程叫溫度約介二:二敛Π晶；問極14及源/汲極16表面形成石夕係留;虛緣間隔層20及場氧化層11表面係邊下剩餘未與矽反應之金屬鈦層。531795 5. Description of the invention (1) --- The present invention relates to a self-aligned silicidation or SALICIDE process, and particularly relates to a self-aligned metal silicide process using cobalt silicide. ^ The electronic devices are becoming more and more complicated, and the size of integrated circuits such as metal oxide (M0s) transistors is shrinking. Therefore, the source / drain resistance of the transistor is also affected by the channel area of the transistor. Relatively improved. In view of this, in order to reduce the resistance value. While maintaining the shallow junction between the metal layer and the MOS transistor, traditional techniques have revealed a self-aligned metal silicide process, as shown in Figures A through E. First, according to FIG. 1A, a basic MOS structure is formed on a semiconductor substrate 10. For example, an active area is first isolated by a field oxide layer n. Traditional product, circuit processes such as deposition, lithography, and engraving steps are formed in the active area. / A / Ifrt layer 12, polycrystalline silicon gate 14, gate insulating spacer 20, and source / inverter region 16. Then as shown in Figure 1B * ’, a metal layer is deposited, and the 3 ore process is comprehensively deposited. It has a good ... ii] In =, Ming or turned layer’ Here, take the titanium metal layer as an example, its characteristics ίί: Kaizhi! It can react with Shixi to form Shixi Titanium, and with its compound ..., it can form a good ohmic contact between Shixi and the titanium interface. Its-person 'is shown in Figure 1C. The process of Γ is called temperature introduction: two convergent Π crystals; the surface of the interrogation pole 14 and the source / drain pole 16 forms a stone evening mooring; The surface of 20 and field oxide layer 11 is a titanium metal layer which does not react with silicon.

531795531795

接耆’依據第ID圖，除去在絕緣間隔層2〇及 π表面剩餘未與矽反應之金屬鈦層，舉例而古，=彳匕層 T刻，例如連續兩道濕餘刻製程，其中第一道則=硫酸和雙氧水之混合液為蝕刻劑。前述濕蝕刻製^ 以’合解剩餘未反應之金屬鈦層3〇，但不會溶蝕矽化‘化人物31，故在絕緣間隔層20及場氧化層丨丨表面剩餘未與秒^ 應之金屬鈦層30將因此去除，而留下在複晶矽閘極“及源 /汲極1 6表面之矽化鈦化合物3丨。、Then, according to the ID chart, remove the remaining titanium metal layer that has not reacted with silicon on the surfaces of the insulating spacers 20 and π. For example, the metal layer is T-cut, for example, two consecutive wet-etching processes. One rule = a mixture of sulfuric acid and hydrogen peroxide is used as an etchant. The aforementioned wet etching method ^ uses the remaining unreacted metal titanium layer 30 to "combine the solution, but does not dissolve the silicified character 31", so the remaining metal on the insulating spacer layer 20 and the field oxide layer 丨丨 surface does not correspond to the second metal. As a result, the titanium layer 30 will be removed, leaving the titanium silicide compound 3 丨 on the surface of the polycrystalline silicon gate "and the source / drain electrode 16".

其次，實施一第二熱製程，如快速熱退火製程（RTp) 、，溫度約介於80 0。(：至900 t：之間。經由此熱退火步驟，在複晶石夕閘極1 4及源/汲極1 6表面之矽化鈦化合物3丨的阻值可以降低。然而，上述之矽化鈦化合物（TiSi2))的晶粒尺寸約為 0.2微米’為了往後更細微尺寸之積體電路的製程需要，因此在0 · 1 8微米世代以下製程則應用矽化鈷之自行對準金屬矽化物製程，但在實際製程經驗上發現於實施第二熱製程後會有石夕化始化合物之皺摺（agg 1 〇mera t i on)缺陷產生。經由實際研究發現此缺陷之形成因素，乃由於？+型態之源/汲極摻雜係使用BF2作為摻雜離子，而在實施第一熱製 _ 程後BF2中之氟離子會造成矽化鈷化合物（Co-Six)中之矽濃度之不足而導致實施第二熱製程後會產生矽化鈷化合物之皺摺，進而使得良率降低。為了解決上述問題及往後更細微尺寸之積體電路的製Second, a second thermal process, such as a rapid thermal annealing process (RTp), is performed at a temperature of about 80 ° C. (: To 900 t: between. Through this thermal annealing step, the resistance value of the titanium silicide compound 3 on the surface of the polycrystalline silicon gate 14 and the source / drain electrode 16 can be reduced. However, the above-mentioned titanium silicide The compound (TiSi2)) has a grain size of about 0.2 microns. In order to process the integrated circuits with a finer size in the future, the processes below 0. 18 microns should use the self-aligned metal silicide process of cobalt silicide. However, in actual process experience, it is found that after the second thermal process is performed, agglomeration (agg 1 omera ti on) defects of the stone oxidative starting compound are generated. What is the reason for the formation of this defect through actual research? + -Type source / drain doping uses BF2 as doping ions, and the fluorine ion in BF2 will cause insufficient silicon concentration in cobalt silicide compound (Co-Six) after the first thermal process As a result, wrinkles of the cobalt silicide compound are generated after the second thermal process is performed, thereby reducing the yield. In order to solve the above problems and the fabrication of integrated circuits with a finer size in the future

0503-6982TW ； TSMC2001-0926 ； ycchen.ptd 第5頁丄 /y：> 五發明說明（3) Ϊ : ί r本=開發改良的使用矽化鈷之自行對準金屬石夕生猎：=:植入㈣子以防止辦化合物右鞭认L解述習知技術之缺點。 I r ^ Γ 1本發明之目的在於提供一種使用矽化鈷之 I ^及梯、’矽化物製程，其可防止矽化鈷化合物之皺摺發生及增加後續製程的良率。杆科ίϊϊ上述之目的，本發明提出―種使_化姑之自 :::金屬矽化物製程’適用於一半導體基底，首先於此 =體基底上形成一由閘極絕緣層、閘極導電層和閘極間 =組成之閘極結m ’其次，於此閘極結構兩側之此半導 _ 土底形成一源/汲極區。接著，於此源/汲極表面和此閘極結構表面上形成一鈷金屬層。之後，施行一第一熱製程以在此閘極導電層及此源/汲極表面形成第一矽化鈷（c〇_ s I2)化合物。然後’去除未反應成此第一矽化鈷化合物之其他鈷金屬層。其次，於此閘極導電層及此源/汲極内植入矽離子。最後，施行第二熱製程使第一矽化鈷化合物 (Co-Six)反應成第二矽化鈷化合物（c〇-Si2)。 « 以下’就圖式說明本發明之一種使用矽化鈷之自行對準金屬矽化物製程實施例。【圖式簡單說明】第1 A至第1 D圖係顯示傳統之金屬矽化物之製程剖面圖。第2 A至第2 E圖係代表本發明之一實施例中，使用石夕化鈷之自行對準金屬矽化物製程剖面圖。0503-6982TW; TSMC2001-0926; ycchen.ptd Page 5 丄 / y: > Explanation of the five inventions (3) Ϊ: rr = development and improvement of self-aligning metal stone using cobalt silicide: =: Implants of gardenia are used to prevent compounds from right-flapping and explain the shortcomings of conventional techniques. I r ^ Γ 1 The purpose of the present invention is to provide an I ^ and ladder, 'silicide process using cobalt silicide, which can prevent the occurrence of wrinkles of the cobalt silicide compound and increase the yield of subsequent processes. For the above purpose, the present invention proposes "a method for making a chemical compound ::: metal silicide process" applicable to a semiconductor substrate. First, a gate insulating layer and a gate conductive layer are formed on the body substrate. Between the layer and the gate = the gate junction m 'composed of the second, the source / drain region is formed by the semiconducting soil on both sides of the gate structure. Next, a cobalt metal layer is formed on the source / drain surface and the gate structure surface. After that, a first thermal process is performed to form a first cobalt silicide (co_s I2) compound on the gate conductive layer and the source / drain surface. Then, the other cobalt metal layers which have not reacted into this first cobalt silicide compound are removed. Secondly, silicon ions are implanted into the gate conductive layer and the source / drain. Finally, a second thermal process is performed to react the first cobalt silicide compound (Co-Six) to a second cobalt silicide compound (co-Si2). «The following" illustrates an embodiment of a self-aligned metal silicide process using cobalt silicide according to the present invention. [Brief description of the drawings] Figures 1A to 1D are cross-sectional views showing the traditional metal silicide process. Figures 2A to 2E are cross-sectional views of a self-aligned metal silicide process using petrified cobalt in one embodiment of the present invention.

0503-6982TW ； TSMC2001-0926 ； ycchen.ptd 第6頁 531795 發明說明（4) 第3圖係代表本發明之第二實施例中，使用石夕化鈷之自行對準金屬矽化物製程剖面圖。 [符號說明] 場氧化層〜11 ; 複晶石夕閘極〜1 4 ; 源/沒極區〜1 6 ; 矽化鈦化合物〜3 1 ; 閘極氧化層〜1 〇 1 ; 閘極結構〜G ; 源/汲極區〜1 〇 6 ; 覆蓋層〜11〇 ; 植入矽離子〜114、120。半導體基底〜10 ; 閘極氧化層〜1 2 ; 閘極絕緣間隔層〜2 0 ; 金屬層〜30 ; 半導體基底〜100 ; 複晶矽閘極〜1 0 2 ; 閘極間隔層〜1 0 4 ; 金屬層〜1 0 8 ; 矽化化合物〜11 0、1 1 8 ; 實施例1 凊參閱第2 A至2 D圖’其顯示本發明之一實施例中，一種使用矽化鈷之自行對準金屬矽化物製程。首先依據第2A圖，本實施例適用於一半導體基底 100，如由矽（silicon)半導體材質所構成，形^方式則有蟲晶（expitaxial )或絕緣層上有矽（silic〇n 〇n insulator )等，為方便說明，在此以一矽基底為例。然後定義出電晶體所在之主動區，例如利用區域氧化法（LOCOS)或淺溝隔離製程（STI)來形成一場絕緣層 (field insulator)，並藉該場絕緣層來隔離出曰主動區 (active area)。再依據傳統積體電路製程如沈積、影及蝕刻步驟於主動區形成一閘極絕緣層1〇1、閘$電0503-6982TW; TSMC2001-0926; ycchen.ptd page 6 531795 Description of the invention (4) Figure 3 represents a cross-sectional view of a self-aligned metal silicide process using cobalt sulfide in the second embodiment of the present invention. [Symbol description] Field oxide layer ~ 11; polycrystalline stone gate ~ 1 4; source / inverted region ~ 16; titanium silicide compound ~ 3 1; gate oxide layer ~ 1 〇1; gate structure ~ G ; Source / drain region ~ 1 06; cover layer ~ 11 ;; implanted silicon ions ~ 114,120. Semiconductor substrate ~ 10; Gate oxide layer ~ 12; Gate insulation spacer layer ~ 20; Metal layer ~ 30; Semiconductor substrate ~ 100; Polycrystalline silicon gate ~ 1 0 2; Gate spacer layer ~ 1 0 4 Metal layer ~ 1 0 8; Silicide compound ~ 11 0, 1 1 8; Example 1 凊 Refer to Figures 2 A to 2 D ', which shows an example of the present invention, a self-aligned metal using cobalt silicide Silicide process. Firstly, according to FIG. 2A, this embodiment is applicable to a semiconductor substrate 100. For example, the semiconductor substrate 100 is made of silicon semiconductor material, and the shape of the semiconductor substrate is expitaxial or silicon (silicon ON insulator). ), Etc., for the convenience of explanation, a silicon substrate is taken as an example here. Then define the active area where the transistor is located. For example, a field insulator (LOCOS) or shallow trench isolation process (STI) is used to form a field insulator, and the field insulation is used to isolate the active area. area). Then, a gate insulating layer 101 and a gate electrode are formed in the active area according to the traditional integrated circuit manufacturing processes such as deposition, shadowing and etching steps.

531795 五、發明說明（5) 層（複晶石夕閘極）1 〇 2、閘極間隔層丨〇 4所構成之閘極結構 G ° 然後’利用如離子植入法或擴散方式，於閘極結構G 兩側之半導體基底位置形成源/汲極1〇6。接著’請再參閱第2 A圖，先順應性（C 〇 n f 〇 r m a b 1 e)形成一始金屬層108，以覆蓋如源/汲極丨〇6表面、絕緣間隔層1 0 4外側壁、上側壁和複晶矽閘極丨〇 2上表面，例如，以直流（DC)磁控濺鍍製程順應性沈積一具有良好氧吸能力之始金屬層1 0 8，其特性為在適當之溫度下，能與矽產生反應形成石夕化鈷，並藉由交互擴散形成低阻值之化合物，因此，在矽和鈷介面間可形成良好之歐姆接觸。上述金屬層亦可利用例如物理氣相沉積法（以下簡稱為pVE)法）或化學氣相沉積法（以下簡稱為CVD法）來形成，且其材質可為擇自翻（Pt)、鈦（Ti)、鎳（Ni)、銘（Co)及斜（Er)中之一者，而所形成之金屬層厚度較佳的範圍為5〇至150埃。其次，全面性形成一覆蓋層110以覆蓋鈷金屬層1〇8，例如利用化學氣相沈積製程沈積一厚度約2〇〇至3〇〇 A之氮化鈦層11 〇，以覆蓋鈷金屬層1 〇 8。再者，請參閱第2B圖，進行金屬矽化物製程。例如，實施一第一熱製程，如快速熱退火製程（RTP)，溫度約介於4 0 0 °C至6 0 0 °C之間施行30秒〜2分鐘。經由此熱退火步驟，鈷和複晶矽閘極102及源/汲極106表面形成第一石夕化鈷化合物（Co-Six)l 12。其中，在絕緣間隔層104表面係留下剩餘未與矽反應之鈷金屬層。然後，去除覆蓋層丨丨〇，531795 V. Description of the invention (5) layer (polycrystalline stone gate) 1 〇2, the gate structure composed of gate spacer 丨〇 4 and then 'using, for example, ion implantation or diffusion methods, in the gate The source / drain 106 is formed on the semiconductor substrate on both sides of the electrode structure G. Next, please refer to FIG. 2A again. First, conformity (C0nf 0rmab 1e) is formed to form an initial metal layer 108 to cover the source / drain surface, the insulating spacer layer 104 outer wall, The upper side wall and the upper surface of the polycrystalline silicon gate 丨〇2, for example, a direct metal (DC) magnetron sputtering process is compliant to deposit a starting metal layer 1 0 8 with good oxygen absorption capacity, which is characterized at an appropriate temperature Then, it can react with silicon to form cobalt sulfide, and form a low-resistance compound through cross-diffusion. Therefore, a good ohmic contact can be formed between the silicon and cobalt interfaces. The above metal layer can also be formed by, for example, a physical vapor deposition method (hereinafter referred to as pVE method) or a chemical vapor deposition method (hereinafter referred to as CVD method), and its material can be selected from Pt, titanium ( Ti), nickel (Ni), indium (Co) and oblique (Er), and the thickness of the metal layer formed is preferably in the range of 50 to 150 angstroms. Secondly, a cover layer 110 is comprehensively formed to cover the cobalt metal layer 108. For example, a chemical vapor deposition process is used to deposit a titanium nitride layer 110 having a thickness of about 2000 to 300 A to cover the cobalt metal layer. 1 〇8. Moreover, please refer to FIG. 2B for the metal silicide process. For example, a first thermal process, such as a rapid thermal annealing process (RTP), is performed at a temperature between about 400 ° C and 600 ° C for 30 seconds to 2 minutes. After this thermal annealing step, the first petrified cobalt compound (Co-Six) 112 is formed on the surfaces of the cobalt and the polycrystalline silicon gate 102 and the source / drain 106. Among them, a cobalt metal layer remaining unreacted with silicon remains on the surface of the insulating spacer layer 104. Then, remove the cover layer 丨丨〇,

0503-6982TW ; TSMC2001-0926 i ycchen.ptd 第8頁 5317950503-6982TW; TSMC2001-0926 i ycchen.ptd page 8 531795

=使用反應性離子蝕刻法（RIE : reactive i〇n etch)之渴餘刻方式，除去覆蓋層丨丨〇。 …、接著，凊參閱第2C圖，除去在絕緣間隔層1 〇4表面剩餘未與矽反應之鈷金屬層，舉例而言，可利用選擇性蝕，例如連續兩道濕蝕刻製程，其中第一道蝕刻製程係以氨水和，氧水之混合液為蝕刻劑，第二道蝕刻製程則以硫酸和雙氧水之混合液為蝕刻劑。前述濕蝕刻製程可以溶解剩餘未反應之鈷金屬層1 〇 8，但不會溶蝕矽化鈷化合物丨丨2，= Using a reactive ion etching method (RIE) to remove the cover layer. …, Next, referring to FIG. 2C, remove the cobalt metal layer remaining on the surface of the insulating spacer layer 104 that has not reacted with silicon. For example, selective etching can be used, for example, two consecutive wet etching processes, of which the first The etching process uses a mixture of ammonia and oxygen water as an etchant, and the second etching process uses a mixture of sulfuric acid and hydrogen peroxide as an etchant. The aforementioned wet etching process can dissolve the remaining unreacted cobalt metal layer 108, but will not dissolve the cobalt silicide compound.

因此，在絕緣間隔層1 〇4表面剩餘未與矽反應之鈷金屬層 1 〇 8被去除’而留下在複晶矽閘極1 〇 2及源/汲極1 q 6表面之石夕化始化合物1 1 2。其次，請參閱第2D圖，利用如離子植入法或擴散方式 ’於複晶矽閘極1 0 2及源/汲極1 〇 6内植入矽離子1 1 4，石夕離子係之植入劑大抵為1至2 E 4 a t 〇 m / c m3，能量則大抵為 30 至50 Kev。 … 最後，請參閱第2E圖，實施一第二熱製程，如快速熱退火製程（RTP)，溫度約介於8 0 0 °C至9 0 0 °C之間施行3〇秒〜2分鐘。經由此熱退火步驟，在複晶矽閘極丨〇 2及源/汲極 106表面之第一石夕化始化合物（Co-Six)112可與充分之石夕反應成第二石夕化始化合物（C〇- S i2) 11 8，以降低阻值。其中’如第2 D圖所示’在本實施例之金屬碎化物製程中’由於係精植入砍離子以增加複晶碎閘極1 q 2及源/沒極 1 0 6内之矽離子濃度，然後再實施第二熱製程使第一石夕化始化合物（C〇- S ix)與充分之矽反應成第二矽化始化合物Therefore, the remaining cobalt metal layer 1 0 that does not react with silicon is removed from the surface of the insulating spacer layer 104 and left on the surface of the polycrystalline silicon gate electrode 102 and the source / drain 1 q 6 surface. Actor compound 1 1 2. Secondly, please refer to FIG. 2D, using, for example, an ion implantation method or a diffusion method to implant silicon ions 1 1 4 into the complex crystal gate 102 and source / drain 1 06. The input agent is probably 1 to 2 E 4 at 0 m / c m3, and the energy is probably 30 to 50 Kev. … Finally, referring to Figure 2E, a second thermal process, such as a rapid thermal annealing process (RTP), is performed at a temperature between 800 ° C and 900 ° C for 30 seconds to 2 minutes. After this thermal annealing step, the first co-Six 112 (Co-Six) 112 on the surface of the polycrystalline silicon gate and the source / drain 106 can react with the full co-Six to form the second co-Six Compound (Co-S i2) 11 8 to reduce resistance. Among them, 'as shown in FIG. 2D', in the metal fragmentation process of this embodiment, because the system is implanted with chopping ions to increase the silicon ions in the multi-crystal fragment gate 1 q 2 and the source / mirror 106. Concentration, and then a second thermal process is performed to make the first siliconization compound (Co-Six) react with sufficient silicon to form a second siliconization compound

0503-6982TW ； TSMC2001-0926 ； ycchen.ptd 第 9 頁 W1795 五、發明說明（7) -----—__ (C〇~~Si Λ 1 1 〇 . 2 8 ’因此可有效防止金屬石夕化物之皺摺現象八 ^，避免製程缺陷。兔實施例2 首先依弟2 A至2 B圖，進行同前一實施例之各項制步驟與料，且同一標號為具有相同功能之元件各員“ 、：、久’晴參閱第3圖，利用如離子植入法或擴散方气於複晶石夕閘極1 〇 2及源/汲極1 〇 6内植入矽離子1 2 〇，功t 承之植入劑量大抵為1至2E4 atom/cm3，能量則大把 30 至50 KeV 。馬叙接著’同第2 C圖’除去在絕緣間隔層1 〇 4表面剩餘未 >、石夕^應之始金屬層，舉例而言，可利用選擇性蝕刻，例 =連續兩道濕蝕刻製程，其中第一道蝕刻製程係以氨水和 #氧水之此合液為餘刻劑，第二道触刻製程則以硫酸和雙氧水之混合液為蝕刻劑。前述濕蝕刻製程可以溶解剩餘未反應之始金屬層，但不會溶蝕矽化鈷化合物丨丨2，因此，在絕緣間隔層1 04表面剩餘未與矽反應之鈷金屬層丨〇8被去除，而留下在複晶矽閘極1〇2及源/汲極1〇6表面之矽化化合物11 2。 ^最後，同第2 E圖，實施一第二熱製程，如快速熱退火製程（^?)，溫度約介於80 0。0至90 0。(：之間。經由此熱退火步驟，在複晶矽閘極102及源/汲極106表面之第一矽化鈷化合物（Co-Six)l 10可與充分之矽反應成第二矽化鈷化合物（Co-Si2) 118，以降低阻值。同實施例1之說明，如第3圖所示，在本實施例之金屬0503-6982TW; TSMC2001-0926; ycchen.ptd Page 9 W1795 V. Description of the invention (7) -----—__ (C〇 ~~ Si Λ 1 1 〇 2 8 The wrinkling phenomenon of the compound is avoided to avoid manufacturing process defects. Rabbit Example 2 First, according to the drawings of 2A to 2B, the steps and materials of the previous embodiment are performed, and the same reference numerals are used for components with the same function. "" ::, Jiu 'Qing refer to Figure 3, using such methods as ion implantation or diffusion method to implant silicon ions 12 and 2 at the source / drain electrode 106. The implantation dose of work is probably 1 to 2E4 atom / cm3, and the energy is 30 to 50 KeV. Ma Xu then 'same as in Fig. 2 C' to remove the remaining remaining on the surface of the insulating spacer 104 and the stone In the beginning, the metal layer can be selectively etched, for example, two consecutive wet etch processes. The first etch process uses the combined solution of ammonia and #oxy water as the remaining etchant. The two touch-etching processes use a mixed solution of sulfuric acid and hydrogen peroxide as an etchant. The aforementioned wet etching process can dissolve the remaining unreacted starting metal layer, However, it does not dissolve the cobalt silicide compound. Therefore, the remaining cobalt metal layer that does not react with silicon on the surface of the insulating spacer layer 104 is removed, leaving behind the complex silicon gate electrode 102 and the source / The silicide compound 11 on the surface of the drain electrode 106. ^ Finally, as shown in Figure 2E, a second thermal process, such as a rapid thermal annealing process (^?), Is performed, and the temperature is about 80. 0 to 900. (: Between. After this thermal annealing step, the first cobalt silicide compound (Co-Six) l10 on the surface of the polycrystalline silicon gate 102 and the source / drain 106 can react with sufficient silicon to form a second cobalt silicide compound. (Co-Si2) 118 in order to reduce the resistance value. As explained in the first embodiment, as shown in FIG. 3, the metal in this embodiment

531795 五、發明說明（8) 物製私中，由於係藉植入石夕離子以增加複晶石夕閘極 ^ #及^源/汲極1 〇 6内之矽離子濃度，然後再實施第二熱製 =#第一矽化鈷化合物（C〇 —Six)與充分之矽反應成第二矽 if參^合物（C〇-Si2)，因此可有效防止金屬矽化物之皺摺現象發生，避免製程缺陷。雖然本發明已以數個較佳實施例揭露如上，麸豆f # 明；：：此技藝者，在不脫離;發= 保護範圍::後:者::本發明之531795 V. Description of the invention (8) In the production of private goods, because of the implantation of Shi Xi ions to increase the polysilicon Xi gate ^ # and ^ source / drain electrode 106 silicon concentration, and then implement the first Two thermal system = #First cobalt silicide compound (Co-Six) reacts with sufficient silicon to form a second silicon compound (Co-Si2), so it can effectively prevent the occurrence of wrinkling of metal silicide, Avoid process defects. Although the present invention has been disclosed as above with several preferred embodiments, the bran bean f # is clear :: This artist does not leave; hair = protection scope :: later: the :: of the present invention

Claims

531795 六、申請專利範圍 1 · 一種使用矽化鈷之自行對準金屬矽化物製程，適用於一半導體基底，包括下列步驟：於該半導體基底上形成一由閘極絕緣層、閘極導電層和閘極間隔層組成之閘極結構；曰於該閘極結構兩側之該半導體基底形成一源/汲極區； •於該源/汲極表面和該閘極結構表面上形成一鈷金屬層，，施仃一第一熱製程以在該閘極導電層及該源/汲極面形成第一矽化鈷（C〇 —3丨2)化合物；去除未反應成該第一矽化鈷化合物之其他鈷金屬層；閘極導電層及該源/汲極内植入矽離子；以及曰，第施仃第一熱製程使第一矽化鈷化合物（Co-Six)反應成石夕化錄化合物（Co-S i2)。、準金2屬利範圍第1項所述之使用石夕化始之自行對積法或化學氣相沉積法所形成。札相'儿 _ 準令3凰::卜專利範圍第1項所述之使用矽化鈷之自行對丄金埃屬简製程’其中上述钻金屬層之厚度為為= 準金4屬範【：1項所述之使用彻之自行對為400〜60(KC，上过既二;^述第一熱製程之施行溫度範圍 ,,, 返既疋&行時間為3 0秒〜2分鐘。 • 明專利範圍第1項所述之使用矽化鈷之自行對531795 6. Scope of patent application 1. A self-aligned metal silicide process using cobalt silicide, suitable for a semiconductor substrate, including the following steps: forming a gate insulating layer, a gate conductive layer and a gate on the semiconductor substrate A gate structure composed of a gate spacer layer; said semiconductor substrate on both sides of the gate structure forms a source / drain region; • a cobalt metal layer is formed on the source / drain surface and the gate structure surface, A first thermal process is performed to form a first cobalt silicide (Co-3—2) compound on the gate conductive layer and the source / drain surface; and remove other cobalt that has not reacted to the first cobalt silicide compound. A metal layer; a gate conductive layer and silicon ions implanted in the source / drain; and said, the first thermal process is to react the first cobalt silicide compound (Co-Six) to a chemical compound (Co-Six) S i2). 2. Zhunjin 2 is formed by using the self-convolution method or chemical vapor deposition method started by Shi Xihua as described in item 1 of the profit scope. Zha Xiang'er_ Zhunling Order 3 :: The self-alignment process using cobalt silicide as described in item 1 of the patent scope is a simple process of arranging gold and stellite, where the thickness of the above-mentioned drilled metal layer is = quasi-gold 4 genus [: The use of the self-pairing described in item 1 is 400 ~ 60 (KC, after the previous two; ^ The operating temperature range of the first thermal process, and the return time is 30 seconds ~ 2 minutes. • Self-alignment using cobalt silicide as described in item 1 of the patent

531795 六、申請專利範圍準金屬矽化物製程，其中上述第二熱製程之施行溫度範圍為8 0 0〜9 0 0 °C，上述既定施行時間為3 〇秒〜2分鐘。 6 ·如申請專利範圍第1項所述之使用石夕化錄之自行對準金屬矽化物製程，其中上述去除未反應鈷金屬層之步驟係利用氨水和雙氧水之混合液來進行。 7 ·如申請專利範圍第1項所述之使用矽化鈷之自行對準金屬石夕化物製程，其中上述去除未反應鈷金屬層之步驟係利用硫酸和雙氧水之混合液來進行。、8·如申請專利範圍第1項所述之使用矽化鈷之自行對準金屬石夕化物製程，更包括，於形成該鈷金屬層之後，再形成一覆蓋層以覆蓋該麵金屬層。 9 · 一種使用石夕化姑之自行對準金屬矽化物製程，適用於一半導體基底，包括下列步驟：於該半導體基底上形成一由閘極絕緣層、閘極導電層和閘極間隔層組成之閘極結構；於該閘極結構兩側之該半導體基底形成一源/汲極區；於該源/汲極表面和該閘極結構表面上形成一鈷金層； i /施仃一第一熱製程以在該閘極導電層及該源/汲極表面形成第一石夕化始（Co-S i2 )化合物；於該閘極導電層及該源/汲極内植入矽離子；去除未反應成該第一矽化鈷化合物之其他鈷金以及 ^曰，531795 6. Scope of patent application For the metalloid silicide process, the temperature range of the above-mentioned second thermal process is 800 ~ 900 ° C, and the above-mentioned predetermined execution time is 30 seconds ~ 2 minutes. 6 · The self-aligning metal silicide process using Shixi Hualu as described in item 1 of the scope of the patent application, wherein the step of removing the unreacted cobalt metal layer is performed by using a mixture of ammonia and hydrogen peroxide. 7. The self-aligning metal fossilization process using cobalt silicide as described in item 1 of the scope of the patent application, wherein the step of removing the unreacted cobalt metal layer is performed using a mixed solution of sulfuric acid and hydrogen peroxide. 8. The self-aligning metal fossilization process using cobalt silicide as described in item 1 of the scope of the patent application, further comprising, after forming the cobalt metal layer, forming a cover layer to cover the surface metal layer. 9 · A self-aligned metal silicide process using Shi Xihua is suitable for a semiconductor substrate, and includes the following steps: forming a gate insulating layer, a gate conductive layer and a gate spacer layer on the semiconductor substrate; A gate structure; forming a source / drain region on the semiconductor substrate on both sides of the gate structure; forming a cobalt-gold layer on the source / drain surface and the gate structure surface; i / 施一第A thermal process to form a first co-S i2 compound on the gate conductive layer and the source / drain surface; implant silicon ions into the gate conductive layer and the source / drain; Removing other cobalt gold that has not reacted into the first cobalt silicide compound and

0503-6982TW ； TSMC2001-0926 * ycchen.ptd 第13頁六、申請專利範圍知 <亍第二哉制第二彻化：ί(=2;:夕化钻化合物(co〜準金1屬0 ·石夕如化申^專圍中第9項所述之使用石夕化敍之自行對積法或化學氣相；積;二；钻金屬層係利用物理氣相- 準八1遥1.々如申請專利範圍第9項所述之使用石夕化録之自杆料二屬梦化物製程’其中上述鈷金屬層之厚度為為5自〇:對準金1屬2·石夕如化t專㈣圍第9項所述之使用石夕化銘之自行對其中上述第一熱製程之施行溫度範圍、、 0 C ’上述既定施行時間為3 0秒〜2分鐘。；1 3·如申請專利範圍第9項所述之使用矽化鈷之自行對準金屬矽化物製程，其中上述第二熱製程之施行溫度範圍為80 0〜90 0 °c，上述既定施行時間為3〇秒〜2分鐘。 1 4·如申請專利範圍第9項所述之使用矽化鈷之自行對準金屬石夕化物製程，其中上述去除未反應鈷金屬層之步驟係利用氨水和雙氧水之混合液來進行。 1 5 ·如申請專利範圍第9項所述之使用矽化鈷之自行對準金屬砍化物製程，其中上述去除未反應鈷金屬層之步驟係利用硫酸和雙氧水之混合液來進行。 1 6 ·如申請專利範圍第9項所述之使用矽化鈷之自行對準金屬矽化物製程，更包括，於形成該鈷金屬層之後，再形成一覆蓋層以覆蓋該鈷金屬層。0503-6982TW; TSMC2001-0926 * ycchen.ptd Page 13 VI. Knowing the scope of patent application < Second implementation of the second system: ((= 2 ;: Xihua diamond compound (co ~ quasi gold 1 belongs to 0 · Shi Xi as described in item 9 of the application for the use of Shi Xihua's self-advection method or chemical vapor phase; product; two; drilling metal layer system using physical vapor phase-Zhunba 1 Yao 1. 々As described in item 9 of the scope of the patent application, the use of Shi Xihua's self-bar material is a dream material process' where the thickness of the above cobalt metal layer is 5 to 0: aligning gold 1 belongs to 2. Shi Xiruhua The temperature range in which the first thermal process is performed by Shi Xihuaming, which is described in item 9 of the Zhuanzhuo Wai, is 0 ° C. The above-mentioned predetermined execution time is 30 seconds to 2 minutes. 1 3 · 如The self-aligned metal silicide process using cobalt silicide as described in item 9 of the scope of the patent application, wherein the execution temperature range of the second thermal process is 80 0 to 90 0 ° C, and the above-mentioned predetermined execution time is 30 seconds to 2 1 4 · The self-aligning metal lithoxide process using cobalt silicide as described in item 9 of the scope of patent application, wherein the above removal The step of reacting the cobalt metal layer is performed by using a mixed solution of ammonia and hydrogen peroxide. 1 5 · The self-aligned metal cutting process using cobalt silicide as described in item 9 of the patent application scope, wherein the above-mentioned removal of the unreacted cobalt metal layer The steps are performed by using a mixed solution of sulfuric acid and hydrogen peroxide. 1 6 · The self-aligned metal silicide process using cobalt silicide as described in item 9 of the scope of patent application, further comprising, after forming the cobalt metal layer, A cover layer is formed to cover the cobalt metal layer.

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