TW550819B - Thin-film semiconductor device - Google Patents
Thin-film semiconductor device Download PDFInfo
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- TW550819B TW550819B TW090118806A TW90118806A TW550819B TW 550819 B TW550819 B TW 550819B TW 090118806 A TW090118806 A TW 090118806A TW 90118806 A TW90118806 A TW 90118806A TW 550819 B TW550819 B TW 550819B
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- thin film
- film transistor
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- 239000010409 thin film Substances 0.000 title claims abstract description 194
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000010408 film Substances 0.000 claims abstract description 68
- 230000002093 peripheral effect Effects 0.000 claims abstract description 23
- 239000004973 liquid crystal related substance Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims 1
- 230000007704 transition Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 101100041125 Arabidopsis thaliana RST1 gene Proteins 0.000 description 3
- 101100443250 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG1 gene Proteins 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000009751 slip forming Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 101100443251 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG2 gene Proteins 0.000 description 2
- 101100041128 Schizosaccharomyces pombe (strain 972 / ATCC 24843) rst2 gene Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
550819 A7 B7 五、發明説明(丨 ) 發明背景 本發明有關一種由薄膜電晶體整合而成之薄膜半導體, 而且尤其有關一種薄膜半導體,包括一像素行列區段及一 配置在其四週之週邊電路區段,用以作為活性矩陣型液晶 顯示器單元之驅動基材。 活性矩— 陣型液晶顯示器單元通常以薄膜電晶體為開關元 件。薄膜電晶體中,作為主動層之半導體薄膜通常以多晶 矽構成,多晶矽半導體薄膜不僅作為開關元件亦作為電路 元件,開關元件結合電路元件即在一基材上形成週邊驅動 電路。而且,多晶矽半導體薄膜可以極小體積構成,因此 每一開關元件只在每一像素上佔據極小區域,而使得像素 有一大的隙缝比。活性矩陣型液晶顯示器單元尺寸很小卻 擁有高解析顯示,適用於攝錄機,數位相機及可攜式電話 終端機之螢幕。 不幸地,傳統多晶矽半導體薄膜需要一較高的驅動電 壓,大約9 - 1 5伏特,導致液晶顯示器功率消耗增加,以省 電立場考量,並不適用於手提電話及其他手提裝置。如果 要求活性矩陣型液晶顯示器能以低功率消粍方式運作,多 晶矽半導體薄膜即需以低驅動電壓方式運作。 * 另一方S,多晶矽半導體薄膜也有另一不便,即它們在 玻璃基#上形成時,藉著所謂低溫處理經過一大約為600°C -700 °C之焱璃轉換點。不便之處即由於熱載子而有低崩潰 電壓,尤其在η -通道形式之電晶體例子。避免熱載子造成 惡化方法之一,係在薄膜電晶體汲極末端形成一 LDD區(即 -4 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 550819 A7 B7 五、發明説明(2 ) 輕度摻雜汲極),LDD區在汲極末端減緩電場濃度,不過, 在汲極末端形成LDD區不可避免地會降低薄膜電晶體之導 通電流,這令人難以理解在低驅動電壓下以大電流運作之 薄膜電晶體能藉此節省功率消耗。 在日本專利公告號45930/1997中已揭示一種新薄膜電晶 體,其建— 構能同時符合避免熱載子引起之惡化與增加導通 電流之雙重要求。新揭示結構之特徵為其部分LDD區與部 分電極重疊,不過,其中並無揭示LDD區之相關位置及閘 極電極如何影響薄膜電晶體之操作特性。 一種活性矩陣型液晶顯示器,其中一基材上形成像素行 列區段及週邊電路區段,週邊驅動電路之薄膜電晶體通常 需要具有一高導通電流,同時也要求在像素行列區段形成 之薄膜電晶體具有一低洩漏電流(截止電流),用以切換像 素電極。電路薄膜電晶體與像素薄膜電晶體所需之特性自 然各不相同,應付這情況之技術已在日本專利公告號 88972/1994,189998/1998及 W098/13911中揭示,不過,從實用觀 點看,這些並不能滿足需求。 發明總結 在前述觀點中,本發明係達成改進積體薄膜電晶體之結 構,以用在如活性矩陣型液晶顯示器之薄膜半導體裝置 中,本#明之目的係提供一種薄膜半導體裝置,適用於低 功率消耗~之高品質影像顯示。薄膜半導體裝置包括以低驅 動電壓運作之電路薄膜電晶體及以小洩漏電流運作之像素 薄膜電晶體,兩種形態之薄膜電晶體皆在同一基材上整 _^_ 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 550819 A7
合。本發明指出一種薄膜半導體裝置,具有—像素行列區 段及-配置在其四週之週邊電路區段,該像素行列:段包 括像素電極及用以切換像素電極之像素薄膜電晶體,該週 邊:路區段包括多個驅動電路,每一驅動電路包括多個電 路薄胰電晶體用以驅動像素薄膜電晶體。該每—薄膜而曰 體均具料片結構,包括—半導料膜,1極電極二 閘絕緣薄膜插人㈣之間,而該半導料膜在閘極電極末 端内側有-通道區’該通道區外侧係輕度掺雜區,在該輕 度掺雜區外射重度轉區,而—濃度邊界將輕度捧雜區 及重度摻雜區分開,其中從該閘極電極末端測量之該濃度 邊界,其位置在該電路薄膜電晶體中較在像素薄膜電晶體 中更近内側。 根據一較佳實例,電路薄膜電晶體之濃度邊界位於閘極 電極末端内側,而像素薄膜電晶體之濃度邊界位於閘極電 極末端外側’·或電路薄膜電晶體之濃度邊界距閘極電極末 端内側位置與第一距離相等,而像素薄膜電晶體之濃度邊 界距閘極電極末端外側位置與第二距離相等,其中第一距 離短於第二距離。 根據另一較佳實例,電路薄膜電晶體在汲極側有一輕度 摻雜區但源極側則無。更佳地,每一薄膜電晶體皆具有2 問形態之薄片結構,其中半導體薄膜位於閘極電極上,兩 者之間並***一閘絕緣薄膜。 本發明具有以下特點:該濃度邊界由該閘極電極末端測 起其位置在该電路薄膜電晶體中較在像素薄膜電晶體中 550819 A7
更近内側。濃度邊界將輕度摻雜區(11)1)區)及重度摻雜區 (汲極區及源極區)分開,本發明發現,當其由閘極電極向 内ί、彳和動時會增加導通電流,而由閘極電極向外側移動時 會減少洩漏電流。調整濃度邊界相關閘極電極末端之位置 使得電路薄膜電晶體及像素薄膜電晶體之操作特性發揮最 大效用。結果在像素行列區段不失去影像品質之下,減少 週邊電路區段的功率消耗。 附圖簡單說明 圖1係一部分剖面圖,根據本發明說明薄膜半導體裝置 弟一實例。 圖2係一部分剖面圖,說明第二實例。 圖3係一部分剖面圖,說明第三實例。 圖4係一示意圖,說明ldd結構之一例。 圖5係一示意圖,說明LDE)結構之另一例。 圖6係一示意圖,說明LDD結構之其他例子。 圖7係一曲線圖,說明薄膜電晶體之汲極電流/閘極電壓 特性’此薄膜電晶體具有圖4至圖6之LDD結構。 圖8 Α至圖8 Η係根據本發明以圖表說明生產薄膜半導體 裝置之步驟。 圖9係一部分剖面圖,說明第四實例。 圖1 0係:一示意立體圖,說明根據本發明液晶顯示器單元 之一例。 較佳實例說明 將以相關附圖在以下詳細說明本發明之實例,圖i係一 550819 A7 B7
五、發明説明 示意部分剖面圖,說明有關本發明薄膜半導體裝置之第一 實例。涊半導體裝置包括一像素行列區段及一配置在其四 週之週邊電路區段,該像素㈣區段包括一像素電極Η及 一用以切換像素之薄膜電晶體(TFT_pxL)。此實例中,該 TFT-PXL具有雙閘形式之底閘結構並屬於卜通道形式,另二 方面,週H:電路區段包括一驅動電路,用以組成電路薄膜 電晶體(TFT-CKT),該驅動電路用以驅動像素薄膜電晶體 TFT-PXL。圖1說明只有一 n_通道形式之TFT-CKT,其具有單 閘形式之底閘結構,每一薄膜電晶體TFT_pxL& tft_ckt均 具有薄片結構,包括一半導體薄膜5及一閘極電極丨,兩者 之間並***一閘絕緣薄膜(2,3)。半導體薄膜5由多晶矽所 形成,孩閘絕緣薄膜具有薄片結構,包括一閘氮化物薄膜 2及一氧化物薄膜3。附帶地,這些薄膜電晶體TFT_pxL& TFT-CKT係在一絕緣基材〇 (如破璃)上藉整合而形成。 半導體薄膜5與每一薄膜電晶體之元件區有一致性印刷 圖案,已印刷圖案之半導體薄膜5有一位於閘極電極丨末端 (E)内側足通道區(ch),輕度摻雜區(LDE^)由通道區 向外側延伸,而重度摻雜區(源極區3及汲極區〇)由1^〇區 向外側延伸,而一濃度邊將輕度摻雜區及重度摻雜區 刀開。另外,母一薄膜電晶體之通道區(ch)均由一阻片薄 膜6所保護。薄膜電晶體TFlvpxL& TFT_CKT如前述方式建 構,由一内層緣絕薄膜7及一保護薄膜8所覆蓋,保護薄膜 8上形成一接線電極9 ,每一接線電極9係藉一接觸孔以電 極連接至每一薄膜電晶體之源極區s及汲極區D ,該接觸
550819 A7 ______B7 五、發明説明(6 ) 孔開口在内層緣絕薄膜7及保護薄膜8中。接線電極9由一 平面薄膜1 0所覆蓋,一像素電極1 1以前述一致之圖案在平 面薄膜1 0上形成。 本發明之特徵係電路薄膜電晶體TFT-CKT不同於像素薄膜 電晶體TFT-PXL,其中濃度邊界B從閘極電極末端E測得位 置X較深入前者而非後者。換言之,薄膜電晶體以此方式 整合形成,達成XI,X2<X3,X4,X5,X6之關係。圖 1中,左邊之薄膜電晶體代表週邊電路區段n_通道丁FT-CKT,而右邊之薄膜電晶體代表像素多閘形TFT-PXL,其中 兩個閘極電極1具有相同電位。圖1中,圖中未示之週邊電 路區段p -通道TFT-CKT,在每一薄膜電晶體中,閘極電極末 端E至濃度邊界B (參照LDD末端)之距離由XI,χ2,X3 , X4,X5,X6代表,從左至右在圖丄中標出。又丨及又二各 自指出TFT-CKT中閘末端E與LDD末端B之距離,而χ3至X6 各自指出TFT-PXL中閘末端E與LDD末端B之距離。TFT-CKT 需要一高導通電流,但TFT-PXL卻需要一低洩漏電流,當達 成0 < XI,X2 < X3,X4,X5,Χό之關係時,這些要求 就能滿足’其中距離係由閘末端Ε測起,往閘極電極1内側 及外側之距離分別以負數及正數表示。 圖2係一示意部分剖面圖,說明相關本發明之薄膜半導 體裝置第二實例,圖1中之數字用在圖2之對應零件。本實 例特徵係用於電路之薄膜電晶體TFT_CKT在閘極電極i末端 E内側有;辰度邊界B,而用於像素之薄膜電晶體丁ρτ-pxj^在 每一閘極電極1末端E外側有濃度邊界b,換言之,存在 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱) 550819 A7 B7 五、發明説明(7 ) XI,X2 < 〇 < X3,X4,X5,X6之關係。此關係不同於 第一實例提及之關係,即TFT-CKT之LDD末端自閘極電極末 端以第一距離更靠外側,而TFT-PXL之LDD末端自閘極電極 末端以第二距離更靠外側,換言之,在TFT-CKT及TFT-PXL 兩者之LDD末端皆在閘極電極末端外側,而第一距離比第 二距離短、 圖3係一示意部分剖面圖,說明與本發明有關之薄膜半 導體裝置第三實例,圖1,2中之相關數字用在圖3中說明 相同零件。本實例特徵係TFT-CKT在汲極側有一輕度摻雜區 (LDD區),但在源極側則無輕度掺雜區(LDD區),不對稱結 構之TFT-CKT可用於導通電流一直以固定方向流動之那部分 電路,換言之,當沒極固定時LDD區會減緩場濃度’而缺 少LDD區會從源極區得到大量導通電流。在第三實例中, 也達成X2 < X3,X4,X5,X6之關係,因此TFT-CKT有一 高導通電流而TFT-PXL壓制一低洩漏電流。 以下參考圖4至圖7係本發明之理論性解釋,圖4至圖6說 明薄膜電晶體之LDD結構,圖7說明對等於圖4至圖6所示 之每一 LDD結構中薄膜電晶體之汲極電流/閘極電壓特 性。圖4至圖6中,距離X定義成X = (LDD末端B) — (閘末端 E),其中B及E兩者位置皆以閘末端E為相同原點(〇)測 起,朝閘~末端E外側測量之距離為正數,而朝閘末端E内 側測量之距離為負數。圖4之LDD結構,X> 0係因LDD區之 末端B沿著通道區(Ch)之縱向方向是在閘末端E外側,此 LDD結構具有如圖7中曲線” a ”所代表之汲極電流/閘極電 ___^_-10-___ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 550819 A7 B7 五、發明説明(8 ) 壓特性,當閘極電壓負數時,以下情形即發生:在閘極電 極與LDD區重疊部分,閘場會影響LDD區而產生一反轉層, 閘末端外側之LDD區因未受閘場影響而保持一高電阻,因 此閘末端仍保持低電場。因此,圖4之LDD結構以此方式展 現功能,使洩漏電流在它關閉區域夠低,且導通電流因高 LDD電阻而減少,因此圖4之LDD結構適用於像素薄膜電晶 體。 相對之下,圖6中之LDD結構,X < 0係因為LDD區之末端 B在閘末端E内側,此LDD結構具有如圖7所示之特性曲線 n c ”,因LDD區完全與閘極電極重疊,當閘極電壓是負數 時,整個LDD區構成一反轉層,結果,汲極末端線條呈大 彎度而在汲極末端之電場較濃。結果閘極偏電壓在負數方 向增加而洩漏電流因隧道電流而增加,另一方面,閘偏壓 為正數之飽和電流區由於調變形成一聚集層,結果在無 LDD電阻之下使導通電流增加。熱載子只發生在次門檻區 (相當於淺閘極偏壓區),因此,LDD在熱載子發生區很難 執行調變,因此LDD區可充分減緩汲極末端之電場,換言 之,圖6中之LDD結構在壓制熱載子發生時,能在飽和區增 加導通電流。因此,此LDD結構適用於週邊電路區段之薄 膜電晶體。 圖5說曰月另一 LDD結構,其中閘末端Ε與LDD末端Β —致, 因此X = 0。相關此LDD結構之薄膜電晶體具有汲極電流/ 閘極電壓特性(如圖7曲線’’ b ’’所示)。此結構中,飽和區電 流比圖4之結構增加更多,它與圖6所示結構相當相似,此 _- 11 __ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 550819 A7 B7 五、發明説明 結構之洩漏電流係圖4及圖6結構中之中間值。 參考圖8A至圖8H的根據本發明之製造薄膜半導體裝置 的方法貫例以具體解釋,此實例有關藉低溫方法在一玻璃 基材0上整合底閘形式之薄膜電晶體,附圖說明右半邊之 兩個像素多閘結構薄膜電晶體,及左半邊兩個電路薄膜電 曰9固係n -通道形式而另一個係ρ -通道形式。如圖 8 A所示’製程開始於在一絕緣基材0形成一 3 0至300 n m厚 度之高溶金屬薄膜(此類金屬如鉬,鈦,姮及鎢),金屬薄 膜經過圖案印刷而形成閘極電極1。 然後,如圖8B所示,藉由電漿CVD ,大氣CVD,減壓 CVD或類似物形成一 5 〇 n m厚度閘矽氮化物(別队)薄膜2, 在此薄膜上持續形成一大約1〇〇 n m厚度之閘氧化矽(Si〇2)薄 膜3 ’在此薄膜上持續形成一大約至go nm厚度之非晶 係矽化物半導體薄膜4。接下來之步驟,如在藉由電漿CVD 進行製程之例子’係在一氮氣或真空中於4〇〇它至45〇它溫 度下緩慢退火一小時,藉以從薄膜消除氫氣。此退火步驟 後,非晶系矽化物藉由準分子雷射退火(ELA)轉成多晶矽 準分子雷射退火主要在於以準分子雷射光束照射非晶形 矽,藉以在由熔化物的冷卻過程中將其轉換為多晶形矽。 之後,如圖8 C所示,形成一大約100至3〇〇 nm厚度之別〇2 薄膜,此薄膜藉背面側暴露經過圖案印刷而形成阻片薄膜 6,藉由對Si〇2薄膜應用一光阻完成圖案印刷,利用閘極電 極1作為光罩以光透過基材〇來暴露光阻薄膜,因此與閘極 黾極1 一致之圖案即在光阻薄膜上形成,利用在光阻薄膜 上开> 成之圖案作為光罩對下方之Si〇2進行触刻。以此方式 本紙張尺度適用中國國家標準(CNS) A4規格(⑽父297公复) 裝 綠 -12- 550819 A7 __ B7 五、發明説明(1Q ) 形成與閘極電極1成一直線之阻片薄膜6。 圖8 D所示之步驟,形成LDD區係利用阻片薄膜6作為光 罩進行比較光摻雜之含磷(P)離子植入,此離子植入在基 材0整個表面進行,因此,除了阻片薄膜6未覆蓋之部分, 半導體薄膜5變成輕度摻雜區’而阻片薄膜6覆蓋之部分仍 保持為通崔區(ch) ,LDD之離子植入在一加速電壓5至10 KeV及一 5xl012至1.5xl013/cm2放射劑量下進行。 圖8 E所示步驟,離子植入以形成一 η -通道薄膜電晶體 TFT係以以下方式進行:變成ρ -通道電路薄膜電晶體Pch-TFT-CKT之部分由電阻光罩RST1所覆蓋,而變成η-通道電路 薄膜電晶體Nch-TFT-CKT及η -通道像素薄膜電晶體Nch-TFT-PXL之部分由防蝕光罩RST2,RST3及RST4所覆蓋,重度摻雜 區含磷(P)離子植入透過防蝕光罩RST1至RST4來進行,以形 成η -通道薄膜電晶體Nch-TFT之源極區S及汲極區D。此實 例中,含磷離子植入多晶半導體薄膜5係在一加速電壓10 KeV及一 lxl015/cm2放射劑量下進行,如圖所示,LDD區終於 在那些由電阻光罩RST2,RST3及RST4所覆蓋之部分中形 成。此實例中,電阻光罩RST以此方式印刷圖案,導致Nch-TFT-CKT之LDD區在閘極電極1之内側形成,而N c h - TFT-PXL 之LDD區在閘極電極1之外側形成。如前所述,藉防蝕圖案 於電路薄膜電晶體與像素薄膜電晶體間形成源極及汲極 處’底間形式之薄膜電晶體即能輕易建立一最佳LDD長 度。 考 圖8 F所示之步驟,防蝕光罩RST1至RST4使用後即移除, 即在ρ -通道電路薄膜電晶體形成一新防蝕光罩RST5,此防 ---- -13-________ 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公着) 550819 A7 B7 五、發明説明(U ) 蝕光罩覆蓋Nch-TFT-CKT及Nch-TFT-PXL。多晶半導體薄膜5 以RST5為光罩,在一加速電壓10 KeV及一 lxl015/cm2放射劑量 下經過硼(B)離子植入,以此方式形成源極區S及汲極區 D。不像Nch-TFT-CKT,Pch-TFT-CKT並不由LDD區來提供,通 常,一 η·通道薄膜電晶體基本上需要LDD結構來減緩汲極 末端之電濃度,反而ρ -通道薄膜電晶體不用LDD區,不 用多說,ρ -通道薄膜電晶體當然可有LDD區。像素薄膜電 晶體TFT-PXL也可屬於ρ -通道形式以取代圖示之η -通道形 式,在此情況下,LDD區最好也在用於電路之薄膜電晶體 中是短的,而在用於像素之薄膜電晶體中為長的。 圖8 G所示之步驟,防蝕光罩RST5使用後即移除,而植入 半導體薄膜之摻雜藉ELA,RTA(快速熱退火)或鎔爐退火而 活化。半導體薄膜5經過蝕刻,形成每一薄膜電晶體之區 域,進行蝕刻係為消除氧化矽Si02構成阻片薄膜6時的無用 部分。在半導體薄膜5及阻片薄膜6上形成二氧化矽内層絕 緣薄膜7 (厚度100至200 nm),矽氮化物保護薄膜8(厚度100 至200 nm)持續形成,基材0在氮氣中以350°C至400°C溫度緩 慢退火二小時,在保護薄膜8中及内層絕緣薄膜7之氫氣因 此能進入半導體薄膜5。 圖8 Η所示之最後步驟,接觸孔在内層絕緣薄膜7及保護 薄膜8中作成,接線電極9藉鋁濺擊形成,藉塗佈壓克力有 -機樹脂或旋塗式玻璃形成一平面薄膜1 0。接觸孔在平面薄 膜1 0中,在接觸孔上形成一 ΙΤΟ或ΙΧΟ透明傳導薄膜,其最 終將持續印刷圖案而形成像素電極11。前述步驟之後,可 __UA-- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐) 裝 訂
550819 A7 B7 五、發明説明(12 ) 得到包括一 η-通道像素薄膜電晶體(Nch-TFT-PXL)及電路薄 膜電晶體(Nch-TFT-CKT及Pch-TFT-CKT)之薄膜半導體裝置。 圖9係一示意部分剖面圖,說明與本發明相關之薄膜半 導體裝置第四實例,圖1之數字用在圖9的對應零件。本實 例不屬底閘結構而係屬頂閘結構,它在一絕緣基材0上有 一下方氮—化物薄膜6a及一氧化物薄膜6b,一多晶矽半導體 薄膜5在氧化物薄膜6b上形成,其與各薄膜電晶體TFT區域 印刷一致之圖案,閘絕緣薄膜2 3覆蓋此區域,而閘極電極 1也在此處形成。此實例中,η-通道電路薄膜電晶體(Nch-TFT-CKT)也與η-通道像素薄膜電晶體(Nch-TFT-PXL)不同, 其中前者至LDD末端之距離X2比後者至LDD末端之距離X3 短,換言之,Χ2<Χ3,這表示電路薄膜電晶體中導通電流 增加而像素薄膜電晶體中洩漏電流減少。 圖1 0係一示意透視圖,說明一活性矩陣型液晶顯示器單 元之例,其由根據本發明之薄膜半導體裝置所驅動。液晶 顯示器單元具有面板結構,包括一對絕緣基材〇及102,而 一光學基材103在它們中間,該光學基材103係一液晶材 料。藉整合像素行列區段104及週邊電路區段形成較低層基 材0,週邊電路區段區分為垂直驅動電路105及平行驅動電 路106,像素行列區段104有閘接線109形成列而信號接線110 形成欄,像素電極1 1形成在兩接線之交叉點而一薄膜電晶 體TFT驅動像素電極1 1。薄膜電晶體TFT其閘極電極連接至 相同之閘接線109,其汲極區連接至相同之像素電極1 1, 其源極區連接至相同之信號接線110,其閘接線109連接至 — _ 1 _ 本紙張尺度遴用中國國家標準(CNS) A4規格(210 X 297公釐) 550819 A7 B7 五、發明説明(13 ) 垂直驅動電路105,而信號接線110連接至平行驅動電路 106。根據本發明之最佳LDD長度在切換像素電極1 1之薄膜 電晶體,及包括垂直驅動電路105及平行驅動電路106中之 薄膜電晶體均具有一重要地位。 如前所述,本發明使人易於了解週邊驅動電路之薄膜電 晶體維持=高導通電流,而像素薄膜電晶體維持低洩漏電 流,而且,本發明使在同一基材上整合可由低電壓驅動之 週邊電路區段薄膜電晶體及具有低洩漏電流之像素薄膜電 晶體成為可能。這種薄膜電晶體對具低功率消耗之高品質 液晶顯示器單元是有用的,換言之,本發明對液晶顯示器 單元節省能源是有貢獻的,本發明也對提供所謂系統顯示 器之高功能電路整合有極大貢獻。 _- - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
Claims (1)
- 550819 A8.一種溥膜半導體裝置,具有一 ’ 像素仃列區段及一配置其 四周之週邊電路區段,該像音 ,,. 素仃列區焱包括像素電極及 2像素電極之像素薄膜電晶體,該週邊電路區段包括 触動電路,各有電路薄膜電晶體用以驅動像素薄膜電晶 月豆’孩每一薄膜電晶體係薄 辱片結構,具有一半導體薄 嗅’—,極電極及一閘絕绫蒗瞪并 # 巴家潯膜插在其間,而該半導體 涛膜在閘極電極末端内側有一 ,,^ 逋迢£,在孩通遒區外側 有-輕度摻雜區,在該輕度摻雜區外财_重度換雜 區,而-濃度邊界將該輕度摻雜區及重度摻雜區彼此分 開’其中從該閘極電極末端測量之該濃度邊界,立位置 在該電路薄膜電晶體中較在像素薄膜電晶體中更近内 側。 2.如申請專利範圍p項之薄膜半導體裝置,其中電路薄 膜電晶體之濃度邊界位於閘極電極末端内側,而像素薄 膜電晶體之濃度邊界位於閘極電極末端外側。 3·如申請專利範圍第丨項之薄膜半導體裝置,其中,以第 距離短於第二距離之方式,與第一距離等距之閘極電 極末端内側形成電路薄膜電晶體之濃度邊界,而與第二 距離等距之閘極電極末端外側形成像素薄膜電晶體之濃 度邊界。 4.如申諝專利範圍第1項之薄膜半導體裝置,其中電路薄 膜電晶—體在汲極側有一輕度摻雜區,但在源極側則無。 5·如申請專利範圍第1項之薄膜半導體裝置,其中每一薄 膜電晶體具有底閘形式之薄片結構,其中半導體薄膜置 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公董) 一 " — --- 六、申請專利範圍 .於閘極電極上,兩者之間***一閘絕緣薄膜。 6· —種液晶顯示器單元,具有兩個基材,兩者之間以保持 預設空間方式銜接,而在該空間内保持一液晶材料,其 中一基材具有像素行列區段及配置其四周之週邊電路區 段,而另一基材具有電極面對該像素行列區段,該像素 行列區-及包括像素電極及切換像素電極之像素薄膜電晶 體,該週邊電路區段包括驅動電路,各有電路薄膜電晶 體用以驅動像素薄膜電晶體,其中該每一薄膜電晶體係 薄片結構,具有一半導體薄膜,一閘極電極及一閘絕緣 薄膜插在其間,而該半導體薄膜在閘極電極末端内側有 一通道區,在該通道區外側有一輕度摻雜區,在該輕度 摻雜區外側有一重度摻雜區,而一濃度邊界將該輕度摻 雜區及重度摻雜區彼此分開,其中從該閘極電極末端測 量之該濃度邊界,其位置在該電路薄膜電晶體中較在像 素薄膜電晶體中更近内側。 7. 如申'請專利範圍第6項之液晶顯示器單元,其中電路薄 膜電晶體之濃度邊界位於閘極電極末端内側,而像素薄 膜電晶體之濃度邊界位於閘極電極末端外側。 8. 如申請專利範圍第6項之液晶顯示器單元,其中,以第 一距離短於第二距離之方式,與第一距離等距之閘極電 極末卷内側形成電路薄膜電晶體之濃度邊界,而與第二 距離等~距之閘極電極末端外側形成像素薄膜電晶體之濃 度邊界。 9. 如申請專利範圍第6項之液晶顯示器單元,其中電路薄 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 550819 A8 B8 C8 D8 申請專利範圍 .膜電晶體在汲極側有一輕度摻雜區,但在源極側則無。 10.如申請專利範圍第6項之液晶顯示器單元,其中每一薄 膜笔曰9體具有底閘形式之薄片結構,其中半導體薄膜置 於閘極電極上,兩者之間***一閘絕緣薄膜。 H_ —種薄膜半導體裝置製造方法,該裝置具有像素行列區 段及配--置其四周之週邊電路區段,該像素行列區段包括 像素電極及切換像素電極之像素薄膜電晶體,而該週邊 電路區段包括驅動電路,各有電路薄膜電晶體用以驅動 像素薄膜電晶體,該方法包括藉由一半導體薄膜,一閘 極電極及一閘絕緣薄膜插在其間形成薄片以形成該薄膜 電晶體’形成該半導體薄膜之方式係在閘極電極末端内 側有-通道區,在該通道區外侧有_輕度掺雜區,在咳 輕度摻雜區外财-重度摻雜區,而—濃度邊界將該輕 f摻雜區及重度轉區彼此分開,其中從該閘極電極末 袖測量之該濃度邊界’其位置在該電路薄膜電晶體中較 在像素薄膜電晶體中更近内側。 π.如申請專㈣„ η項之薄膜半物裝置製造方法,並 中電路薄膜電晶體之濃度邊界在閘極電極末端内例形 成’而像素薄膜電晶體之濃度邊界在問極電極末端外側 形成。 13.如申請·專利範圍第丨丨項之薄膜半導體裝置製造方法,並 中’以弟-距離短於第二距離之方式,與第一距離等距 1極電極末端内側形成電路薄膜電晶體之濃 而與第二距科距之閘極電極末端相形成像=薄膜電 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 550819 A BCD 六、申請專利範圍 --- .晶體之濃度邊界。 认如:請專利範圍第μ之薄膜半導體裝置製造方法,其 电各薄膜笔曰曰體在;及極側形成一輕度掺雜區,但在源 極側則無。 一 … A如申凊專利範圍第1 1項之薄膜半導體裝置製造方法,其 中薄膜:電晶體以底閘形式形成,其中半導體薄膜置於鬧 極私極上,兩者之間***一閘絕緣薄膜。 A 一種液晶顯示器單元製造方法,該單元有兩個基材,兩 者又間以保持指定空間方式銜接,而在該空間内保持一 液印材料,其中一基材具有像素行列區段及配置其四周 ^週邊電路區段,而另一基材具有電極面對該像素行列 區蚁,涘像素行列區段包括像素電極及切換像素電極之 像素薄膜電晶體,該週邊電路區段包括驅動電路,各有 電路薄膜電晶體用以驅動像素薄膜電晶體,該方法包括 藉由一半導體薄膜,一閘極電極及一閘絕緣薄膜插在其 2形成薄片以形成該薄膜電晶體,該半導體薄膜在閘極 電極末端内側形成一通道區,在該通道區外側形成一輕 度摻雜區,在該輕度摻雜區外側形成一重度摻雜區,而 形成一濃度邊界以分開該輕度摻雜區及重度摻雜區,從 孩閘極電極末端測量之該濃度邊界,其在該電路薄膜電 晶體中-形成位置較在像素薄膜電晶體中更近内側。 17·如申請專利範圍第丨6項之液晶顯示器單元製造方法,其 中電路薄膜電晶體之濃度邊界在閘極電極末端内側形 成,而像素薄膜電晶體之濃度邊界在閘極電極末端外 -20- 550819 A8 B8 C8 D8 申請專利範圍 .形成。 18. 如申請專利範圍第1 6項之液晶顯示器單元製造方法,其 中,以第一距離短於第二距離之方式,與第一距離等距 之閘極電極末端内側形成電路薄膜電晶體之濃度邊界, 而與第二距離等距之閘極電極末端外側形成像素薄膜電 晶體之=濃度邊界。 19. 如申請專利範圍第1 6項之液晶顯示器單元製造方法,其 中電路薄膜電晶體在汲極側形成一輕度摻雜區,但在源 極側則無。 20·如申請專利範圍第1 6項之液晶顯示器單元製造方法,其 中薄膜電晶體以底閘形式形成,其中半導體薄膜置於閘 極電極上,兩者之間***一閘絕緣薄膜。 -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6680223B1 (en) * | 1997-09-23 | 2004-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
TW575777B (en) * | 2001-03-30 | 2004-02-11 | Sanyo Electric Co | Active matrix type display device |
TW508830B (en) * | 2001-08-28 | 2002-11-01 | Hannstar Display Corp | Thin film transistor structure having four procedures of mask processing and the manufacturing method |
JP4149168B2 (ja) * | 2001-11-09 | 2008-09-10 | 株式会社半導体エネルギー研究所 | 発光装置 |
US7592980B2 (en) | 2002-06-05 | 2009-09-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2004095671A (ja) * | 2002-07-10 | 2004-03-25 | Seiko Epson Corp | 薄膜トランジスタ、スイッチング回路、アクティブ素子基板、電気光学装置、電子機器、サーマルヘッド、液滴吐出ヘッド、印刷装置、薄膜トランジスタ駆動発光表示装置 |
KR100906633B1 (ko) * | 2003-01-08 | 2009-07-10 | 삼성전자주식회사 | 박막 트랜지스터 기판 |
KR100900404B1 (ko) * | 2003-12-22 | 2009-06-02 | 엘지디스플레이 주식회사 | 액정표시소자의 제조 방법 |
US20060068532A1 (en) * | 2004-09-28 | 2006-03-30 | Sharp Laboratories Of America, Inc. | Dual-gate thin-film transistor |
US7407843B2 (en) * | 2004-04-23 | 2008-08-05 | Sharp Laboratories Of America, Inc. | Four-transistor Schmitt trigger inverter |
US20060166415A1 (en) * | 2004-06-07 | 2006-07-27 | Sharp Laboratories Of America, Inc. | Two-transistor tri-state inverter |
US7532187B2 (en) * | 2004-09-28 | 2009-05-12 | Sharp Laboratories Of America, Inc. | Dual-gate transistor display |
KR100601370B1 (ko) * | 2004-04-28 | 2006-07-13 | 삼성에스디아이 주식회사 | 박막 트랜지스터 및 그를 이용한 유기 전계 발광 표시 장치 |
US7033870B1 (en) * | 2004-11-29 | 2006-04-25 | International Business Machines Corporation | Semiconductor transistors with reduced gate-source/drain capacitances |
EP1998375A3 (en) * | 2005-09-29 | 2012-01-18 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device having oxide semiconductor layer and manufacturing method |
JP4827499B2 (ja) * | 2005-11-16 | 2011-11-30 | キヤノン株式会社 | 電流駆動型装置及び表示装置 |
KR101343435B1 (ko) * | 2006-08-09 | 2013-12-20 | 삼성디스플레이 주식회사 | 어레이 기판의 제조방법 및 이에 의해 제조된 어레이 기판 |
TWI420670B (zh) * | 2008-10-30 | 2013-12-21 | Hitachi Displays Ltd | 顯示裝置 |
JP5323604B2 (ja) * | 2009-07-30 | 2013-10-23 | 株式会社ジャパンディスプレイ | 表示装置及びその製造方法 |
KR102462043B1 (ko) * | 2009-10-16 | 2022-11-03 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
KR20110090408A (ko) * | 2010-02-03 | 2011-08-10 | 삼성전자주식회사 | 박막 형성 방법, 표시판용 금속 배선 및 이를 포함하는 박막 트랜지스터 표시판 및 그 제조 방법 |
CN103165471A (zh) * | 2013-02-19 | 2013-06-19 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法和显示装置 |
JP6898211B2 (ja) * | 2017-11-27 | 2021-07-07 | 浜松ホトニクス株式会社 | 光計測方法、光計測装置、光計測プログラム、及び光計測プログラムを記録する記録媒体 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3066036B2 (ja) * | 1990-01-12 | 2000-07-17 | 株式会社日立製作所 | 半導体装置 |
JP2650543B2 (ja) * | 1991-11-25 | 1997-09-03 | カシオ計算機株式会社 | マトリクス回路駆動装置 |
US5266507A (en) * | 1992-05-18 | 1993-11-30 | Industrial Technology Research Institute | Method of fabricating an offset dual gate thin film field effect transistor |
US5576556A (en) * | 1993-08-20 | 1996-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film semiconductor device with gate metal oxide and sidewall spacer |
JP3587537B2 (ja) * | 1992-12-09 | 2004-11-10 | 株式会社半導体エネルギー研究所 | 半導体装置 |
KR100333153B1 (ko) * | 1993-09-07 | 2002-12-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체장치제작방법 |
JP3030368B2 (ja) * | 1993-10-01 | 2000-04-10 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
JPH07335904A (ja) * | 1994-06-14 | 1995-12-22 | Semiconductor Energy Lab Co Ltd | 薄膜半導体集積回路 |
JPH07135323A (ja) * | 1993-10-20 | 1995-05-23 | Semiconductor Energy Lab Co Ltd | 薄膜状半導体集積回路およびその作製方法 |
JP3153065B2 (ja) * | 1993-12-27 | 2001-04-03 | 株式会社半導体エネルギー研究所 | 半導体集積回路の電極の作製方法 |
JP3312083B2 (ja) * | 1994-06-13 | 2002-08-05 | 株式会社半導体エネルギー研究所 | 表示装置 |
US5789762A (en) * | 1994-09-14 | 1998-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor active matrix circuit |
US6300659B1 (en) * | 1994-09-30 | 2001-10-09 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistor and fabrication method for same |
US5548132A (en) * | 1994-10-24 | 1996-08-20 | Micron Technology, Inc. | Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions |
US6599790B1 (en) * | 1996-02-15 | 2003-07-29 | Semiconductor Energy Laboratory Co., Ltd | Laser-irradiation method and laser-irradiation device |
JP3499381B2 (ja) * | 1996-09-21 | 2004-02-23 | 株式会社半導体エネルギー研究所 | アクティブマトリクス型表示装置およびその作製方法 |
JPH1197705A (ja) * | 1997-09-23 | 1999-04-09 | Semiconductor Energy Lab Co Ltd | 半導体集積回路 |
US6201260B1 (en) * | 1997-09-25 | 2001-03-13 | Kabushiki Kaisha Toshiba | Thin film transistor and method of manufacturing the same |
GB9806609D0 (en) * | 1998-03-28 | 1998-05-27 | Philips Electronics Nv | Electronic devices comprising thin-film transistors |
US6346730B1 (en) * | 1999-04-06 | 2002-02-12 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device having a pixel TFT formed in a display region and a drive circuit formed in the periphery of the display region on the same substrate |
-
2000
- 2000-08-10 JP JP2000241984A patent/JP2002057339A/ja active Pending
-
2001
- 2001-08-01 TW TW090118806A patent/TW550819B/zh not_active IP Right Cessation
- 2001-08-03 US US09/921,532 patent/US6563136B2/en not_active Expired - Lifetime
- 2001-08-10 KR KR1020010048185A patent/KR100831881B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100831881B1 (ko) | 2008-05-23 |
US20020068372A1 (en) | 2002-06-06 |
US6563136B2 (en) | 2003-05-13 |
KR20020013762A (ko) | 2002-02-21 |
JP2002057339A (ja) | 2002-02-22 |
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