TW521390B

TW521390B - Method to produce interconnect with inhibited copper electromigration (EM)

Info

Publication number: TW521390B
Application number: TW91101773A
Authority: TW
Inventors: Chung-Liang Chang; Shau-Lin Shue
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-02-01
Filing date: 2002-02-01
Publication date: 2003-02-21

Abstract

A method for producing an interconnect with a inhibited copper EM comprises: forming a dielectric layer having a via on a substrate; forming a copper seed layer on the inner surface of the via as a plating substrate; in an environment containing a PdSn catalyst or in an environment sequentially containing a SnCl2 catalyst and a PdCl2 catalyst, performing an electroless deposition to form a Sn-containing copper interconnect to inhibit the copper EM; and performing an annealing treatment on the interconnect to diffuse Sn atoms to the surface of the interconnect and inhibit the diffusion of copper atoms to the dielectric layer, in which the annealing temperature is 250 to 450 DEG C.

Description

發明說明（1) 發明領域：，發明係有關於—種内連線方法， -種抑制銅電遷移之内特別疋有關於銅原子電遷移及擴鸯s Ϊ線製曰t抑制内連線中的相關技術說明： 1運線之口口質。在極大型積體電路（ULSI )中，金屬化、鱼1 1Zatl〇n )為一重要步驟，其中内連線扮演電性 “路中各個元件的角色，因此其深深影響元件之電特，内連線材料。然而’銅金屬擴散係數高，Description of the invention (1) Field of the invention: The invention relates to-a method of interconnecting,-a method of suppressing the electromigration of copper, especially about the migration and expansion of copper atoms. Related technical descriptions: 1 The mouth quality of the transport line. In the ultra-large integrated circuit (ULSI), metallization and fish (11Zat10n) is an important step, in which the interconnects play the role of electrical "elements in the road, so it deeply affects the electrical characteristics of the components, Interconnect material. However, 'copper metal has a high diffusion coefficient,

=石夕，觸後會快速擴散進人基材而造成元件電性之不I 衫s 。另一方面，隨著内連線尺寸縮小化，題也日趨嚴重。电运秒Γ生的問二在習知技術之銅内連線製造方法中，會在形成内前形成擴散阻障層以防止銅原子擴散。另外，台灣專、、公告編號第4 2 6 9 6 4號揭示一種銅合金内連線掣造方法 ^ 由在純銅的上、下表面形成鄰接的銅合金層，再施以艮藉 j:’以形成銅合金内連線’然』，上述方法仍】法U 電遷移的問題。 $ 另一習知做法係利用錫銅合金作為靶射，以物理氣相沉積法（physical vapor deposition，PVD)來製造之内連線。為了進一步說明，以下參照第1&到1(1圖說= 習知技術形成含錫或鎂合金之銅内連線製程厂立口」思圖〇= Shi Xi, after contact, it will quickly diffuse into the human substrate and cause the electrical conductivity of the component. On the other hand, as the size of interconnects has become smaller, the problem has become more serious. Questions about the electrical transport time ② In the conventional copper interconnect manufacturing method, a diffusion barrier layer is formed to prevent the diffusion of copper atoms before forming the inner. In addition, Taiwan Special Publication No. 4 2 6 9 6 4 discloses a method for manufacturing copper alloy interconnects. ^ The adjacent copper alloy layers are formed on the upper and lower surfaces of pure copper, and then j: ' In order to form copper alloy interconnects, the above method still has the problem of electromigration. $ Another known practice is to use tin-copper alloys as target shots and use physical vapor deposition (PVD) to make interconnects. In order to further explain, the following references 1 & to 1 (1 picture said = conventional technology to form a copper or tin alloy containing tin or magnesium alloy process plant stand "

521390 五、發明說明（2) 首先，請參照第1 a圖，在一形成有電路（未繪示）之基板1 0 0上形成一介電層1 〇 2。接著，藉由微影蝕刻技術在介電層102上形成一介層洞i〇2a。接下來，請參照第1 b圖，在介電層介電層1 〇 2上及介層洞1 0 2 a内順應性形成一銅合金層丨〇 6，例如錫銅合金或鎮銅合金。％接下來’請參照第1 c圖，以習知之p v D製程在銅合金層106上全面性形成銅金屬層1〇8。由於現今半導體製程線寬日趨縮小化，例如〇 · 1微米（# m )以下，介層洞丨〇 2a的高寬比（aspect ratio)增高，因此藉由pvd製程來將銅金屬層108填入介層洞l〇2a容易因突出（overhang )而形成孔洞，如圖所示。最後’請參照第1 d圖，藉由習知化學機械研磨 (chemical mechanic polishing，CMP)製程去除介電層 102上的銅金屬層108及銅合金層1〇6並在介層洞内1〇2&留胃下銅金屬層108及銅合金層106以作為内連線。雖然此内連線中錫原子因位於銅的晶界（grain boundary)而可有效抑制銅電遷移的發生，然而由於内連線中形成有孔洞，如圖所示’因此導致内連線品質不佳而引發其他電性問題。有鑑於此，本發明提供一種抑制銅電遷移之内連線製造方法，其藉由無電鍍沉積法取代物理化學汽相沉積（pVD ) 法來製造内連線’期間並使用含鈀錫觸媒來進行活化處理。接著，再施加一退火處理，使錫原子擴散至銅内連線之表面而具有緻密無孔洞、抑制電遷移及阻障擴散之優點，521390 V. Description of the invention (2) First, referring to FIG. 1a, a dielectric layer 102 is formed on a substrate 100 on which a circuit (not shown) is formed. Next, a via hole 102a is formed in the dielectric layer 102 by a lithography etching technique. Next, referring to FIG. 1b, a copper alloy layer, such as a tin-copper alloy or a copper-copper alloy, is conformably formed on the dielectric layer 102 and the dielectric hole 10a. % Next 'Please refer to FIG. 1c to form a copper metal layer 108 on the copper alloy layer 106 in the conventional p v D process. As the current semiconductor process line width is shrinking, for example, below 0.1 micron (# m), the aspect ratio of the via hole 丨 02a is increased, so the copper metal layer 108 is filled by the pvd process. The via hole 102a is easy to form a hole due to overhang, as shown in the figure. Finally, please refer to FIG. 1d, and remove the copper metal layer 108 and the copper alloy layer 106 on the dielectric layer 102 through the conventional chemical mechanic polishing (CMP) process and place them in the hole of the dielectric layer. 2 & the subgastric copper metal layer 108 and the copper alloy layer 106 are used as interconnects. Although the tin atoms in this interconnect can effectively suppress the occurrence of copper electromigration because they are located at the grain boundary of copper, but due to the formation of holes in the interconnect, as shown in the figure, the quality of the interconnect is not good. And cause other electrical problems. In view of this, the present invention provides a method for manufacturing interconnects that suppresses electromigration of copper. The method uses electroless deposition instead of physical chemical vapor deposition (pVD) to manufacture interconnects and uses a palladium-tin-containing catalyst. To perform the activation treatment. Next, an annealing process is applied to diffuse tin atoms to the surface of the copper interconnects, which has the advantages of being dense and void-free, inhibiting electromigration, and blocking diffusion.

0503-7100twf ； TSMC2001-1068 ； Chen.ptd 第5頁 52l39〇五、發明說明（3) 進而提昇積發明概述：本發明造方法，其連線，以抑本發明線製造方法内連線之銅根據上連線製造方有具介層洞 ’以作為鍍鍍敷層於介連線實施一再者，更包一阻障層的層且把錫觸 2 5 0 〇C 到 4 5 0 又根據内連線製造成有具介層層，以作為觸媒的環境之銅内連線體電路之可靠度。之目的在於提供一種抑制銅電遷移之内連線裂在含有把錫觸媒的環境下無電鍍沉積法製造内制銅電遷移並形成緻密無孔洞之内連線。之另一目的在於提供一種抑制銅電遷移之内連 ’其藉由在内連線實施一熱退火處理，以抑制原子擴散至介電層。述之目的，本發明提供一種抑制銅電遷移之内法，包括下列步驟：提供一基板，基板上形成之介電層；在介層洞之内表面形成一銅晶種層敷之基底；在含有鈀錫觸媒的環境下，填入^ 層洞内’以構成一含錫之銅内連線；以及對内熱退火處理，以將錫原子擴散至内連線表面。括在形成銅晶種層之前在介層洞之内表面形成 v驟其中，利用無電鍍沉積法形成該銅鑛數媒係一鈀錫膠體。另外，熱退火處理溫度在 °C的範圍。上述之目的，本發明提供一種抑制銅電遷移之方法，包括下列步驟：提供，基板，基板上形 2 2 ’丨電層：在介層洞之内表♦形成-銅晶種、又之基底’依序在含有氯化錫觸媒及氯化鈀下，填入銅鍍敷層於介層洞内，以 ;以及對内連線實施一熱退火卢理 ^^ ^ …、疋人處理，以將錫原0503-7100twf; TSMC2001-1068; Chen.ptd Page 5 52l390. 5. Description of the invention (3) Further enhancement of the invention summary: The method of the present invention, which is connected to suppress the copper wire connected in the method of manufacturing the wire of the present invention According to the manufacturer of the connection line, there is a hole with interlayers, which is used as a plating and plating layer on the connection lines, and it is implemented again and again, and a layer of a barrier layer is included, and the tin is contacted from 2 5 0 0 C to 4 5 0 The connection is manufactured with copper interlayer body circuits with a dielectric layer as a catalyst environment. The purpose is to provide a method for suppressing cracks in copper electromigration interconnects. Electromigration of copper under electroless deposition in an environment containing tin catalysts to form dense and void-free interconnects. Another object is to provide an interconnect that suppresses the electromigration of copper by performing a thermal annealing treatment on the interconnect to suppress the diffusion of atoms into the dielectric layer. For the purposes described, the present invention provides an internal method for suppressing copper electromigration, including the following steps: providing a substrate, a dielectric layer formed on the substrate; forming a copper seed layer substrate on the inner surface of the via; In an environment containing a palladium-tin catalyst, it is filled into the ^ layer holes to form a tin-containing copper interconnect; and an internal thermal annealing treatment is performed to diffuse tin atoms to the surface of the interconnect. Including the formation of a copper seed layer on the inner surface of the via hole before the formation of a step, wherein the electroless deposition method is used to form the copper ore media-based palladium tin colloid. The thermal annealing temperature is in the range of ° C. For the above purpose, the present invention provides a method for suppressing electromigration of copper, which includes the following steps: providing, a substrate, and a 2 2 '丨 electric layer on the substrate: formed within the interlayer hole ♦ formation of a copper seed and a substrate 'Sequentially fill the copper plating layer in the interlayer hole with tin chloride catalyst and palladium chloride; and perform a thermal annealing on the interconnects ^^ ^, ... Xiyuan

521390 五、發明說明（4) 子擴散至内連線表面。再者，更包括在形成銅晶種層之前在介層洞之内表面形成一阻障層的步驟。其中，利用無電鍍沉積法形成該銅鍍敷層。另外，熱退火處理溫度在2 5 0 °C到450 °C的範圍。圖式之簡單說明：為讓本發明之上述目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：第1 a到1 d圖係繪示出習知形成含錫或鎂合金之銅内連線製程剖面示意圖。第2a到2e- 1圖係繪示出根據本發明實施例之抑制銅電遷移之内連線製造方法剖面示意圖。 [符號說明] 1 0 0、2 0 0〜基板； 1 0 2、2 0 2〜介電層； 102a、202a〜介層洞； 204〜阻障層； 106〜銅合金層； 108〜銅金屬層； 206〜銅晶種層； 208〜銅鍍敷層； 209〜銅電鍍層。較佳實施例之詳細說明：以下配合第2a到2e圖說明本發明實施例之抑制銅電遷 .夕r '1' 移之内連線製造方法。丨': 首先，請參照第2a圖，提供一基板20 0，例如一矽晶圓，其中此基板200上形成有電路及元件，此處為簡化圖式僅繪示出一平整表面。接著，在基板2 00上形成一介電521390 V. Description of the invention (4) The ions diffuse to the surface of the interconnect. Furthermore, it further comprises the step of forming a barrier layer on the inner surface of the via hole before forming the copper seed layer. The copper plating layer is formed by an electroless deposition method. In addition, the thermal annealing treatment temperature ranges from 250 ° C to 450 ° C. Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings, as follows: Figures 1 a to 1 d A schematic cross-sectional view of a conventional process for forming copper interconnects containing tin or magnesium alloys is shown. Figures 2a to 2e-1 are schematic cross-sectional views illustrating a method for manufacturing an interconnect that suppresses copper electromigration according to an embodiment of the present invention. [Description of symbols] 100, 2000 ~ substrates; 102, 202 ~ dielectric layer; 102a, 202a ~ via hole; 204 ~ barrier layer; 106 ~ copper alloy layer; 108 ~ copper metal Layer; 206 ~ copper seed layer; 208 ~ copper plating layer; 209 ~ copper plating layer. The detailed description of the preferred embodiment: The following describes the manufacturing method of the inner connection for suppressing the copper electrical migration. The r'1 'shift according to the embodiment of the present invention with reference to Figures 2a to 2e.丨 ': First, please refer to FIG. 2a, and provide a substrate 200, such as a silicon wafer, in which circuits and components are formed on the substrate 200. Here, only a flat surface is shown for simplicity. Next, a dielectric is formed on the substrate 2000.

0503-7100twf ； TSMC2001-1068 ； Chen.ptd 第7頁 5213900503-7100twf; TSMC2001-1068; Chen.ptd page 7 521390

層2 0 2。然後，藉由微影蝕刻技術在介電層2 〇 2上形成一介層洞202a。接下來’請參照第2b圖，藉由物理氣相沉積（pvD ) 法在介電層2 〇 2上及介層洞2 〇 2a内順應性形成一擴散阻障層\04 ’例如氮化鈦（TiN )或氮化鈕（TaN )，以防止在後續製程中，金屬原子擴散至介電層2 〇 2，例如銅原子。在本實施例中，阻障層204係使用氮化鈕（TaN )。另外亦可忽略形成此阻障層2 〇 4之步驟，其原因於本文稍後說明0 接下來’請參照第2 c圖，同樣藉由p v D製程以順應性沉積一銅晶種層20 6於阻障層204上。當然，在沒有形成阻障層2 0 4的情形下，則晶種層2 〇 6直接形成於介電層2 〇 2上及介層洞202a之内表面。形成此晶種層2〇β的目的在於作為後續鍍敷（plating)製程之基底，其厚度一般在2〇〇到 1 0 0 0埃（A )之間。接下來，請參照第2d圖，以鈀錫（pdSn )膠體 (colloid)作為鍍敷製程前活化處理（catalyzati〇n) 之觸媒（catalyst )，並在銅晶種層20 6表面形成一觸媒層（未繪示）。在本實施例中，鍍敷製程係指無電鍍沉積法或電鍍沉積法。接著，將完成上述步罄冬基板2 〇〇浸入電鍍液中並以無電鍍沉積法在介電層202·表®上及介層洞 202a内’或是在表面形成有阻障層204及/或銅晶種層206 的介電層202及介層洞202a内全面性覆蓋一緻密無孔洞之銅鍍敷層208，而構成一含錫之銅鍍敷層208。另外，請參Layer 2 0 2. Then, a via hole 202a is formed in the dielectric layer 202 by a lithography etching technique. Next, please refer to FIG. 2b. A diffusion barrier layer \ 04 is conformed to be formed on the dielectric layer 202 and the dielectric hole 200a by physical vapor deposition (pvD) method, such as titanium nitride. (TiN) or nitride button (TaN) to prevent metal atoms from diffusing to the dielectric layer 200, such as copper atoms, in subsequent processes. In this embodiment, the barrier layer 204 is a nitride button (TaN). In addition, the step of forming the barrier layer 2 04 can be omitted, the reason is explained later in this article. 0 Next 'Please refer to FIG. 2 c, and also deposit a copper seed layer 20 6 conformably by the pv D process. On the barrier layer 204. Of course, in the case where the barrier layer 204 is not formed, the seed layer 206 is directly formed on the dielectric layer 202 and the inner surface of the via hole 202a. The purpose of forming the seed layer 20β is to serve as a substrate for a subsequent plating process, and its thickness is generally between 200 and 100 angstroms (A). Next, referring to FIG. 2d, a palladium tin (pdSn) colloid is used as a catalyst for a catalyst activation (catalyzation) before the plating process, and a contact is formed on the surface of the copper seed layer 20 6 Media layer (not shown). In this embodiment, the plating process refers to an electroless deposition method or an electroplating method. Then, the above-mentioned stepped substrate 200 is immersed in a plating solution and the electroless deposition method is used to form a barrier layer 204 and / or a dielectric layer 202 on the surface of the dielectric layer 202 and the surface of the interlayer hole 202a and / Or the copper seed layer 206 and the dielectric layer 202 and the via hole 202a of the copper seed layer 206 are completely covered with the copper plating layer 208 which is uniform and non-porous to form a copper plating layer 208 containing tin. Also, see

0503-7100twf ； TSMC2001-1068 ； Chen.ptd 第8頁 521390 五、發明說明（6) 照第2 d - 1圖，上述銅鍍敷層2 0 8亦可順應性形成於介電層 202上及介層洞202a内，或是形成於表面形成有阻障層204 及/或銅晶種層206的介電層202及介層洞202a内。接著，再以電鍍沉積法在銅鍍敷層2 0 8上全面性覆蓋一銅電鍍層 209 〇接下來，請參照第2 e圖，藉由習知化學機械研磨 (chemical mechanic polishing，CMP)製程研磨去除銅0503-7100twf; TSMC2001-1068; Chen.ptd Page 8 521390 5. Description of the invention (6) According to Figure 2 d-1, the above copper plating layer 208 can also be conformably formed on the dielectric layer 202 and The via hole 202a is formed in the dielectric layer 202 and the via hole 202a with the barrier layer 204 and / or the copper seed layer 206 formed on the surface. Next, a copper plating layer 209 is completely covered on the copper plating layer 208 by the electroplating deposition method. Next, referring to FIG. 2e, by the conventional chemical mechanical polishing (CMP) process Grinding to remove copper

鍍敷層208並在介層洞内202a留下此銅鍍敷層208而構成一含錫之銅内連線。或者，去除銅電鍍層209及銅鍍敷層208 並在介層洞内202a留下銅電鍍層209及銅鍍敷層208而同樣構成一含錫之銅内連線，如第2e-1圖所示。由於此内連線中的錫原子會佔據在銅晶界上，如此便可有效抑制銅電遷移。最後，對此内連線實施一熱退火處理，其熱退火處理 /瓜度在2 5 0 C到4 5 0 C的範圍。如此一來，便可以將内連線中的錫原子擴散至内連線表面（未繪示）而有效抑制銅原子擴散至介電層2 0 2。亦即，具有擴散阻障層之功效。因此，可忽略形成阻障層2 〇 4之步驟。The plating layer 208 and the copper plating layer 208 are left in the via hole 202a to form a tin-containing copper interconnect. Alternatively, the copper plating layer 209 and the copper plating layer 208 are removed and the copper plating layer 209 and the copper plating layer 208 are left in the via hole 202a to form a copper interconnect including tin, as shown in FIG. 2e-1. As shown. Since the tin atoms in this interconnect will occupy the copper grain boundaries, the electrical migration of copper can be effectively suppressed. Finally, a thermal annealing process is performed on the interconnects, and the thermal annealing process / degree is in the range of 250 ° C to 450 ° C. In this way, the tin atoms in the interconnects can be diffused to the surface of the interconnects (not shown), and the copper atoms can be effectively inhibited from being diffused into the dielectric layer 202. That is, it has the effect of a diffusion barrier layer. Therefore, the step of forming the barrier layer 204 can be omitted.

在上述實施例中，係以在含鈀錫觸媒的環境下進行鍍敷製程作範例’然而本發明另一做法係在完成第2以2(^ 之步驟之後’將基板2〇〇依序浸入作為觸媒之氯化錫 (SnCl2 )溶液及氯化鈀（PdC12 )溶液，以在阻障層2〇4 銅晶種層206表面形成觸媒層（未綠示）’並進行益電鍍沉積以形成含錫之銅鍍敷層208，如第2d圖所示，或是‘ 序進行無電鍍沉積1電鍍沉積以分別形成含錫之In the above embodiments, the plating process is performed as an example in an environment containing a palladium tin catalyst. However, another method of the present invention is to complete the substrate 200 sequentially after completing the second step (2). Immerse in a tin chloride (SnCl2) solution and a palladium chloride (PdC12) solution as catalysts to form a catalyst layer (not shown in green) on the surface of the barrier layer 204 copper seed layer 206 'and perform electroplating In order to form a tin-containing copper plating layer 208, as shown in FIG. 2d, or in the order of electroless deposition 1 and electroplating to form tin-containing copper

521390 五、發明說明（7) 208及銅電鍍層209，如第圖所示。再|，由於後續步 f與上述貫施例相同’在此不重複說明。此外，上述根據 .月之!!連線製造雖以單鑲嵌（damascene)式之内連線製造作範例，缺而太名又 '、 t明並未受限於此’本發明亦可靡用於雙鑲嵌製程中内連線H U7T 了應雖然本發明已以較佳徐限定本發明，任何孰習=轭例揭鉻如上，然其並非用以神和範圍内，當可作更勤7技藝者，在不脫離本發明之精當視後附之申請專利範圍；：J者：：本發明之保護範圍521390 V. Description of the invention (7) 208 and copper plating layer 209, as shown in the figure. Furthermore, since the subsequent step f is the same as the above-mentioned embodiment, the description will not be repeated here. In addition, the above is based on the month. Although the connection manufacturing is based on a single damascene-type interconnection manufacturing as an example, it is abbreviated and is not limited to this. The present invention can also be used In the dual-damascene process, the internal connection H U7T should be used. Although the present invention has better limited the present invention, any practice = yoke example to expose chromium as above, but it is not used within the scope of God and can be used more frequently. Artists, without departing from the scope of patent application attached to the essence of the invention; J :: the scope of protection of the invention

Claims

六、申請專利範圍六、申請專利範圍驟 τ歹彳步丨.-種抑制銅電遷移之内連線製造方法，包括基底； ?供-基板’該基板上形成在該介層洞之内表面形成洞之介電層；之 ; j日日種層，以作為鍍數在含有鈀錫觸媒的環境下，内，以構成-含錫之銅内連線；以、及銅鍍敷層於該介層洞内連連線實施-熱退…，以將錫原子擴散至該㈣11、t請專利範圍第1項所述之抑制銅電遷移之内連、、、^ 4 ，更包括在形成該銅晶種層之前在該介層洞之内表面形成一阻障層的步驟。 ,3 ·如申請專利範圍第1項所述之抑制銅電遷移之内連線製造方法，其中利用物理氣相沉積法形成該銅晶種層。 4 ·如申請專利範圍第1項所述之抑制銅電遷移之内連線製造方法，其中利用無電鍍沉積法形成該銅鍍敷層。 5 ·如申請專利範圍第1項所述之抑制銅電遷移之内連線製造方法，其中該鈀錫觸媒係一鈀錫膠體。 6 ·如申請專利範圍第1項所述之抑制銅電遷移之内連線製造方法，其中該熱退火處理溫度在250 °C到450 °C的範圍。 7 ·如申請專利範圍第2項所述之抑制銅電遷移之内連線製造方法，其中該阻障層為氮化钽。 8 · —種抑制銅電遷移之内速線製造方法，包括下列步 0503-7100twf ； TSMC2001-1068 ； Chen.ptd 第11貢 521390Sixth, the scope of the patent application Sixth, the scope of the patent application step τ 丨.-A method for manufacturing copper interconnects to suppress the electromigration, including a substrate;-supply-substrate 'The substrate is formed on the inner surface of the via hole Forming a dielectric layer of the hole; of the j-day seed layer to be used as the plating number in an environment containing a palladium-tin catalyst to form a copper interconnect including tin; and a copper plating layer on the The inter-connecting hole of the interlayer hole is implemented by thermal withdrawal ... to diffuse the tin atoms to the inter-connecting copper, copper, copper, copper, and copper, which are described in item 1 of the patent scope, and are included in the formation. The step of forming a barrier layer on the inner surface of the via hole before the copper seed layer. 3, The method for manufacturing an interconnect for suppressing copper electromigration as described in item 1 of the scope of the patent application, wherein the copper seed layer is formed by a physical vapor deposition method. 4. The method for manufacturing an interconnect for suppressing copper electromigration according to item 1 of the scope of patent application, wherein the copper plating layer is formed by an electroless deposition method. 5. The method of manufacturing an interconnect for suppressing copper electromigration as described in item 1 of the scope of the patent application, wherein the palladium tin catalyst is a palladium tin colloid. 6 · The method for manufacturing copper interconnects as described in item 1 of the scope of patent application, wherein the thermal annealing treatment temperature is in a range of 250 ° C to 450 ° C. 7. The method for manufacturing an interconnect for suppressing copper electromigration as described in item 2 of the scope of the patent application, wherein the barrier layer is tantalum nitride. 8 · A method for manufacturing internal velocity wires that suppress copper electromigration, including the following steps: 0503-7100twf; TSMC2001-1068; Chen.ptd 11th Tribute 521390

六、申請專利範圍驟：提供一基板，該基板上形成有具介層洞之介電層；在該介層洞之内表面形成一銅晶種層，以作基底； 1数之依序在含有氯化錫觸媒及氯化鈀觸媒的環境下，填銅鍍敷層於該介層洞内，以構成一含錫之銅内連線；以及對該内連線實施一熱退火處理，以將錫原子擴散至該内連線表面。 ~ 9 ·如申請專利範圍第8項所述之抑制銅電遷移之内連線裝ie方法’更包括在形成該銅晶種層之前在該介層洞之内表面形成一阻障層的步驟。 I 0 ·如申請專利範圍第8項所述之抑制銅電遷移之内連線製造方法’其中利用物理氣相沉積法形成該銅晶種層。 II ·如申請專利範圍第8項所述之抑制銅電遷移之内連線製造方法，其中利用無電鍍沉積法形成該銅鍍敷層。 1 2 ·如申請專利範圍第8項所述之抑制銅電遷移之内連線製造方法’其中該熱退火處理溫度在250 °C到450 °C的範圍。 1 3 ·如申請專利範圍第9項所述之抑制銅電遷移之内連線製造方法’其中該阻障層為氮化纽。>:·6. Scope of applying for patent: Provide a substrate on which a dielectric layer having a dielectric hole is formed; a copper seed layer is formed on the inner surface of the dielectric hole as a base; In an environment containing a tin chloride catalyst and a palladium chloride catalyst, a copper plating layer is filled in the via hole to form a tin-containing copper interconnect; and a thermal annealing process is performed on the interconnect. To diffuse tin atoms to the surface of the interconnect. ~ 9 · The method for mounting copper interconnects as described in item 8 of the scope of the patent application 'further includes the step of forming a barrier layer on the inner surface of the via hole before forming the copper seed layer . I 0 · The method of manufacturing an interconnect for suppressing copper electromigration according to item 8 of the scope of the patent application, wherein the copper seed layer is formed by a physical vapor deposition method. II. The method of manufacturing an interconnect for suppressing copper electromigration as described in item 8 of the scope of patent application, wherein the copper plating layer is formed by an electroless deposition method. 1 2 · The method for manufacturing an interconnect for suppressing copper electromigration according to item 8 of the scope of the patent application, wherein the thermal annealing treatment temperature is in a range of 250 ° C to 450 ° C. 1 3 · The method of manufacturing an interconnect for suppressing copper electromigration as described in item 9 of the scope of the patent application, wherein the barrier layer is a nitride nitride. > ::

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