TW411569B - Method of using the electroless plating technology to fabricate the copper/gold connections in integrated circuits - Google Patents
Method of using the electroless plating technology to fabricate the copper/gold connections in integrated circuits Download PDFInfo
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4ίΐ569 五、發明說明（1) , 發明背景 (1 )發明領域 本發明案的主要内容係關於如何於半導體元件上 ’ 製作金屬連接導線的製程，特別是使用無電鍍技術产 半導體元件上製作金或銅金屬導線結構。 2 )先前技藝的描述 本發明案的主要内容係有關於無電鍍技術如何應用 在半導體元件上製作金屬連接導線的製程，更重要的是 應用無電鍍銅或鎳的製程於積體電路上製作金屬導線或 金屬隆點（metal bump)。此製程也關係到如何於半導體 材料或構裝基板上製作高密度（高解析度）的傳導金屬線 路的圖案（pattern)。 無電鍍製程是一種可以於某些材料或者是半導體基 板上沉積金屬薄膜的技術之一。無電鍍製程的主要步驟 是將基板於適當的條件下，浸入含有欲鍍金屬離子的溶> 液中，使得金屬離子能夠在基板的表面上析出。無電鍍 製程與傳統的電鍍製程並不相同，因為電鍍製程需要外 加電場，以使離子發生氧化還原的反應而於基板上析 出，可是無電鍍製程並不需要外加的電場。無電鍍製程 同時也具有選擇性沉積的優點，也就是說，此沉積過程 只會在基板的某些區域發生，但這些區域須具有合適的 電化學表面特性，例如無電鍍反應可能只發生在與欲鍍 金屬相同的材料上，或者是對欲鍛金屬較有親和力 (affinity)的材料上，因此可以針對基板上的某些區域4ίΐ569 V. Description of the Invention (1), Background of the Invention (1) Field of the Invention The main content of the present invention relates to the process of how to make metal connection wires on a semiconductor element, especially the use of electroless plating technology to produce gold or Copper metal wire structure. 2) Description of previous technology The main content of the present invention is about how the electroless plating technology is applied to the process of making metal connection wires on semiconductor elements, and more importantly, the process of electroless copper or nickel is used to make metal on integrated circuits Wire or metal bump. This process is also related to how to make a high-density (high-resolution) conductive metal circuit pattern on a semiconductor material or a mounting substrate. Electroless plating is one of the technologies that can deposit metal thin films on certain materials or semiconductor substrates. The main step of the electroless plating process is to immerse the substrate in a solution containing metal ions to be plated under appropriate conditions, so that metal ions can be deposited on the surface of the substrate. The electroless plating process is not the same as the traditional electroplating process, because the electroplating process requires an external electric field to cause ions to undergo redox reactions and precipitate on the substrate. However, the electroless plating process does not require an external electric field. The electroless plating process also has the advantage of selective deposition, that is, this deposition process can only occur in certain areas of the substrate, but these areas must have appropriate electrochemical surface characteristics. For example, the electroless plating reaction may only occur with On the same material to be plated or on materials that have more affinity for the metal to be forged, it can target certain areas on the substrate
D:\patent\nbs\870040. ptd 第4頁 411569 五、發明說明（2) 進行化學處理或者是利用催化劑（c a t a 1 y s t )進行活化 (activation)處理，使得金屬薄膜會以較快的沉積速度 在這些具有催化特性的區域沉積金屬鍍層。而這些在’基 板中具有催化特性的區域，被稱之為成核層（seed _ 1 a y e r )。我們也定義出在真有催化活性的區域中，其沉 積速度與不具催化活性的區域中的沉積速度的比值為 “無電鐘製程的選擇比（electroless plating process selectivity) 。無電鍵製程的沉積速度與催化活性區 域的表面物理特性有關，例如此區域的面積大小及方向 比（aspect ratio)等。針對基板上同樣具有催化特性但 不同的區域而言，如果金屬沉積速率都相近的話，即稱 之為此沉積製程的均勻性良好。對很多應用而言，製程 均勾性，製程選擇性以及沉積金屬薄膜與基板間的附著 性等，均是決定此製程成敗與否的重要因素。 增加金屬鍍層與基板間的附著力的方法之一是先將 基板進行熱退火（annealing)處理，而會影響錢層均勻 性、製程選擇性以及鍍層物理特性的因素包括：鍍層沉 積溫度、鍍浴中的離子濃度、沉積時間、鍍浴的p Η值 等。這些因素的組合即成為我們所稱的“技術製程窗口 (technological process window) ，為了 要確認無電 鍍製程的再現性及均一性，技術製程窗口應該要越大越 好。 無電鍍製程技術的原理是從含有金屬離子的溶液中 析出金屬薄膜於具有催化活性的基板表面上，這種製程D: \ patent \ nbs \ 870040. Ptd page 4 411569 5. Description of the invention (2) Chemical treatment or activation treatment using catalyst (cata 1 yst), so that the metal film will be deposited at a faster rate Metal coatings are deposited on these areas with catalytic properties. These regions with catalytic properties in the 'substrate' are called nucleation layers (seed _ 1 a y e r). We also define the ratio of the deposition rate to the rate of deposition in areas where there is no catalytic activity as "electroless plating process selectivity. The deposition rate and catalysis of non-bonded processes The surface physical properties of the active area are related, such as the area size and aspect ratio of the area. For different areas on the substrate that also have catalytic properties, but different metal deposition rates are similar, this is called this. The uniformity of the deposition process is good. For many applications, the uniformity of the process, the selectivity of the process, and the adhesion between the deposited metal film and the substrate are all important factors that determine the success or failure of this process. Add metal plating and substrate One of the methods of adhesion is to thermally anneal the substrate first. Factors that affect the uniformity of the layer, process selectivity, and physical properties of the coating include: coating deposition temperature, ion concentration in the plating bath, Deposition time, pΗ value of plating bath, etc. The combination of these factors becomes our Called "technical process window (technological process window), in order to confirm the electroless plating process reproducibility and uniformity, technology process window should be larger the better. The principle of electroless plating process is to deposit a metal thin film from a solution containing metal ions on the surface of a substrate with catalytic activity.
D:\patent\nbs\870040. ptd 第5頁 •i , 五、發明說明（3) 很早就已經被應用在印刷電路板（p r i n t e d c board)的工業中以製作印刷電路板上的金屬 通孔（via hole)的連接導線結構13最近這項 被應用在積體電路的製程中，以製作金屬連 電鍵技術與其他技術（例如滅鑛（sputtering (evaporation))相較起來，此製程擁有相當 而其中最大的優點是無電鍍製程所使用的材 本均便宜很多，亦即其生產的成本遠低於其 另外還有一相當重要的優點是無電鍍製程具 積的優點，也就是說無電鍍反應只會在具有 表面上發生，因此具有選擇性沉積的優點是 次微影（photolithographic patterning)和 的步驟來去除多餘的金屬。無電鍍金屬製程 積體電路中沉積不易被蝕刻的金屬薄膜材料 金屬雖然具有低阻值的優點，可是卻不易被 此可以利用無電鍍技術於積體電路上製作高 線結構，以進一步降低金屬導線的阻值。 無電鍍製程的優點還包括其沉積速度相 沉積速率與其基板表面型態的差異較無明顯 性質可以使無電鍍製程應用於印刷電路板及 具高方向比（high· aspect eatio)的導通孑LJ 濺鍍和蒸鍍技術於導通孔的應用，均無法沉 勻的金屬薄膜鍍層。 目前發表的論文中最常被提及的是將無 i r c u i t 導線以及導 製作技術’更 接導線 '無 )或蒸鍍 多的優點， 料與設備成 他的製程。 有選擇性沉 催化活性的 可以減少一 姓刻（e t c h ) 也被應用在 上，例如銅 乾蝕刻，因 密度的銅導 當快，且其 的關係。此 積體電路上 二，相較於 積出厚度均 電鍍技術應D: \ patent \ nbs \ 870040. Ptd Page 5 • i, V. Description of the invention (3) It has been applied to printed circuit board industry for making metal through holes on printed circuit boards for a long time. (Via hole) connecting wire structure 13 Recently, this process has been applied to the manufacturing process of integrated circuits. Compared with other technologies (such as sputtering (evaporation)), this process has considerable advantages. The biggest advantage is that the materials used in the electroless plating process are much cheaper, that is, the production cost is much lower than it. Another important advantage is that the electroless plating process has a built-in advantage, which means that the electroless plating reaction only It will occur on the surface, so the advantage of selective deposition is the photolithographic patterning and steps to remove excess metal. Metal film materials that are not easily etched are deposited in the integrated circuit of electroless metal process. The advantage of low resistance, but it is not easy to use this. Electroless plating technology can be used to fabricate high-line structures on integrated circuits to further reduce gold. It is a resistance value of the wire. The advantages of the electroless plating process also include the difference between the deposition rate and the deposition rate of the substrate and the surface type of the substrate. ) The application of LJ sputtering and vapor deposition technology to vias can not evenly deposit metal thin film coatings. The most commonly mentioned in the published papers is the use of ircuit-free conductors and conductive fabrication technology to connect the conductors. 'None' or more advantages of evaporation, materials and equipment into his process. The selective catalytic activity can reduce the nick (e t c h) is also applied to, such as copper dry etching, because the density of copper conducts quickly, and its relationship. Compared with the integrated circuit, the thickness of the integrated circuit
D:\patent\nbs\870040. ptd 第6頁 五、發明說明（4) 用在積體電路中的接觸孔（contact hole)以及導通孔 (via hole)上，傳統製作接觸孔的方式是利用曝光顯影 的製程於介電層上先定義出接觸孔的位置，然候再用蝕 刻方式蝕刻介電層至矽晶片表面上元件的傳導層上，接 著再沉積金屬，使其與元件的傳導層相連接，所以接觸 孔的主要目的是連接上層的導電金屬層與晶片表面上元 件上的導電層相連，而形成完整的連接導線結構。無電 鍍製程因為具有選擇性沉積的特性，所以非常適合作為 沉積接觸孔中金屬薄膜鍍層，這樣的製程產生了 一個金 屬“栓塞（p 1 ug ) ” ，來作為上層與下層金屬間的連接， 利用無電鍍製程製作金屬栓塞的優點是可以控制金屬栓 塞中沉積金屬的厚度到與介電層表面一樣的高度，如此 可以避免在接觸孔金屬的沉積過程_，於接觸孔開口附 近因高度差異所產生的表面不平坦的現象，這些不平坦 的問題，會對後續的製程產生不穩定的現象。 雖然無電鍍技術應用在積體電路中的接觸孔及導通 孔的金屬薄膜沉積製程，可以讓製程設計者多一些選 擇，可是應用這項技術於積體電路中仍然有相當多的問 題尚待解決，因為這些技術看起來雖然很簡單，但是在 沉積過程中於基板表面上發生的化學反應卻是相當複雜 的。會限制無電鍍技術被廣泛應用的因素，包括了如何 在沉積過程中於基板上獲得厚度均勻的金屬鍍層、沉積 過程中降低污染物對此製程的敏感度、以及控制金屬薄 膜的沉積過程中得到較佳的製程選擇性..等等。這些影D: \ patent \ nbs \ 870040. Ptd Page 6 V. Description of the invention (4) Used in contact holes and via holes in integrated circuits. The traditional method of making contact holes is to use The process of exposure and development first defines the position of the contact hole on the dielectric layer. Then, the dielectric layer is etched to the conductive layer of the component on the surface of the silicon wafer by etching, and then the metal is deposited to make it contact the conductive layer of the component. Phase connection, so the main purpose of the contact hole is to connect the upper conductive metal layer with the conductive layer on the component on the surface of the wafer to form a complete connection wire structure. The electroless plating process is very suitable for depositing metal thin film coatings in contact holes because of its selective deposition characteristics. Such a process creates a metal "plug (p 1 ug)" as the connection between the upper and lower metals. The advantage of making metal plugs without electroplating is that the thickness of the deposited metal in the metal plug can be controlled to the same height as the surface of the dielectric layer. This can avoid the deposition process of the metal in the contact hole_, which is caused by the height difference near the opening of the contact hole. The unevenness of the surface, these unevenness problems will cause instability in subsequent processes. Although the electroless plating technology is applied to the metal film deposition process of contact holes and vias in integrated circuits, it can give process designers more choices, but there are still many problems to be solved in applying this technology to integrated circuits Because these technologies seem simple, the chemical reactions that occur on the substrate surface during the deposition process are quite complicated. Factors that will limit the widespread application of electroless plating techniques include how to obtain a uniform metal coating on the substrate during the deposition process, reduce the sensitivity of contaminants to this process during the deposition process, and control the metal film deposition process to obtain Better process selectivity .. etc. These shadows
D:\patent\nbs\870040.ptd 第7頁 五、發明說明（5) _ 響無電鍍製程的因素中，又多與基板表面的活化程序有 關，也就是說如何讓基板表面變成具有催化活性，以利 後續的無電鍍反應能夠順利進行是相當重要的。本發’明 案提出了新的表面活化處理技術，使得基板表面具有，催 化能力，所以能獲得更均勻的無電鍍層厚度。 最近有很多專利以及技術文件中發表有關基板表面 活化的技術，這些發表的文獻大多是於基板上的某些區 域吸附一原子層或者是沉積一薄金屬層。至於是需要利 用吸附的原子層或者是沉積薄金屬層來達到活化的目 的，則視我們我們實際的製程而定。目前最常將無電鍍 技術應用於積體電路製程中，是無電鍍鎳、鈷、鈀、和 銅金屬。石夕晶片的表面可能是複晶石夕（ρ ο 1 y s i 1 i c ο η )、 鋁、鋁合金或者是銅。而非傳導層材料包括了二氧化矽 (Si02)、氮化矽（Si3M4)或者是其它高分子聚合物的絕 緣層=目前在基材表面上施以活化的製程，可以區分為 三類：（1 )利用蒸鍍或濺鍍方式沉積一層具有催化性質 的材料；（2)利用電化學表面改質（electrochemical surface modification)技術沉積一廣具有催化性質的 #料；（3)利用膠體懸浮（collidal suspension)的方 式，沉積具有催化性.質的材料。 纪（Palladium ; Pd)和銘（Platinum ; Ρ〇 最常被使 用作為無電鍍製程前的催化表面金屬層，這兩種金屬可 以利用蒸鍍或濺鍍方式沉積於基材之上，然後利用傳統 的傳統的微影技術定義出導線的形狀，此法特別適合在D: \ patent \ nbs \ 870040.ptd Page 7 V. Invention Description (5) _ Among the factors that affect the electroless plating process, they are mostly related to the activation process of the substrate surface, that is, how to make the substrate surface become catalytically active. In order to facilitate the subsequent electroless plating reaction is very important. This invention's proposal proposes a new surface activation treatment technology, which enables the surface of the substrate to have a catalytic ability, so that a more uniform thickness of the electroless plating layer can be obtained. Recently, there are many patents and technical documents published on the surface activation technology of substrates. Most of these published documents are adsorption of an atomic layer or deposition of a thin metal layer on some areas of the substrate. As for the need to use the adsorbed atomic layer or the deposition of a thin metal layer to achieve the purpose of activation, it depends on our actual process. Currently, electroless plating is most commonly used in integrated circuit manufacturing processes and is electroless nickel, cobalt, palladium, and copper. The surface of the Shi Xi wafer may be polycrystalline Shi Xi (ρ ο 1 y s i 1 i c ο η), aluminum, aluminum alloy, or copper. The non-conductive layer materials include silicon dioxide (Si02), silicon nitride (Si3M4), or other high-molecular polymer insulation layers. Currently, the activation process is applied on the surface of the substrate, which can be divided into three categories: ( 1) Use evaporation or sputtering to deposit a layer of material with catalytic properties; (2) Use electrochemical surface modification technology to deposit a wide range of materials with catalytic properties; (3) Use collidal suspension (collidal suspension) to deposit catalytic materials. (Plaladium; Pd) and Platinum (Po; most commonly used as the catalytic surface metal layer before the electroless plating process, these two metals can be deposited on the substrate by evaporation or sputtering, and then use the traditional The traditional lithography technique defines the shape of the wire. This method is particularly suitable for
D:\patent\nbs\870040.ptd 第 8 頁 411569 五、發明說明（6) 有較寬的導線製作過程中。 有文獻指出以蒸鍍方式沉積的鈀金屬薄膜的催化活 性低於以其它方式製作的鈀膜（例如以電化學方式），' 這 層低催化活性的鈀膜會影響到後續無電鍍層的均勻性以 及產品最後的良率，特別是較窄的導線結構或者是較密 的導線樣式的影響特別明顯。無電鍍溶液中會添加穩定 劑（s t a b i 1 i z e r )以防止鍍浴的自然分解，所以穩定劑會 造成沉積過程中的尺寸（size) —和近接（proximity)效 應。穩定劑會減低或者是阻止在微小粒子上發生自催化 的無電鍍反應，而這些微小粒子可能是空氣中的灰塵或 者是鍍浴中的汙染粒子，穩定劑雖然可以抑制鍍浴的自 然分解，但是它也會影響金屬鍍層的機械性質以及電 性，儘管這些機制並不完全被瞭解。而且雖然如前所 述，鍍浴中的穩定劑會抑制微小粒子的自發分解過程， 但是它也會影響金屬鍍層沉積在基板上一些微細導線結 構的機制。不過幸運的是這些缺點可以利用修正鍍浴的 成份或者是製程的條件，以改善金屬鍍層的結構能及品 質，例如增加沉積溫度或者是減少鍍浴中穩定劑的濃 度，以改善無電鍍鍍層沉積在次微米寬度的導線結構的 製程穩定性，但是這些修正也會導致沉積的選擇性變差 以及鍍浴的穩定劑減弱等缺點發生。 事實上基板表面的活化處理步驟也會影響到無電鍍 鍍層的厚度均勾性以及沉積的選擇性，而且基板表面在 進行任何步驟之前及之後的清洗步驟，或者是基板在沉D: \ patent \ nbs \ 870040.ptd Page 8 411569 V. Description of the invention (6) There is a wide wire manufacturing process. Some literatures point out that the catalytic activity of palladium metal films deposited by evaporation is lower than that of palladium films prepared by other methods (such as electrochemical methods). 'This layer of low catalytic activity palladium film will affect the uniformity of subsequent electroless plating layers. The effect of the product and the final yield of the product, especially the narrower conductor structure or the denser conductor pattern, is particularly obvious. A stabilizing agent (s t a b i 1 i z e r) is added to the electroless plating solution to prevent the natural decomposition of the plating bath, so the stabilizing agent will cause size — and proximity effects — during the deposition process. Stabilizers can reduce or prevent self-catalyzed electroless plating reactions from occurring on tiny particles, which may be dust in the air or polluted particles in the plating bath. Although the stabilizer can inhibit the natural decomposition of the plating bath, but It also affects the mechanical properties and electrical properties of metal coatings, although these mechanisms are not fully understood. And although the stabilizer in the plating bath can inhibit the spontaneous decomposition of fine particles, as mentioned above, it also affects the mechanism of the metal wire deposits on the substrate for some fine wire structures. Fortunately, these disadvantages can be used to modify the composition of the plating bath or the process conditions to improve the structural energy and quality of the metal coating, such as increasing the deposition temperature or reducing the concentration of the stabilizer in the plating bath to improve the electroless plating deposition. The process stability of the sub-micron-wide wire structure, but these corrections also lead to disadvantages such as poor deposition selectivity and weakening of the stabilizer of the plating bath. In fact, the activation treatment step of the substrate surface will also affect the uniformity of the thickness of the electroless plating layer and the selectivity of the deposition. Moreover, the substrate surface is cleaned before and after any step, or the substrate is in a sinking state.
D:\patent\nbs\870040.ptd 第9頁 五、發明說明（7) 積金屬鍍層之前曝露在空氣中的時間長短，均會嚴重影 響鍍層厚度的均句性以及所欲沉積的導線形狀。 有很多文獻報導指出，利用電化學表面改質技術可 以得到較寬的操作範圍，且能使鍍層沉積在金屬或者是 介電層上。也有文獻指出在超大型積體電路的製程中， 將矽晶片浸入含有氣化鈀以及氩氣酸的溶液中，會在矽 晶片上的鋁金屬表面上吸附一層非常薄的的鈀金屬層作 為成核層。通常在鋁的表面上的薄氧化層可以於進行鈀 活化步驟前先將晶片浸入稀釋的氩氟酸溶液中去除，而 鋁表面的活化程度與鋁先前的表面處理製程有非常密切 的關係。影響活化程度的因素包括：活化液中的活化劑 (a c t i v a t 〇 r )濃度、活化溫度、活化時間等。如果要得 到高度活化的表面時，製程的窗口就會受到影響，例如 如果活化時間太短的話，將會導致表面的活化程度不 足，而使得沉積的金屬鍍層厚度不均勻，但是如果活化 時間太久的話，將會使得沉積金層與基板間的附著性產 生問題。所以已有很多人投入研究如何設計出一個穩定 性高、再現性高、以及容易操作的活化製程，儘管這樣 的製程不易達到。 鋁的另一種表面活化方式是將基板浸入含有鋅的強 鹼溶液裏，因為金屬鋅是非常適合作為無電鍍製程的催 化材料，這樣的製程稱之為鋅置換（zincating)，鋅置 換製程對於處理大體積的物件是非常有效的，可是對於 像積體電路中次微米尺寸的導線結構而言，此製程的窗D: \ patent \ nbs \ 870040.ptd Page 9 V. Description of the invention (7) The length of time the metal layer is exposed to the air before plating will seriously affect the uniformity of the thickness of the plating and the shape of the wire to be deposited. There are many reports in the literature that use electrochemical surface modification technology can obtain a wider operating range, and can deposit the plating layer on the metal or dielectric layer. Some literature also pointed out that in the process of super large integrated circuits, immersing a silicon wafer in a solution containing vaporized palladium and argon acid will adsorb a very thin palladium metal layer on the aluminum metal surface on the silicon wafer as a component. Nuclear layer. Generally, the thin oxide layer on the surface of aluminum can be removed by dipping the wafer in a dilute argon fluoride solution before the palladium activation step. The degree of activation of the aluminum surface is closely related to the previous surface treatment process of aluminum. Factors affecting the degree of activation include: the concentration of the activator (a c t i v a t 〇 r) in the activating solution, the activation temperature, the activation time, and the like. If a highly activated surface is to be obtained, the process window will be affected. For example, if the activation time is too short, the surface activation degree will be insufficient and the thickness of the deposited metal coating will be uneven, but if the activation time is too long If it does, it will cause problems in the adhesion between the deposited gold layer and the substrate. Therefore, many people have invested in researching how to design an activation process with high stability, high reproducibility, and easy operation, although such a process is not easy to achieve. Another method for surface activation of aluminum is to immerse the substrate in a strong alkali solution containing zinc, because metal zinc is very suitable as a catalytic material for electroless plating processes. Such a process is called zincating. The zinc replacement process is for processing Large-volume objects are very effective, but for sub-micron-sized wire structures in integrated circuits, the window of this process
D:\patent\nbs\870040. ptd 第10頁 411569 五、發明說明（8) 口是非常小的。至於鋅置換的製程條件以及對基板的影 響，均與上述的鈀活化製程相同β 傳統上於積體電路的製作過程中，會利用微影及_乾 蝕刻方式製作出金屬導線以及介電材料層。然而以往於 積體電路製程中常用的鋁-矽或鋁-矽-銅金屬，已不能 滿足很多需要，例如高熱穩定性、高抗電遷移 (electromigration)以及高腐姓阻抗（corrosion resistance)。銅因為有很多優於铭合金的特性，所以 已被認為是未來多層導線結構的傳導材料，可是銅也並 非是全無缺點的導電材料，例如在高溫的環境中，銅在 矽的移動率（m 〇 b i 1 i t y )非常得快，所以極易形成陷阱 (trap)而對元件造成嚴重的影響，也因為這些原因，我 們必須在銅與石夕之間加入一層擴散障礙層（d i f f u s i ο η barrier layer)材料，以抑制銅原子的擴散。一般而 言，擴散障礙層須具備下列的條件： a.擴散障礙層擴散至相鄰兩層的速度須很慢； b .擴散障礙層與相鄰兩層的反應速度須很慢； c. 擴散障礙層與相鄰兩層的附著性須很強； d. 擴散障礙層的厚度須非常的均勻； e. 從熱力學的觀點來看，擴散障礙層與相鄰兩層是屬 於穩定狀態的； f .擴散障礙層材料必須是具有低阻值的材料。 近年來無電鍍銅技術是相當受到大家注意，因為無 電鍍的設備成本低廉、沉積溫度低、沉積速度快且鍍層D: \ patent \ nbs \ 870040. Ptd page 10 411569 5. Description of the invention (8) The mouth is very small. As for the process conditions of zinc replacement and the effect on the substrate, they are the same as the above-mentioned palladium activation process. Traditionally, in the fabrication of integrated circuits, lithography and dry etching are used to produce metal wires and dielectric material layers. . However, the aluminum-silicon or aluminum-silicon-copper metal commonly used in the integrated circuit manufacturing process has not been able to meet many needs, such as high thermal stability, high electromigration, and high corrosion resistance. Copper has many characteristics that are superior to Ming alloy, so it has been considered as a conductive material for the future multilayer wire structure. However, copper is not a conductive material without defects. For example, in high-temperature environments, the mobility of copper in silicon ( m 〇 bi 1 ity) is very fast, so it is easy to form traps and severely affect the components. For these reasons, we must add a diffusion barrier between copper and Shi Xi (diffusi ο η barrier layer) material to suppress the diffusion of copper atoms. Generally speaking, the diffusion barrier layer must have the following conditions: a. The diffusion barrier layer must diffuse slowly to the adjacent two layers; b. The diffusion barrier layer and the adjacent two layers must react slowly; c. Diffusion The adhesion between the barrier layer and the adjacent two layers must be strong; d. The thickness of the diffusion barrier layer must be very uniform; e. From a thermodynamic point of view, the diffusion barrier layer and the adjacent two layers are stable; f The material of the diffusion barrier layer must be a material having a low resistance value. In recent years, electroless copper technology has attracted considerable attention because of the low cost of electroless equipment, low deposition temperature, fast deposition speed, and plating.
D:\pateat\nbs\870040. ptd 第11頁 41156¾ 五、發明說明（9) 品質相當好。在催化表面上進行的無電鍍銅製程，通常 被認為有兩種反應同時在進行，第一種為還原劑的陽極-氧化’而第二種是金屬離子的陰極還原。在無電鍍製-程 中所須要的催化表面的目的即是要用來催化還原劑氧化 而且將釋出的電子從陽極反應位置到發生陰極反應的地 方，因此我們如欲解決擴散障礙層不具催化表面特性的 問題，通常會在擴散障礙層之上沉積一附著層 (adhesion layer)材料。 克服上述所提出的無電鍍製程的諸多問題是非常重 要的’所以現在有很多專利以及技術文件均對此問題提 出改進之道；其中又以Zhao所提出的美國專利 5，674，787 *'Selective electroless copper deposited interconnect plugs for ULSI applications”提出很多改進的技術，Zhao於此篇專利 中提出一個於半導體基板上利用無電鍍具有選擇性沉積 的特性，製作出銅金屬栓塞，以形成多層導線的結構， 導通孔的主要目地在於讓被介電材料層所分隔開的不同 層金屬導線提供能夠相互連接的路徑，此介電層材料可 以是二氧化矽（S i 0 2 )、氮化矽（S i 3 N 4 )、或氮氧化矽 (Si ON)等材料，當導通孔製作完成後，會先於導通孔的 底部及四周先沉積TiN材料以作為擴散障礙層，然後再 利用接觸置換（contact displacement)法於擴散障礙層 之上形成一具有活化特性的薄銅金屬層，隨即可以進行 無電鍍反應，因為薄銅金屬層表面具有催化特性，所以D: \ pateat \ nbs \ 870040. Ptd page 11 41156¾ 5. Description of the invention (9) The quality is quite good. The electroless copper process on a catalytic surface is generally considered to have two reactions proceeding simultaneously, the first being anodizing of the reducing agent 'and the second being the cathodic reduction of metal ions. The purpose of the catalytic surface required in the electroless plating process is to catalyze the oxidation of the reducing agent and transfer the released electrons from the anode reaction position to the place where the cathode reaction occurs. Therefore, if we want to solve the diffusion barrier layer, there is no catalysis The problem of surface characteristics is usually to deposit an adhesion layer material on top of the diffusion barrier layer. It is very important to overcome the above-mentioned problems of the electroless plating process. Therefore, there are many patents and technical documents that have proposed ways to improve this problem. Among them, US Patent 5,674,787 proposed by Zhao * 'Selective "electroless copper deposited interconnect plugs for ULSI applications" put forward many improved technologies. In this patent, Zhao proposed a method of selectively depositing copper metal plugs on a semiconductor substrate using electroless plating to form a multilayer wire structure. The main purpose of the via is to allow different layers of metal wires separated by the dielectric material layer to provide paths that can be connected to each other. The material of the dielectric layer can be silicon dioxide (S i 0 2), silicon nitride (S i 3 N 4), or silicon oxynitride (Si ON) and other materials. After the vias are fabricated, TiN material is deposited as the diffusion barrier layer at the bottom and around the vias, and then contact replacement is used. displacement) method to form a thin copper metal layer with activation characteristics on the diffusion barrier layer The reaction, because the thin metal layer having a copper surface catalytic properties, so
D:\patent\nbs\870040.ptd 第 12 頁 411569 五、發明說明αο) 可以提供作為無電錄自催化反應的地方，亦即無電鑛銅 會沉積於導通孔内，直到導通孔幾乎被金屬填滿為止，· 然後再於導通孔的銅金屬上沉積擴散障礙層，以完成整 個導通孔的製作。 US 5，308’796(Feldman)提出利用印化把 (Palladium silicide)材料作為無電鍍反應的催化材 料。 US 5，169,680(Ting)提出利用無電鍍法製作金屬導 US 5，183,795(Ting)提出利用無電鍍具有選擇性沉 積的特性，製作銅金屬導線。 U S 5，5 6 2，7 6 0 ( B a 1 1 a r d )，u S 4，2 6 5，9 4 3 (Goldstein)中均討論無電鍍金屬沉積的製程。 1^[^等人於】.圧1€€1：1：〇(：116«1.8〇<:.，第136卷（1 9 89 ) 第2 期，第462-466 頁發表 “Selective electroless metal deposition for via hole filling in VLSI multi level interconnect ion structures ，討論到 無電鍍金屬的沉積技術。D: \ patent \ nbs \ 870040.ptd Page 12 411569 V. Description of the invention αο) can be provided as a place where the electroless recording of the autocatalytic reaction, that is, electroless copper will be deposited in the via until the via is almost filled with metal When it is full, a diffusion barrier layer is then deposited on the copper metal of the via to complete the fabrication of the entire via. US 5,308'796 (Feldman) proposes the use of a Palladium Silicide material as a catalytic material for electroless plating reactions. US 5,169,680 (Ting) proposes the use of electroless plating to make metal conductors US 5,183,795 (Ting) proposes the use of electroless plating with selective deposition characteristics to produce copper metal wires. U S 5, 5 6 2, 7 6 0 (B a 1 1 a r d), u S 4, 2 6 5, 9 4 3 (Goldstein) discuss the process of electroless metal deposition. 1 ^ [^ et al.]. 圧 1 €€ 1: 1: 0 (: 116 «1.8〇 <:., Vol. 136 (1 9 89) Issue 2, pages 462-466 published" Selective electroless metal deposition for via hole filling in VLSI multi level interconnect ion structures, discusses the deposition technology of electroless metal.
Laptin 等人於 1997 VMIC conference p. 219 至p. 224 發表 “Selective.electroless CoWP deposition onto Pd-activated in-laid Cu lines” 討論無電錄金屬的 沉積技術。 發明的綜合說明Laptin et al. Published a "Selective.electroless CoWP deposition onto Pd-activated in-laid Cu lines" at the 1997 VMIC conference p. 219 to p. 224 to discuss electroless metal deposition techniques. Comprehensive description of the invention
D:\patent\nbs\870040.ptd 第13頁 4ίΐ56Β 五、發明說明（11) 本發明案的目的是提供一個利用無電鍍技術於積體電 路上製作銅金屬導線的方法。 本發明案的目的是提供一個利用無電鍍技術於積體電 路上製作多層銅金屬連接導線的方法。 本發明案的另一目的是提供一個於第一金屬導線層及 第二導線層間的導通孔的製作方法。 為了達到上述所提的多項目的，本發明案提供了三種 利用無電鍍技術製作金或銅接點以及連接導線，這三種製 程技術皆分別提出不同的附著層材料以及擴散障礙層，以 作為製作銅或金栓塞用。本發明揭露出利用無電鍍製程於 超大型積體電路中製作電路的技術，此金屬化層是屬於加 成（additive)的製程，及選擇性沉積的製程，以完成多層 金屬導線間及與矽晶片元件間的連接導線結構。 第一種製程是指使用鎳、鈀、複晶矽或者是矽化鈀 (PdSix)作為附著層材料，而擴散障礙層材料為鎳-硼合金 (Ni-B)、鎳、鈀或者是鈷金屬，另外還利用無電鍍選擇 性沉積銅或金於第一金屬層與第二金屬層間的導通孔。第 一種製程的描述如下： 於絕緣層（20)上製作接觸孔（24)至基板（10)表面，此 接觸孔的側壁皆是絕緣層材料。 沉積附著層（2 8 )材料於接觸孔（2 4 )的絕緣層侧壁，以 及絕緣層底部所露出的基板表面上，此附著層的材料可以 是鋁、鋁合金、複晶矽、鎳以及非晶質矽。 第一擴散障礙層（34)材料可以利用無電鍍技術沉積於D: \ patent \ nbs \ 870040.ptd Page 13 4 ΐ56Β 5. Description of the invention (11) The purpose of the present invention is to provide a method for making copper metal wires on an integrated circuit by using electroless plating technology. The object of the present invention is to provide a method for manufacturing multilayer copper-metal connecting wires on an integrated circuit by using electroless plating technology. Another object of the present invention is to provide a method for manufacturing a via hole between a first metal wire layer and a second wire layer. In order to achieve the above-mentioned multiple items, the present invention provides three types of electroless plating technology for making gold or copper contacts and connecting wires. These three process technologies respectively propose different adhesion layer materials and diffusion barrier layers for production. For copper or gold embolization. The invention discloses a technique for making a circuit in an ultra-large integrated circuit by using an electroless plating process. The metallization layer is an additive process and a selective deposition process to complete the multilayer metal wire and the silicon Structure of connecting wires between chip components. The first process refers to using nickel, palladium, polycrystalline silicon or palladium silicide (PdSix) as the material of the adhesion layer, and the material of the diffusion barrier layer is nickel-boron alloy (Ni-B), nickel, palladium or cobalt metal In addition, electroless plating is used to selectively deposit copper or gold vias between the first metal layer and the second metal layer. The first process is described as follows: A contact hole (24) is formed on the insulating layer (20) to the surface of the substrate (10), and the sidewalls of the contact hole are all made of the insulating layer material. Deposit the material of the adhesion layer (2 8) on the sidewall of the insulation layer of the contact hole (2 4) and the substrate surface exposed at the bottom of the insulation layer. The material of the adhesion layer may be aluminum, aluminum alloy, polycrystalline silicon, nickel, and Amorphous silicon. The material of the first diffusion barrier layer (34) can be deposited on
D:\patent\nbs\870040. ptd 第14頁 ^αΐ56ϋ 五、發明說明（12) 附著層（28)之上，第一擴散障礙層的材料可以是鎳、鈀、 姑、和其合金。 利用含有氣化鈀的溶液來活化第一擴散障礙層材料_的 表面。 第一金屬導線層（38)是使用無電鍍技術具有選擇性沉 積的特性，沉積銅或金等金屬層於第一擴散障礙層之上， 並且將接觸孔（2 4 )填滿。 製作第二絕緣層（42)於第一金屬層之上。 於第二絕緣層（42)之上製作導通孔（44)，且此導通孔 的製作方式是蝕刻第二絕緣層至第一金屬層的表面。 沉積第二擴散障礙層（46)材料於第一金屬層之上，此 第二擴散障礙層材料可以是鎳、鈷、或鈀金屬》 利用含有氣化鈀的溶液來活化第二擴散障礙層材料的 表面。 利用無電鍍選擇性沉積的特性沉積第二金屬層於第二 擴散障礙層上，並填滿導通孔（44)，此第二金屬層材料可 以是金或者是銅金屬。 第二種製程和第三種製程與第一種製程的差異在於附 著層及擴散障礙層材料的成份。 本發明案主要是揭露出一種可以利用無電鍍具有選擇 性沉積的特性，開發出於導體或非導體之上製作金屬連接 導線結構的製程，假如底層材料表面不具催化特性時，即 須要在底層表面沉積一附著層材料，或者是對其表面施以 活化處理。D: \ patent \ nbs \ 870040. Ptd page 14 ^ αΐ56ϋ 5. Description of the invention (12) Above the adhesion layer (28), the material of the first diffusion barrier layer may be nickel, palladium, silicon, and alloys thereof. A solution containing vaporized palladium is used to activate the surface of the first diffusion barrier material. The first metal wire layer (38) is selectively deposited using an electroless plating technique. A metal layer such as copper or gold is deposited on the first diffusion barrier layer, and the contact holes (2 4) are filled. A second insulating layer (42) is formed on the first metal layer. A via hole (44) is formed on the second insulating layer (42), and the manufacturing method of the via hole is to etch the second insulating layer to the surface of the first metal layer. Depositing a second diffusion barrier layer (46) material on top of the first metal layer, the second diffusion barrier layer material may be nickel, cobalt, or palladium. The second diffusion barrier layer material is activated by using a solution containing vaporized palladium. s surface. The second metal layer is deposited on the second diffusion barrier layer by using the characteristic of electroless selective deposition and fills the vias (44). The material of the second metal layer may be gold or copper metal. The second and third processes differ from the first process in the composition of the adhesion layer and the diffusion barrier material. The present invention mainly discloses a process that can use electroless plating with selective deposition characteristics to develop a process for making a metal connection wire structure on a conductor or non-conductor. If the surface of the underlying material does not have catalytic properties, it must be on the underlying surface An adhesion layer material is deposited or the surface is subjected to activation treatment.
D:\patent\nbs\870040.ptd 第15頁 4U569 五、發明說明（13) 本發明案的其他目的及優點會於後續的製程描述中加 以說明，也可經由本發明案的申請專利範圍中瞭解本發明· 案的真正精神。 ’ 圖式的簡單說明 照著本發明案中所提出的半導體元件的製程特性及優 點，以及半導體元件的詳細製作流程，均會用下面的圖來 加以說明。 圖1至圖9是本發明案中所提出第一種製程中第一種選 擇的橫戴面圖，主要是利用無電鍍沉積技術製作金屬連接 導線。 圖10至圖11是本發明案中所提出第一種製程中第二種 選擇的橫戴面圖，此製程是利用無電鍍選擇性沉積的技術 以製作金屬連接導線，以完成多層金屬導線的連接結構。 圖 12、13、14 ' 15、16、17Α、18Α、19Α、20Α 是本發 明案中提出第二種製程的橫截面圖，此製程是利用無電鍍 選擇性沉積的特性，製作出金屬連接導線結構。 圖 12、13、14、15、16、17Β、18Β、19Β、20Β是本發 明案中提出第三種製程的橫截面圖，此製程是利用無電鍍 選擇性沉積的特性，製作出多層金屬，並完成多層導線連 接結構。 發明的較佳實施例 本發明案所提出的製程，均會配合橫截面圖來加以說D: \ patent \ nbs \ 870040.ptd Page 15 4U569 V. Description of the invention (13) Other objects and advantages of the present invention will be described in the subsequent description of the process, and may also be included in the scope of the patent application for the present invention Learn the true spirit of this invention. A brief description of the drawings According to the process characteristics and advantages of the semiconductor device proposed in the present invention, and the detailed manufacturing process of the semiconductor device, the following drawings will be used to explain it. Figures 1 to 9 are cross-sectional views of the first option in the first process proposed in the present invention, which is mainly used to make metal connection wires using electroless deposition technology. 10 to 11 are cross-sectional views of the second option in the first process proposed in the present invention. This process uses electroless selective deposition technology to make metal connection wires to complete multilayer metal wires. Connection structure. Figures 12, 13, 14 '15, 16, 17, 17A, 18A, 19A, and 20A are cross-sectional views of a second process proposed in the present invention. This process uses the characteristics of electroless selective deposition to produce metal connection wires. structure. Figures 12, 13, 14, 15, 16, 17B, 18B, 19B, 20B are cross-sectional views of a third process proposed in the present invention. This process uses the characteristics of electroless selective deposition to produce multilayer metals. And complete the multilayer wire connection structure. Preferred Embodiments of the Invention The processes proposed in the present invention will be described with reference to cross-sectional views.
D:\patent\nbs\870040. ptd 第16頁 五、發明說明（14) 明如何利用無電鍍選擇性沉積的技術，於積體電路上製 作多層金屬導線結構。 為了更詳細的說明本發明案的内容，所以在陳述本發 明案的内容時，也會針對製程的條件，例如流速、壓力、 溫度、濃度等加以說明。對於熟悉此領域的人而言，即使 沒有這些條件的說明，也會明瞭本發明案的基本精神。 本發明案中所提及的一般元件的製程，皆是已量產化 的技術，所以可於一般書籍或者是技術文獻中獲得這些資 料。為了要讓大家對本發明案有更進一步的認識，我們會 以現有的製程為基礎來加以說明，使得已經熟悉此領域的 人，可以更加瞭解本發明案的精神。 製程一-方法一-金屬導線與矽晶片的連接 圖1至圖9是本發明案中所提出的第一種製程的橫載面 圖，利用無電鍍選擇性沉積的特性製作金屬連接導線。製 程一中有提出兩種方法，其中方法一為矽晶片形成接點的 技術（見圖9)，而方法二是於矽晶片上形成一接點，以及 導線金屬層（38A)(見圖11)。 圖1是指於基板（10)上製作出接觸孔（24)，此接觸孔 的製作方式是利用蝕刻方式，蝕刻絕緣層至矽晶片的的表 面，所以接觸孔的側壁為絕緣層材料。 此基板（10)是半導體材料，可以是矽晶片、砷化鎵或 其它瓜-V化合物半導體。D: \ patent \ nbs \ 870040. Ptd page 16 5. Description of the Invention (14) Explains how to use electroless selective deposition technology to make multilayer metal wire structures on integrated circuits. In order to explain the content of the present invention in more detail, when describing the content of the present invention, the conditions of the process, such as flow rate, pressure, temperature, concentration, etc. will also be described. For those skilled in the art, the basic spirit of the present invention will be clear even without explanation of these conditions. The manufacturing processes of the general components mentioned in the present invention are all mass-produced technologies, so these materials can be obtained in general books or technical literature. In order to let everyone have a further understanding of the present invention, we will explain based on the existing process, so that those who are already familiar with this field can better understand the spirit of the present invention. Process 1-Method 1-Connection of Metal Wire to Silicon Wafer Figures 1 to 9 are cross-sectional views of the first process proposed in the present invention. Metal connection wires are made using the characteristics of selective deposition by electroless plating. There are two methods proposed in process one, one of which is a technique for forming contacts on a silicon wafer (see FIG. 9), and the second method is to form a contact on the silicon wafer and a wire metal layer (38A) (see FIG. 11) ). Figure 1 refers to a contact hole (24) made on a substrate (10). This contact hole is manufactured by etching the insulating layer to the surface of the silicon wafer. Therefore, the sidewall of the contact hole is an insulating layer material. The substrate (10) is a semiconductor material, and may be a silicon wafer, gallium arsenide, or other melon-V compound semiconductor.
D:\patent\nbs\870040, ptd 第17頁 411569_ 五、發明說明（15) 表一：製程一^的結論-圖1至圖9 100 囷I -於絕緣層(20)上製作一接觸孔(24)，利用蝕刻方式蝕刻此絕緣層， 直到基板為止，所以接觸孔的側壁皆是絕緣層材料； 110 圖2、圖3、圖4 -沉積一附著層(28)於接觸·?1的側壁及底部，此附著 層材料可以是鋁、鋁合金、複晶矽、鎳、鈦'以及非晶矽等； 120 圖5 -無電鍍沉積-製作第一擴散障礙層(34)於附著層(28)之上，此第 一擴散障礙層(34)材料可以是鎳、鈷、鈀以及其合金材料； 130 使用含有氱化鈀的溶液活化第一擴散障礙層(34)的表面； 140 圖5 -利用無電鍍選擇性沉積的特性，沉積第一金屬層(38)，於第一擴 散障礙層(34)之上，並填滿接觸孔，此第一金屬層(38)材料可以是銅、 金或其合金； 150 圖6-製作第二絕緣層(42)於第一絕緣層之上； 160 圖7 -將第二絕緣層(42)圖案化以形成導通孔(44),在製作導通孔時， 須蝕刻第二絕緣層(42)至第一金屬層(38)上； 170 闽8 - >儿積第一擴散障礙層(46)於第一金屬層(38)上，此第二擴散障礙 _層(46)材料可以是鎳、鈷、纪以及其合金材料； 180 用含有氣化纪的〉谷液，活化第二擴散障礙層(46)的裊面； 190 Ϊ ^二、利用無電链選擇性沉積的特性，沉積第二金屬層(50)，於第一i 之上，並填滿導通孔(44)，此第二金屬層(50)材料可以是銅、金 1___1 D:\patent\nbs\870040. ptd 第 18 頁 _ 五、發明說明（16) 表二：第一種製程的主要步驟-方法一-圖1至圖9 ί 層 次 材料及組成 不同材料/製程 50 第二無電鍍金屬層（金屬 II) 銅 銅或金 46 第二擴散障礙層 錄-蝴 鎳、鈀或鈷 38 第一無電鍍金屬層 銅 銅或金 34 第一擴散障礙層 厚度約200nm 鎳、鈀或鈷 28 附著層 鎳金屬層，厚度 約為50nm 鋁'鋁合金、非晶質矽、 複晶碎、欽、夕化赵 10 基板 矽 砷化鎵 圖2、圖3和圖4是顯示出於接觸孔（24)的絕緣層（20) 的側壁及絕緣層的底部沉積出第一附著層（2 8 )材料，圖2 是顯示的是沉積附著層材料的步驟，圖3是指利用光阻 (32)在附著層上製作出圖案，圖4是指將附著層蝕刻出預 定的圖案，且將光阻層（32)去除。 此附著層材料可以是鋁、鋁合金、複晶矽 '鎳、鈦或 非晶質矽，而以鋁、鋁合金或複晶矽較為適合，此附著層 的厚度大約在40至60nm(目標值為50nm)，此附著層材料的 製作方式可以利用濺鍍、蒸鍍或化學汽相沉積製程，依其 特性可以歸類為：鋁或鋁合金可以利用濺鍍方式；鎳合 金、無電鍍鎳合金或鈦金屬可以利用無電鍍或濺鍵製程： 而複晶矽或非晶矽可以利用化學汽相沉積方式沉積。 圖5是指於附著層（28)之上沉積第一擴散障礙層 (34)，此第一擴散障礙層（34)材料為鎳、鈀或鈷或其合D: \ patent \ nbs \ 870040, ptd page 17 411569_ 5. Description of the invention (15) Table 1: Conclusion of process 1 ^-Figures 1 to 9 100 囷 I-Making a contact hole in the insulating layer (20) (24) Etching this insulating layer by etching until the substrate, so the sidewalls of the contact holes are all insulating layer materials; 110 Figure 2, Figure 3, Figure 4-Depositing an adhesion layer (28) on the contact Side wall and bottom, the material of this adhesion layer can be aluminum, aluminum alloy, polycrystalline silicon, nickel, titanium 'and amorphous silicon, etc. 120 Figure 5-Electroless Plating-Making the first diffusion barrier layer (34) on the adhesion layer ( 28), the material of the first diffusion barrier layer (34) may be nickel, cobalt, palladium and alloy materials thereof; 130 the surface of the first diffusion barrier layer (34) is activated by using a solution containing tritium palladium; 140 FIG. 5 -Using the characteristics of electroless selective deposition, a first metal layer (38) is deposited on the first diffusion barrier layer (34) and fills the contact hole. The material of the first metal layer (38) may be copper, Gold or its alloy; 150 Figure 6-Making a second insulating layer (42) on top of the first insulating layer; 160 Figure 7-Patterning the second insulating layer (42) Forming a via hole (44), when making the via hole, the second insulating layer (42) must be etched onto the first metal layer (38); 170 Min 8-> The first diffusion barrier layer (46) is formed on the first On a metal layer (38), the material of the second diffusion barrier layer (46) may be nickel, cobalt, metal, and alloy materials thereof. 180 The second diffusion barrier layer (46) is activated with a valley fluid containing gasification period> ); 190 ^ ^ Second, the second metal layer (50) is deposited on top of the first i, and the via (44) is filled with the second metal layer ( 50) The material can be copper or gold 1___1 D: \ patent \ nbs \ 870040. Ptd page 18_ 5. Description of the invention (16) Table 2: The main steps of the first process-method 1-Figure 1 to Figure 9 ί Hierarchical materials and composition of different materials / processes 50 Second electroless metal layer (Metal II) Copper Copper or Gold 46 Second diffusion barrier layer-Butterfly nickel, palladium or cobalt 38 First electroless metal layer copper copper or gold 34 No. A diffusion barrier layer having a thickness of about 200 nm, nickel, palladium or cobalt. An adhesion layer of a nickel metal layer, having a thickness of about 50 nm. Aluminum 'aluminum alloy, amorphous silicon, polycrystalline flakes, , Xihua Zhao 10 Substrate gallium arsenide Figures 2, 3 and 4 show a first adhesion layer (2 8) deposited on the side wall of the insulating layer (20) out of the contact hole (24) and the bottom of the insulating layer. Figure 2 shows the steps of depositing the material of the adhesion layer. Figure 3 refers to the use of photoresist (32) to make a pattern on the adhesion layer. Figure 4 refers to the etching of the adhesion layer to a predetermined pattern and the photoresist. Layer (32) is removed. The material of the adhesion layer may be aluminum, aluminum alloy, polycrystalline silicon, nickel, titanium, or amorphous silicon. Aluminum, aluminum alloy, or polycrystalline silicon is more suitable. The thickness of the adhesion layer is about 40 to 60 nm (target value). 50nm), the method of making this adhesion layer material can use sputtering, vapor deposition or chemical vapor deposition processes, which can be classified according to their characteristics: aluminum or aluminum alloys can be used for sputtering; nickel alloys, electroless nickel alloys Or titanium metal can be processed by electroless plating or sputtering: while polycrystalline silicon or amorphous silicon can be deposited by chemical vapor deposition. FIG. 5 refers to depositing a first diffusion barrier layer (34) on the adhesion layer (28). The material of the first diffusion barrier layer (34) is nickel, palladium or cobalt or a combination thereof.
D:\patent\nbs\870040. ptd 第19頁 411569 五、發明說明C17) 金，但是實際應用上，不限定只能使用這三種材料，擴散 障礙層材料的厚度約為180至220nm(目標值為200nm)，此 擴散障礙層材料的沉積方式可以使用物理汽相沉積、化學 汽相沉積、無電鍍或蒸鍍等製程，而以無電鍍製程最為適 合，擴散障礙層的主要目的是阻止導線金屬的擴散。 於第一金屬層沉積之前須先利用含有氣化鈀的溶液， 使擴散障礙層的表面具有催化性。 此擴散障礙層（3 4 )沉積於接觸孔（2 4 )的底部及側壁。 表三：無電鍍鎳溶液成份 範圍(g/L) 目標值(g/L) Nickel sulphate 28-32 30 Dimethylamine borane (DMAB) 2.8-3.2 3.0 Sodium citrate 25-35 30 Ammonium chloride 28-32 30 Temperature (°C) 58-62 60 pH value 5.9-6.1 6.0 表四：無電鍍鈷溶液成份 範圍(g/L) 目標值(g/L) Cobalt sulphate 19-21 20 Sodium hypophosphite 10.5-11 10.7 Sodium citrate 55-60 58 Ammonium chloride 70-80 75 Temperature (°C) 88-92 90 PH value 6.7-7.1 7.0D: \ patent \ nbs \ 870040. Ptd Page 19 411569 V. Description of the invention C17) Gold, but in practice, it is not limited to these three materials. The thickness of the diffusion barrier material is about 180 to 220 nm (target value) 200nm). The diffusion barrier material can be deposited by physical vapor deposition, chemical vapor deposition, electroless plating, or evaporation processes. The electroless plating process is most suitable. The main purpose of the diffusion barrier layer is to prevent wire metal. Proliferation. Before the first metal layer is deposited, a solution containing vaporized palladium must be used to make the surface of the diffusion barrier layer catalytic. The diffusion barrier layer (3 4) is deposited on the bottom and sidewalls of the contact hole (2 4). Table 3: Composition range of electroless nickel solution (g / L) Target value (g / L) Nickel sulphate 28-32 30 Dimethylamine borane (DMAB) 2.8-3.2 3.0 Sodium citrate 25-35 30 Ammonium chloride 28-32 30 Temperature ( ° C) 58-62 60 pH value 5.9-6.1 6.0 Table 4: Composition range of electroless cobalt solution (g / L) Target value (g / L) Cobalt sulphate 19-21 20 Sodium hypophosphite 10.5-11 10.7 Sodium citrate 55- 60 58 Ammonium chloride 70-80 75 Temperature (° C) 88-92 90 PH value 6.7-7.1 7.0
D:\patent\nbs\870040.ptd 第 20 頁 411569 五、發明說明（18) 表五：無電鍍鈀溶液成份 範圍(g/L) 目標值(g/L) Palladium chloride 28-32 30 Sodium hypophosphite 7.2-7.8 7.5 Sodium citrate 65-80 72 Ammonium chloride 45-50 48 pH value 9.9-10.1 10 圖6是指利用無電鍍技術沉積第一金屬層（38)於第一 擴散障礙層（34)之上，並填滿接觸孔（24)，第一金屬層材 料可以是金或銅，而以鋼最適合，但如果是神化嫁或者是 皿-v化合物半導體的話，以金導線最為適合。本發明案中 第一金屬層材料是以無電鍍方式沉積銅金屬導線，下表是 將無電鍍銅溶液成份以及製程作一整理： 表六：無電鍍銅溶液成份 範圍(g/L) 目標值(g/L) Copper sulphate 6-7 6.5 Sodium citrate 15-15,8 15.4 Nickel sulphate 0.4-0.6 0.5 Sodium hypophosphite 10-11 10.5 Boric acid 4.5-5.5 5.0 Temperature (°C) 62-68 65 pH value 9.0 - 9.3 9.2D: \ patent \ nbs \ 870040.ptd Page 20 411569 V. Description of the invention (18) Table 5: Composition range of electroless palladium solution (g / L) Target value (g / L) Palladium chloride 28-32 30 Sodium hypophosphite 7.2-7.8 7.5 Sodium citrate 65-80 72 Ammonium chloride 45-50 48 pH value 9.9-10.1 10 Figure 6 refers to the use of electroless plating technology to deposit the first metal layer (38) on the first diffusion barrier layer (34). The contact hole (24) is filled. The material of the first metal layer may be gold or copper, and steel is most suitable. However, if it is a deity or a v-v compound semiconductor, a gold wire is most suitable. In the present invention, the first metal layer material is a copper metal wire deposited by electroless plating. The following table summarizes the composition and process of the electroless copper solution: Table 6: Target range of the electroless copper solution component (g / L) (g / L) Copper sulphate 6-7 6.5 Sodium citrate 15-15,8 15.4 Nickel sulphate 0.4-0.6 0.5 Sodium hypophosphite 10-11 10.5 Boric acid 4.5-5.5 5.0 Temperature (° C) 62-68 65 pH value 9.0- 9.3 9.2
411569 五、發明說明（19) 此無電鍍銅溶液是利用次磷酸鈉作為還原劑，取代傳 統使用甲醛作為還原劑的溶液，這是本發明案中一相當重_ 要的創新。 利用無電鍍銅的技術可以將具有高方向比的導通孔填 滿金屬，並製作出銅金屬導線，由於無電鍍銅具有選擇性 沉積的優點，所以不必進行銅的乾蝕刻步驟，此點也是本 發明案中相當重要的創新。 表七是將無電鍍金溶液成份及其製程作一整理。 表七：無電鍍金溶液成份 範圍(g/L) 目標值(g/L) Gold potassium cyanide 1.8-2.2 2.0 Sodium hypophosphite 9.5-10,5 10 Sodium citrate 45-55 50 Ammonium chloride 70-80 75 Temperature (°C) 88-92 90 pH value 6.9-7.1 7.0 本發明案中所提出的利用無電鍍法製作金或銅金屬導 線於擴散障礙層之上，如前所述，如果擴散帳礙層材料為 鎳、鈷或鈀材料的話，會得到較佳的結果。 圖6是指沉積第二絕緣層（I LD層）（4 2 )於第一絕緣層 上，此第二絕緣層的材料最好是二氧化矽》 圖7是指製作導通孔於第二絕緣層（4 2 )上，此導通孔 是先利用光阻製作好圖案後，再利用蝕刻方式蝕刻第二絕411569 V. Description of the invention (19) This electroless copper plating solution is a solution using sodium hypophosphite as a reducing agent instead of the traditional solution using formaldehyde as a reducing agent, which is a very important innovation in the present invention. The technology of electroless copper plating can be used to fill the vias with a high aspect ratio with metal and produce copper metal wires. Since electroless copper has the advantage of selective deposition, it is not necessary to perform a copper dry etching step. This is also the present invention The most important innovation in the case. Table 7 summarizes the composition and process of the electroless gold solution. Table 7: Composition range of electroless gold solution (g / L) Target value (g / L) Gold potassium cyanide 1.8-2.2 2.0 Sodium hypophosphite 9.5-10,5 10 Sodium citrate 45-55 50 Ammonium chloride 70-80 75 Temperature ( ° C) 88-92 90 pH value 6.9-7.1 7.0 In the present invention, the electroless plating method is used to make gold or copper metal wires on the diffusion barrier layer. As mentioned above, if the material of the diffusion barrier layer is nickel For cobalt, cobalt or palladium, better results will be obtained. FIG. 6 refers to depositing a second insulating layer (I LD layer) (4 2) on the first insulating layer. The material of this second insulating layer is preferably silicon dioxide. ”FIG. 7 refers to making a via hole on the second insulating layer. On the layer (4 2), this via is first patterned by photoresist, and then the second insulation is etched by etching.
D：\patent\nbs\870040.ptd 第22頁 411569__ 五、發明說明（20) 緣層至第一金屬層的表面為止。 在此製程中，圖10所示的是指導通孔的尺寸比第一金 屬層（38 )的尺寸來得大，且會有部份的第二絕緣層露出。 另外，活化第一金屬層表面以利後續無電鍍製程進行的活 化步驟，是以含有氣化鈀的活化液最為適合其他的活化液 也可以利用含有氫氟酸的溶液進行活化步驟，此步驟也包 括了酸鹼洗的程序。 圖8是指於第一金屬層（38)上利用無電鍍法沉積一擴 散障礙層（也就是第二擴散障礙層），此第二擴散障礙層的 材料可以是鎳-硼、鈀或者是鈷。如果以銅或金作為導線 金屬材料時，則以鎳-硼為最佳的擴散障礙層材料。無電 鍍鎳-硼鍍層的沉積方式是於無電鍍鎳的溶液中添加一些 微量的含硼化合物，無電鍍鎳-硼鍍層具有較低的阻值。 接著，如圖9所示，製作第二金屬層（50)於第二擴散障礙 層（4 6 )之上，並且填滿導通孔（4 4 )。 第二金屬層於第二絕緣層上的橫向成長的距離，可以 經由沉積的時間來決定。 最適宜的第二金屬層材料是銅或金，且最適合的製程 與第一金屬層相同的利用具選擇性沉積的無電鍍技術。 第一種製程中較重要的製程步驟整理於下表。D: \ patent \ nbs \ 870040.ptd page 22 411569__ 5. Description of the invention (20) The edge layer is up to the surface of the first metal layer. In this process, FIG. 10 shows that the size of the guide via is larger than that of the first metal layer (38), and a part of the second insulating layer is exposed. In addition, the activation step for activating the surface of the first metal layer to facilitate the subsequent electroless plating process is an activation solution containing vaporized palladium which is most suitable for other activation solutions. The activation step can also be performed using a solution containing hydrofluoric acid. Includes the procedure of acid and alkali washing. FIG. 8 refers to depositing a diffusion barrier layer (ie, a second diffusion barrier layer) on the first metal layer (38) by electroless plating. The material of the second diffusion barrier layer may be nickel-boron, palladium, or cobalt. . If copper or gold is used as the wire metal material, nickel-boron is the best material for the diffusion barrier layer. The electroless nickel-boron plating is deposited by adding a trace amount of a boron-containing compound to an electroless nickel plating solution. The electroless nickel-boron plating has a low resistance value. Next, as shown in FIG. 9, a second metal layer (50) is formed on the second diffusion barrier layer (4 6), and the via hole (4 4) is filled. The lateral growth distance of the second metal layer on the second insulating layer can be determined by the deposition time. The most suitable material for the second metal layer is copper or gold, and the most suitable manufacturing process is the same as that of the first metal layer using selective electroless plating technology. The more important process steps in the first process are summarized in the table below.
D:\patent\nbs\870040.ptd 第 23 頁 411569 五、發明說明（21) 表八：第一種製程中的重要步驟-方法一 步驟/層次 圖 原 因說明 120 4 附著層以及擴散障礙層的沉積 130 5 利用無電鍍法沉積第一金屬層(金或銅導線） 8&9 第二擴散障礙層(46)和第二金屬層(50)的沉積 金步 礙程 障製 散些 擴這 用 -應。 作以線 製可導 式們屬 方我金 鑛。層 電構多 無結作 用線製 利導中 是接路 程連電 製銅體 種及積 一以型 第料大 此材超 層到 屬驟 法 方 - 程 製 種- 第 以 可 時 屬 金 點 接 積 沉 於 是 術-1 技ο -—< 種圖 一見 另， 中線 程導 製屬 種金 一作 第製 起 中 ο 11 圖 在 層 面 表 的 緣 絕 的 D 孔 通 導 近 靠 於 積 沉 8 2 1 C圖 層在 著4 附. 板 基 中 IX 和 到 觸 接 是 以 可 沉形 上及 層以 緣孔 絕觸 的接 口滿 開填 >孔並 D i \—/ L 4 I導3 c. C. 層近層 電靠礙 介於障 的們散 間我擴 屬，於 金示} 8 是所(3 者11層 或圖屬 片如金 晶 一 矽 第 層 線 導 屬 金- 第 著 附 於 作 製 的 次 層 些 這 上 之 述 所 前 如 序 程 及 法 方 接 的 大 太 要 需 不 是 點 優 大 最 的 2 法 方 程 製 F< 種 1 第 此 密 的 積 gl、 件 元 加 增 以 件 元 的 件 元 小 縮 以 可 以 所 孔 觸 度 第二種製程-以PdSix作為附著層 圖12-16及圖17A、18A、19A和20A是第二種製程的製D: \ patent \ nbs \ 870040.ptd Page 23 411569 V. Description of the invention (21) Table 8: Important steps in the first process-Method 1 Step / hierarchical reason 120 4 The adhesion layer and the diffusion barrier layer Deposition 130 5 The first metal layer (gold or copper wire) is deposited by electroless plating. 8 & 9 The second diffusion barrier layer (46) and the second metal layer (50) are deposited with gold. -should. Guided by the line are our gold mines. The multi-layer structure of the multi-junction-free action line is guided by a series of electrically connected copper bodies and materials. This material is a super layer to the genus. The technique of accumulating and sinking -1 technique ο -— < see the other picture, the middle thread guide genus of gold is the first system to start ο 11 picture in the level table of the D-hole access close to the accumulation of 8 2 1 C layer is attached in 4. At the base of the board, IX and the contact are filled with a sinkable upper layer and the layer is completely filled with an edge hole. The hole is filled with D i \ — / L 4 I Guide 3 c C. The layer near the electrical barriers are interspersed with the barriers. I expand the genus, and the gold display} 8 is the place (3 of 11 layers or graphic films such as gold crystal and silicon. In the second layer of the system, the above-mentioned predecessors and the traditional method must be not the best and the best 2 method of the equation F < Kind 1 The dense product gl, the number of elements is increased by the number of elements The element size is reduced to the second process that can be touched-using PdSix as the adhesion layer. Figure 12-16 and Figures 17A, 18A, 19A, and 20A are the processes of the second process
D:\patent\nbs\870040, ptd 第24頁 411569__ 五、發明說明（22) 作流程的橫截面圖。 下表是第二種製程中所提供的無電鍍沉積技術，以製 作金屬連接導線結構的流程。 表九：第二種製程的詳細步驟 步驟 製 程描述 圖12-製作一絕緣層(12〇、於基板⑽上； 200 圖1心利用光阻層(124)於絕緣層(120)之上製作出圖案； 210 圖12-利用蝕刻方式製作一接觸孔(128)於絕緣唐（12〇)上，此丛觸孔 須與基板表面元件的導電層相連； 220 圖12-’，儿積第一活化層(m)於接觸孔(128)中的底部(基材的表面），此 第一活化層的沉積方式是將基板浸入含有氮化鈀的溶液中； 230 圖13&14-製作一薄鈀金屬層（136)於第一活化層之上，此鈀金屬層的 沉積方式可以利用無電鍍或激嫂方式進行； 240 將晶片表面的光阻去除； - 250 圖15-進行熱退火處理，使接觸孔中與矽基板接觸的鈀金屬反應生成 矽化鈀(140)材料層； 260 圖16-製作一擴散障礙層〇44)於石夕化鈀層之上，此擴散障礙層的材料 可以是鎳、鈀、鈷或其合金較為適合； 270 圖16-利用無電鍍技術沉積第一金屬層(148)於擴散障礙層之上，並填 滿接觸孔，此第一金屬層(148)的材料是金或銅材料； 280 圖17A-製作一複晶矽(152)廣於第一金屬層之上； 290 圖18A->冗積一鈀金屬層(153)於複晶矽層（152)上，此鈀金屬層可以使 用無電鍍或激鍵方式製作： 292 圖18A-進行退火熱處理，使得把金屬層(153)與複晶矽(152)層能生成 矽化鈀(PdSix)(156)材料； 294 圖19A-製作第二絕緣層(158)於第一絕緣層之上，第二絕緣層中須製 作出導通孔，此導通孔須與接觸孔對齊，且此導通孔的製作須蝕刻 第二絕緣層至氣化鈀(156)的表面； 296 圖20A-利用無電鍍製程具有選擇性;冗積的特性，沉積第二金屬層(16〇) 於第一金屬層上並填滿導通孔，第二金屬層（16〇)材料為金或銅。D: \ patent \ nbs \ 870040, ptd page 24 411569__ 5. Description of the invention (22) A cross-sectional view of the working process. The following table is the process of electroless deposition technology provided in the second process to make the metal connection wire structure. Table 9: Detailed steps of the second manufacturing process. Process description Figure 12- Fabrication of an insulating layer (120 on the substrate); 200 Figure 1 Fabrication of a photoresist layer (124) over the insulating layer (120) Pattern; 210 Figure 12-Etching a contact hole (128) on the insulating substrate (120) by etching. The contact hole of the cluster must be connected to the conductive layer on the surface of the substrate; 220 Figure 12- ', the first activation of the product The layer (m) is on the bottom of the contact hole (128) (the surface of the substrate). The first activation layer is deposited by immersing the substrate in a solution containing palladium nitride; 230 Figure 13 & 14-Making a thin palladium The metal layer (136) is on the first activation layer, and the palladium metal layer can be deposited by electroless plating or agitation; 240 removes the photoresist on the wafer surface;-250 Figure 15- The palladium metal contacting the silicon substrate in the contact hole reacts to form a palladium silicide (140) material layer; 260 Figure 16-Making a diffusion barrier layer (44) on top of the Shixihua palladium layer, the material of the diffusion barrier layer may be nickel , Palladium, Cobalt or their alloys are more suitable; 270 Figure 16-Using electroless plating The first metal layer (148) is on the diffusion barrier layer and fills the contact hole. The material of the first metal layer (148) is gold or copper material. 280 FIG. 17A-Making a polycrystalline silicon (152) is wider than Over the first metal layer; 290 Figure 18A-> A palladium metal layer (153) is superimposed on the polycrystalline silicon layer (152). This palladium metal layer can be fabricated by electroless plating or bonding: 292 Figure 18A- An annealing heat treatment is performed so that the metal layer (153) and the polycrystalline silicon (152) layer can generate a palladium silicide (PdSix) (156) material; 294 FIG. 19A-making a second insulating layer (158) on the first insulating layer A via hole must be made in the second insulating layer, the via hole must be aligned with the contact hole, and the fabrication of this via hole must etch the second insulating layer to the surface of the vaporized palladium (156); 296 Figure 20A-Using an electroless plating process It has the characteristics of selectivity and redundancy. A second metal layer (160) is deposited on the first metal layer and fills the vias, and the second metal layer (160) is made of gold or copper.
D:\patent\nbs\870040. ptd 第25頁 411569 五、發明說明（23) 下表是將第二種製程中，具關鍵的製程步驟作一整 理。 表十：第二種製程的關鍵步驟 層次 最佳組成或參數 不同材料或製程 160 第二金屬層 金或銅 156 PdSix PdSix 153 鈀 152 複晶$夕 148 第一金屬層 銅 144 擴散障礙層 厚度200nm 錄' 把、銘 140 石夕化ίε PdSix 鈀和複晶矽進行退火 熱處理 134 鈀 經由無電鍍方式或濺 鍍方式沉積 132 第一活化層 利用含Pd的溶液 10 基板 梦晶片 發明案中第二種製程是於矽晶片（10)上使用無電鍍沉 積技術製作金屬導線。 圖1 2是指形成絕緣層（1 2 0 )於基板（1 0 )上，此絕緣層 材料為二氧化矽、低溫氧化矽等，此絕緣層的厚度總合在 500至700nm之間（目標值為600nm)i a 圖12是指於第一絕緣層上製作出具有接觸孔圊案的光 阻層（1 2 4 )。 接著再利用蝕刻方式蝕刻絕緣層（1 2 0 )直到矽晶片的D: \ patent \ nbs \ 870040. Ptd page 25 411569 V. Description of the invention (23) The following table is a summary of the key process steps in the second process. Table 10: The key steps of the second process. The optimal composition or parameters of different layers or processes. 160 The second metal layer is gold or copper. 156 PdSix PdSix 153. Palladium. 152 Complex. $ 150. The first metal layer is copper. 144 The thickness of the diffusion barrier layer is 200 nm. Record ', Ming 140 Shi Xihua, εε PdSix Palladium and polycrystalline silicon are annealed and heat treated 134 Palladium is deposited by electroless plating or sputtering 132 The first activation layer uses a solution containing Pd The process is to produce metal wires on a silicon wafer (10) using electroless deposition technology. Figure 12 refers to the formation of an insulating layer (120) on the substrate (10). The material of this insulating layer is silicon dioxide, low temperature silicon oxide, etc. The thickness of this insulating layer is between 500 and 700nm (target The value is 600 nm) ia FIG. 12 shows that a photoresist layer (1 2 4) with a contact hole pattern is fabricated on the first insulating layer. Then, the insulating layer (120) is etched by etching until the silicon wafer
D:\patent\nbs\870040. ptd 第26頁 411569 五、發明說明¢24) 表面為止，所以此接觸孔的側壁皆是絕緣層材料。 圖1 2也顯示出利用含有氣化鈀的溶液，將接觸孔中所 露出的晶片表面進行活化，此步驟是將矽晶片浸入含有氣 化纪的活化液中完成。 而圖13及圖14是沉積一薄鈀金屬層於已活化的矽晶片 (132)表面，此鈀金屬層可以利用無電鍍或濺鍍方式進 行，此纪金屬層的厚度約為48至52nm(目標值為50nm)，下 表是無電鍍鈀的溶液组成。 表十一：無電艘把溶液成份 成 份 範圍(g/L) 目標值(g/L) Palladium chloride 28-32 30 Sodium hypophosphite 7.2 - 7.8 7.5 Sodium citrate 65-80 72 Ammonium chloride 45-50 48 pH value 9.9-10.1 10 相反的，鈀金屬層也可以利用濺鍍方式製作，如果鈀 金屬層是以濺鍍法製作，此矽晶片就不須如前所述的方式 活化其表面。 圖14是指將光阻層去除。 圖1 5是將矽晶片進行熱退火處理，所以在接觸孔裏的 石夕與把金屬層反應生成石夕化纪。 圖16是指於矽化鈀（140)層上沉積第一擴散障礙層 (144)，此擴散障礙層（144)材料以錦、姑、把或其合金最D: \ patent \ nbs \ 870040. Ptd page 26 411569 V. Description of the invention ¢ 24) The surface of the contact hole is made of insulating material. Fig. 12 also shows that the surface of the wafer exposed in the contact hole is activated by using a solution containing vaporized palladium. This step is completed by immersing a silicon wafer in an activation solution containing a vaporization period. 13 and FIG. 14 are a thin palladium metal layer deposited on the surface of the activated silicon wafer (132). The palladium metal layer can be performed by electroless plating or sputtering. The thickness of the metal layer in this period is about 48 to 52 nm ( The target value is 50 nm). The following table shows the composition of the electroless palladium solution. Table 11: The composition range (g / L) target value (g / L) Palladium chloride 28-32 30 Sodium hypophosphite 7.2-7.8 7.5 Sodium citrate 65-80 72 Ammonium chloride 45-50 48 pH value 9.9 -10.1 10 In contrast, the palladium metal layer can also be made by sputtering. If the palladium metal layer is made by sputtering, the surface of the silicon wafer need not be activated as described above. FIG. 14 refers to removing the photoresist layer. Figure 15 shows that the silicon wafer is thermally annealed. Therefore, Shi Xi in the contact hole reacts with the metal layer to form the Shi Xi chemical age. Figure 16 refers to the deposition of a first diffusion barrier layer (144) on a layer of palladium silicide (140). The material of the diffusion barrier layer (144) is
D:\patent\nbs\870040.ptd 第27頁 uii56y 五、發明說明（25) 為適合，但不以此為限，此第一擴散障礙層的厚度為180 至220nm(目標值為200nm) ° 圖16是指利用無電鍍方式製作第一金屬層（148)於撫 散障礙層（144)之上，此第二金屬層的材料是銅或金’奉 十二是無電鍍銅溶液的組成。 表十二：無電鍍鋼溶液的組成 範圍(g/L) 「目標值(g/L) Copper sulphate 6-7 6.5 Sodium citrate 15-15.8 15.4 Nickel sulphate 0.4-0.6 0.5 Sodium hypophosphite 10-11 10.5 Boric acid 4,5 — 5.5 5.0 Temperature (°C) 62-68 65 pH value 9.0-9.3 9.2 圖17A是指沉積一複晶矽（152)層於第一金屬層（148) 之上，此複晶矽的厚度約為28至32nm。 接著，圖18A是指一鈀金屬層（153)沉積於複晶矽 (152)之上，此沉積方式可以利用無電鍍或者是濺鍍方式 製作，此鈀金屬層的厚度約為48nm至52nm。 圖19A所示的是將晶片進行熱處理，使鈀金屬層與複 晶矽於第一金屬層上形成矽化把（156)。 圖19A顯示的是於第一絕緣層之上製作第二絕緣層 (1 5 8 )，在此第二絕緣層（I LD層）製作導通孔（1 59 )。此導 通孔須與接觸孔（1 2 8 )對齊’且此導通孔的製作須蝕刻第D: \ patent \ nbs \ 870040.ptd page 27 uii56y V. Description of the invention (25) is suitable, but not limited to this. The thickness of the first diffusion barrier layer is 180 to 220 nm (target value is 200 nm) ° FIG. 16 shows that the first metal layer (148) is fabricated on the fugitive barrier layer (144) by electroless plating, and the material of the second metal layer is copper or gold, and the composition is an electroless copper plating solution. Table 12: Composition range of electroless steel solution (g / L) "Target value (g / L) Copper sulphate 6-7 6.5 Sodium citrate 15-15.8 15.4 Nickel sulphate 0.4-0.6 0.5 Sodium hypophosphite 10-11 10.5 Boric acid 4,5 — 5.5 5.0 Temperature (° C) 62-68 65 pH value 9.0-9.3 9.2 Figure 17A refers to the deposition of a polycrystalline silicon (152) layer on the first metal layer (148). The thickness is about 28 to 32 nm. Next, FIG. 18A indicates that a palladium metal layer (153) is deposited on the polycrystalline silicon (152). This deposition method can be made by electroless plating or sputtering. The thickness is about 48nm to 52nm. Figure 19A shows that the wafer is heat-treated to form a silicide bar on the first metal layer with the palladium metal layer and the polycrystalline silicon (156). Figure 19A shows the first insulating layer. A second insulating layer (1 5 8) is fabricated on top, and a via hole (1 59) is made on this second insulating layer (I LD layer). This via hole must be aligned with the contact hole (1 2 8), and the via hole Etched
D:\patent\nbs\870040. ptd 第 28 頁 411569_ 五、發明說明（26) 二絕緣層至矽化鈀層（1 5 6 )之上。 圖20A顯示的是利用無電鍍方式沉積第二金屬層（160> 於第一金屬層之上，並填滿整個導通孔，此第二金屬層_的 材料以金或銅較為適合。 第二金屬層於第二絕緣層之上的侧向成長，可以經由 無電鍍的沉積時間來加以控制，此第二金屬層（1 6 0 )材料 以金或銅較為合適，但以銅為最佳的材料° 下表是將第二種製程的關鍵步驟做一整理： 表十三：第二種製程的關鍵步驟 步驟 圊 原因說 明 220 12 將矽(132)表面活化，但不會影響到氧化層的表面； 250 15 製作矽化鈀層作為附著層(136); 296 20A 第二金屬層-利用無電鍍製程製作金屬導線。 第三種製程-鋁或鈦作為附著層 本發明案中的第三種製程中第三種製程有鋁或鈦金屬 作為附著層（2 5 2 )。 此製程的主要步驟整理如下：D: \ patent \ nbs \ 870040. Ptd page 28 411569_ 5. Description of the invention (26) The second insulating layer is on the palladium silicide layer (156). FIG. 20A shows that a second metal layer (160>) is deposited on the first metal layer by electroless plating and fills the entire via hole. The material of the second metal layer is preferably gold or copper. Second metal The lateral growth of the layer above the second insulating layer can be controlled by the electroless deposition time. The material of the second metal layer (160) is more suitable for gold or copper, but copper is the best material. ° The following table is a summary of the key steps of the second process: Table 13: Key steps of the second process Steps Reason explanation 220 12 Activate the surface of silicon (132), but it will not affect the surface of the oxide layer 250 15 making a palladium silicide layer as an adhesion layer (136); 296 20A a second metal layer-using a non-electroplating process to make metal wires. A third process-aluminum or titanium as an adhesion layer in the third process of the present invention The third process has aluminum or titanium as the adhesion layer (2 5 2). The main steps of this process are as follows:
D:\patent\nbs\870040.ptd 第29頁 411569 五、發明說明¢27) 表十四：第三種製程的結論 步驟 原 因 300 圖12-製作二絕緣層(120)於基板(1〇)上：~ '- 310 圖13-於‘緣層（120)之上覆蓋光阻層（124)，並於此光阻層中 製作接觸孔的囷案； 320 圖12_姓刻絕緣層(120)至基板(10)表面，以製作接觸孔 330 圖12-製作一活化層（132)於曝露的基板(1〇)表面，此步驟是將 晶片浸入含有氣化le的溶液中完成； 340 圖丨3&I4-利用無電鍍法沉積鈀金屬層（136)於活化層之上，此 鈀金屬層除了可以利用無電鍍技術之外，也可以利用濺鍍方 式製作： 350 將光阻去除； 360 圖15-將晶片進行熱處理’使把金屬（136)與妙反應生成石夕化纪 (140)材料層於矽晶片上； 370 圖16-製作一擴散障礙層於矽化鈀(140)層之上，此擴散障礙層 材料以鎳、鈷、鈀或其合金最為適合； 380 圖16-利用無電鍍技術選擇性沉積第一金屬層(148)於擴散障礙 層(144)之上，此第一金屬層的材料可以是金或銅； 390 圖I7B-製作一附著層(252)於第一金屬層(148)之上，此附著層 (252)材料可以是鋁或鈦； 400 圖18B-沉積第二活化層(253)於附著層(252)上，此活化方式牙 以利用含有氣化鈀的溶液或鋅置換液進行； 410 圖19B-製作第二絕緣層(158)於第一絕緣層之上，此第二絕緣 層上有導通孔，此導通孔須蝕刻第二絕緣層至接觸孔附近， 且須與接觸孔對齊； 420 圖20B-利用無電鍍選擇性沉積第二金屬層(160)於第一金屬層 之上’且須填滿整個導通孔，此第二金屬層材料可以為金或 銅最為適合。D: \ patent \ nbs \ 870040.ptd Page 29 411569 V. Description of the invention ¢ 27) Table 14: Conclusion steps of the third process Reason 300 Figure 12-Made two insulation layers (120) on the substrate (10) Top: ~ '-310 Figure 13- Covering the photoresist layer (124) on the edge layer (120), and making a contact hole in this photoresist layer; 320 Figure 12_Name insulation layer (120 ) To the surface of the substrate (10) to make a contact hole 330 Figure 12-Making an activation layer (132) on the surface of the exposed substrate (10), this step is completed by immersing the wafer in a solution containing a gasification le; 340 Figure丨 3 & I4-Pladium metal layer (136) is deposited on the activation layer by electroless plating method. In addition to electroless plating technology, this palladium metal layer can also be produced by sputtering: 350 to remove photoresist; 360 Figure 15-Heat-treating the wafer to 'make the metal (136) and the wonderful reaction to form a petrified (140) material layer on the silicon wafer; 370 Figure 16-making a diffusion barrier layer on the palladium silicide (140) layer This diffusion barrier material is most suitable for nickel, cobalt, palladium or its alloys. 380 Figure 16-Selective deposition using electroless plating The first metal layer (148) is on the diffusion barrier layer (144). The material of the first metal layer may be gold or copper; 390 FIG. I7B-making an adhesion layer (252) on the first metal layer (148) The material of this adhesion layer (252) may be aluminum or titanium; 400 FIG. 18B-A second activation layer (253) is deposited on the adhesion layer (252). This activation method is to replace the solution with a solution containing vaporized palladium or zinc. 410 Figure 19B- making a second insulation layer (158) on the first insulation layer, this second insulation layer has a via hole, this via hole must etch the second insulation layer to the vicinity of the contact hole, and Contact hole alignment; 420 FIG. 20B-Selective deposition of a second metal layer (160) on the first metal layer by electroless plating 'and the entire via hole must be filled. The material of the second metal layer can be gold or copper. .
IHHI 第30頁 D:\patent\nbs\870040. ptd ——411569- 五、發明說明（28) 下表是將此製程中較具關鍵步驟整理於下： 表十五：第三種製程的關鍵步驟 層 次 最佳組成或其他參數 其他材料或 製程 160 第二無電鍍金屬層 金或銅 159 導通孔 158 ILD層 253 第二活化層-利用氣化 鈀溶液或鋅置換液 252 鋁或鈦作為附著層 148 第一金屬層 銅 金 144 擴散障礙層 厚度為200nm 錄、#、纪 140 矽化鈀 矽化纪 134 鈀金屬 利用無電鍍或濺鍍方式沉積 132 第一活化層 利用含有鈀離子的溶液 10 基材 矽 圖12-16是第三種製程與第二種製程相同的製作流 程。 圖17B所示的是利用鋁或鈦於第一金屬層（148)上作為 附著層（252)材料；此附著層材料的厚度為50至lOOnm。 圖1 8 B所示的是活化附著層（2 5 2 )材料表面，此活化製程可 以利用含有氣化纪的溶液進行° 圖19B所示的是利用製作第二絕緣層（ILD層）（158)於第一 絕緣層之上，且於第二絕緣層上製作導通孔，此導通孔的 製作須蝕刻第二絕緣層至矽化鈀層（1 5 6 )之上，且須與接IHHI Page 30 D: \ patent \ nbs \ 870040. Ptd ——411569- V. Description of Invention (28) The following table summarizes the key steps in this process below: Table 15: The key to the third process Optimal composition of steps or other parameters Other materials or processes 160 Second electroless metal layer gold or copper 159 Vias 158 ILD layer 253 Second activation layer-using vaporized palladium solution or zinc replacement liquid 252 Aluminum or titanium as adhesion layer 148 The first metal layer is copper-gold 144 The thickness of the diffusion barrier layer is 200 nm, #, period 140, palladium silicide, silicide 134, palladium metal is deposited by electroless plating or sputtering method 132, the first active layer is a solution containing palladium ions, 10 substrate silicon Figure 12-16 shows the same manufacturing process for the third process and the second process. FIG. 17B illustrates the use of aluminum or titanium as the material of the adhesion layer (252) on the first metal layer (148); the thickness of the material of the adhesion layer is 50 to 100 nm. Figure 18B shows the surface of the activated adhesion layer (2 5 2). This activation process can be performed using a solution containing a gasification period. Figure 19B shows the use of a second insulating layer (ILD layer) (158 ) On the first insulating layer, and a via hole is made on the second insulating layer. The fabrication of this via hole must etch the second insulating layer to the palladium silicide layer (156), and it must be connected with
D:\patent\nbs\870040. ptd 第31頁 411569 五、發明說明（29) 觸孔對齊。 圖20B所示的是利用無電鍍技術沉積第二金屬層（160) 於第一金屬層上且填滿導通孔，此第二金屬層（160)的材 料為金或銅為宜。 第二金屬層於第二絕緣層上的侧向成長，可以經由無 電鍍沉積的時間加以控制，此第二金屬層（I 6 0 )材料以金 或銅最為適合，但以銅金屬為佳。 熟悉這個領域的人都會明瞭本發明案中的範例說明只 是本案中的例子，而非限制。在本發明案中所提及的製 程、結構與尺寸是可以隨時修正的。這些製程、結構以及 下列的申請專利範圍才是本發明案的精神。D: \ patent \ nbs \ 870040. Ptd page 31 411569 5. Description of the invention (29) The contact holes are aligned. FIG. 20B shows that a second metal layer (160) is deposited on the first metal layer and fills the via holes by using an electroless plating technique. The material of the second metal layer (160) is preferably gold or copper. The lateral growth of the second metal layer on the second insulating layer can be controlled by the time of electroless deposition. The material of the second metal layer (I 6 0) is most suitable for gold or copper, but copper metal is preferred. Those skilled in the art will understand that the exemplary descriptions in the present invention are only examples in this case, not limitation. The processes, structures, and dimensions mentioned in the present invention can be modified at any time. These processes, structures, and the scope of the following patent applications are the spirit of the present invention.
D:\pateat\nbs\870040, ptd 第32頁D: \ pateat \ nbs \ 870040, ptd p. 32
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108140565A (en) * | 2015-10-05 | 2018-06-08 | 浜松光子学株式会社 | The manufacturing method of wiring structure |
| TWI659126B (en) * | 2015-06-19 | 2019-05-11 | 日商東京威力科創股份有限公司 | Plating treatment method and plating treatment part and plating treatment system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI659126B (en) * | 2015-06-19 | 2019-05-11 | 日商東京威力科創股份有限公司 | Plating treatment method and plating treatment part and plating treatment system |
| CN108140565A (en) * | 2015-10-05 | 2018-06-08 | 浜松光子学株式会社 | The manufacturing method of wiring structure |
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