TWI653367B - Electrochemical deposition on a workpiece having high sheet resistance - Google Patents

Abstract

一種用於至少部分填充工件上的部件的方法通常包括以下步驟：獲得包括部件的工件；將第一導電層沉積在部件中，其中第一導電層的薄層電阻大於10歐姆/方；通過電化學沉積將第二導電層沉積在部件中，其中電氣接觸件至少部分地浸沒在沉積化學品中。 A method for at least partially filling a component on a workpiece generally includes the steps of: obtaining a workpiece comprising the component; depositing a first conductive layer in the component, wherein the first conductive layer has a sheet resistance greater than 10 ohms/square; The deposition deposits a second electrically conductive layer in the component, wherein the electrical contacts are at least partially submerged in the deposition chemistry.

Description

具有高薄片電阻之工件上的電化學沉積 Electrochemical deposition on a workpiece with high sheet resistance 【相關申請的交叉引用】[Cross-reference to related applications]

本案是2013年03月13日提出申請的美國專利申請第13/801786號的部分繼續申請，該美國專利申請請求於2012年04月26日提出申請的美國臨時申請第61/638851號的權益，通過引用將這些美國申請的公開內容全部明確地併入於此。 The present application is a continuation-in-part of U.S. Patent Application Serial No. 13/ 801, 786, filed on Mar. The disclosures of these U.S. applications are hereby expressly incorporated by reference in their entirety.

本案內容涉及用於在微電子工件的部件(例如，溝槽和過孔(via)，特別是鑲嵌(Damascene)應用中的溝槽和過孔)中電化學沉積導電材料(例如金屬，例如，銅(Cu)、鈷(Co)、鎳(Ni)、金(Au)、銀(Ag)、錳(Mn)、錫(Sn)、鋁(Al)和以上各物的合金)的方法。 The present disclosure relates to the electrochemical deposition of conductive materials (eg, metals, for example, metals) in components of microelectronic workpieces (eg, trenches and vias, particularly trenches and vias in damascene applications). A method of copper (Cu), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminum (Al), and alloys of the above.

積體電路是形成在半導體材料和覆蓋半導體材料表面的電媒體材料之內的裝置的互連整體。可形成在半導體內的裝置包括MOS電晶體、雙極型電晶體、二極體和擴散電阻器。可形成在電媒體之內的裝置包括薄膜電阻器和電容器。裝置通過形成在電媒體之內的導體路徑互連。通常，具有由 電媒體層分隔的連續級的兩級或更多級的導體路徑用作互連。在現行實踐中，氧化矽和銅通常分別用於電媒體和導體。 The integrated circuit is an interconnected body of devices formed within the semiconductor material and the dielectric material covering the surface of the semiconductor material. Devices that can be formed within a semiconductor include MOS transistors, bipolar transistors, diodes, and diffusion resistors. Devices that can be formed within an electrical medium include thin film resistors and capacitors. The devices are interconnected by conductor paths formed within the electrical medium. Usually, with Conductor paths of two or more stages of continuous stages separated by a dielectric layer are used as interconnections. In current practice, yttrium oxide and copper are commonly used in electrical media and conductors, respectively.

銅互連體中的沉積物(deposit)通常包括電媒體層、阻擋層、種晶層、銅填充和銅覆蓋(cap)。因為銅易於擴散到電媒體材料中，所以阻擋層用於使銅沉積物與電媒體材料分隔開。然而，應理解，對於除銅之外的其他金屬互連體可以不需要阻擋層。阻擋層通常由耐火金屬或耐火化合物構成，例如，鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)等。其他合適的阻擋層材料可包括錳(Mn)和氮化錳(MnN)。通常使用稱為物理氣相沉積(PVD)的沉積技術形成阻擋層，但也可通過使用其他沉積技術(例如，化學氣相沉積(CVD)或原子層沉積(ALD))形成阻擋層。 Deposits in copper interconnects typically include an electrical dielectric layer, a barrier layer, a seed layer, a copper fill, and a copper cap. Because copper readily diffuses into the dielectric material, the barrier layer serves to separate the copper deposit from the dielectric material. However, it should be understood that a barrier layer may not be required for other metal interconnects than copper. The barrier layer is usually composed of a refractory metal or a refractory compound, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or the like. Other suitable barrier materials can include manganese (Mn) and manganese nitride (MnN). The barrier layer is typically formed using a deposition technique known as physical vapor deposition (PVD), but barrier layers can also be formed by using other deposition techniques, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

種晶層可沉積在阻擋層上。然而，還應理解，直接在阻擋層上(direct on barrier)(DOB)沉積也在本案內容的範圍內，所述直接在阻擋層上(DOB)沉積例如在由合金或共沉積(co-deposited)金屬構成的阻擋層以及在所屬領域的技藝人士所熟知及/或所使用的其他阻擋層上的沉積，互連金屬可沉積在由合金或共沉積金屬構成的所述阻擋層上而不需要單獨的種晶層，所述互連金屬例如鈦釕(TiRu)、鉭釕(TaRu)、鎢釕(WRu)。 A seed layer can be deposited on the barrier layer. However, it should also be understood that direct direct on barrier (DOB) deposition is also within the scope of the present disclosure, which is deposited directly on the barrier layer (DOB), for example by alloying or co-depositing. Metallized barrier layer and deposition on other barrier layers well known and/or used by those skilled in the art, interconnect metal can be deposited on the barrier layer composed of alloy or co-deposited metal without the need for A separate seed layer, such as TiRu, TaRu, WRu.

在一個非限制實例中，種晶層可為銅種晶層。作為另一非限制實例，種晶層可為銅合金種晶層，例如，銅錳合金、銅鈷合金或銅鎳合金。在將銅沉積於部件中的情況下，對於種晶層有數個示例性選擇。第一，種晶層可為PVD銅種 晶層。參見例如用於說明包括PVD銅種晶沉積的製程的圖3。種晶層還可通過使用其他沉積技術(例如CVD或ALD)形成。 In one non-limiting example, the seed layer can be a copper seed layer. As another non-limiting example, the seed layer may be a copper alloy seed layer, such as a copper manganese alloy, a copper cobalt alloy, or a copper nickel alloy. In the case where copper is deposited in the component, there are several exemplary options for the seed layer. First, the seed layer can be a PVD copper species. Crystal layer. See, for example, Figure 3 for illustrating a process including PVD copper seed deposition. The seed layer can also be formed by using other deposition techniques such as CVD or ALD.

第二，種晶層可為堆疊膜，例如，襯墊層及PVD種晶層。襯墊層是用在阻擋層與PVD種晶之間緩解不連續種晶問題並改善PVD種晶粘附力的材料。襯墊通常是貴金屬，例如釕(Ru)、鉑(Pt)、鈀(Pd)和鋨(Os)，但該系列還可包括鈷(Co)和鎳(Ni)。當前，CVD Ru和CVD Co是常見的襯墊；然而，襯墊層也可通過使用其他沉積技術(例如，ALD或PVD)形成。 Second, the seed layer can be a stacked film, such as a liner layer and a PVD seed layer. The liner layer is a material used to relieve discontinuous seed crystal problems between the barrier layer and the PVD seed crystal and to improve PVD seed crystal adhesion. The liner is typically a noble metal such as ruthenium (Ru), platinum (Pt), palladium (Pd), and osmium (Os), but the series may also include cobalt (Co) and nickel (Ni). Currently, CVD Ru and CVD Co are common liners; however, the liner layer can also be formed by using other deposition techniques (eg, ALD or PVD).

第三，種晶層可為二次種晶層。二次種晶層類似於襯墊層，是因為二次種晶層通常由貴金屬(例如Ru、Pt、Pd和Os)形成，但該系列還可包括Co及Ni和最常見的CVD Ru及CVD Co。(像種晶層及襯墊層一樣，二次種晶層還可通過使用其他沉積技術(例如ALD或PVD)形成。)不同之處在於：二次種晶層用作種晶層，而襯墊層是介於阻擋層與PVD種晶之間的中間層。參見例如用於說明包括二次種晶沉積的製程的圖5及圖6，所述二次種晶沉積之後分別是圖5中的ECD種晶沉積，如下文所描述，及圖6中的快閃物沉積(flash deposition)。(「快閃物」沉積主要是在部件的區域(field)上及底部處，沒有顯著沉積在部件側壁上。) Third, the seed layer can be a secondary seed layer. The secondary seed layer is similar to the liner layer because the secondary seed layer is typically formed of noble metals such as Ru, Pt, Pd, and Os, but the series may also include Co and Ni and the most common CVD Ru and CVD. Co. (Like the seed layer and the liner layer, the secondary seed layer can also be formed by using other deposition techniques (such as ALD or PVD).) The difference is that the secondary seed layer is used as a seed layer, and the lining The underlayer is an intermediate layer between the barrier layer and the PVD seed crystal. See, for example, FIGS. 5 and 6 for illustrating a process including secondary seed deposition, which is followed by ECD seed deposition in FIG. 5, as described below, and in FIG. Flash deposition. (The "flash" deposits are mainly on the top and bottom of the part and are not significantly deposited on the side walls of the part.)

在已根據上述實例中的一個實例沉積種晶層之後，部件可包括種晶層增強(SLE)層，所述種晶層增強(SLE)層是沉積的金屬(例如，厚度約2nm的銅)的薄層。SLE層也 被稱為電化學沉積種晶(或ECD種晶)。參見例如用於說明包括PVD種晶沉積及ECD種晶沉積的製程的圖4。參見例如用於說明包括二次種晶沉積及ECD種晶沉積的製程的圖5。如圖4及圖5中所見，ECD種晶可為共形沉積(conformally deposited)層。 After the seed layer has been deposited according to one of the above examples, the component may include a seed layer enhancement (SLE) layer, which is a deposited metal (eg, copper having a thickness of about 2 nm). Thin layer. SLE layer also It is called electrochemical deposition seed crystal (or ECD seed crystal). See, for example, Figure 4 for illustrating a process including PVD seed deposition and ECD seed deposition. See, for example, Figure 5 for illustrating a process including secondary seed deposition and ECD seed deposition. As seen in Figures 4 and 5, the ECD seed crystal can be a conformally deposited layer.

通常使用包括濃度很低的銅乙二胺(EDA)絡合物的鹼性化學品(basic chemistry)沉積ECD銅種晶。還可使用其他銅絡合物(例如，檸檬酸銅、酒石酸銅和尿素銅等)沉積ECD銅種晶，且可在約2到約11、約3到約10的pH範圍內或在約4到約10的pH範圍內沉積ECD銅種晶。 ECD copper seed crystals are typically deposited using basic chemistry including a very low concentration of copper ethylene diamine (EDA) complex. ECD copper seed crystals may also be deposited using other copper complexes (eg, copper citrate, copper tartrate, and urea copper, etc.) and may range from about 2 to about 11, from about 3 to about 10, or at about 4 ECD copper seed crystals are deposited to a pH range of about 10.

在已根據上述實例中的一個實例沉積種晶層之後(所述種晶層也可包括可選的ECD種晶)，例如，可使用酸性沉積化學品在部件中執行傳統的ECD填充及覆蓋。傳統的ECD銅酸性化學品可包括例如硫酸銅、硫酸、甲磺酸、鹽酸和有機添加劑(例如，促進劑(accelerator)、抑制劑(suppressor)及調平劑(leveler))。已發現銅的電化學沉積是沉積銅金屬化層最經濟的方式。除了在經濟上可行外，ECD沉積技術提供實質上自下而上(例如，非共形)金屬填充，所述金屬填充在機械上和電氣上適用於互連結構。 After the seed layer has been deposited according to one of the above examples (the seed layer may also include an optional ECD seed crystal), for example, conventional ECD fill and coverage may be performed in the part using an acidic deposition chemistry. Conventional ECD copper acid chemicals may include, for example, copper sulfate, sulfuric acid, methanesulfonic acid, hydrochloric acid, and organic additives (eg, accelerators, suppressors, and levelers). Electrochemical deposition of copper has been found to be the most economical way to deposit a copper metallization layer. In addition to being economically viable, ECD deposition techniques provide substantially bottom-up (eg, non-conformal) metal fill that is mechanically and electrically suitable for interconnect structures.

傳統的ECD填充，尤其是小部件中的ECD填充，可導致較低品質互連。舉例來說，傳統ECD銅填充可產生空隙，尤其是在尺寸小於30nm的部件中產生空隙。作為使用傳統的ECD沉積形成的空隙類型的一個實例，部件的開口可夾斷(pinch off)。其他類型的空隙還可因在小部件中使用傳統的 ECD銅填充製程而產生。所述空隙及使用傳統的ECD銅填充形成的沉積物的其他固有性質可增加互連體的電阻，從而降低裝置的電氣性能並使銅互連體的可靠性退化。 Traditional ECD fills, especially ECD fills in small parts, can result in lower quality interconnects. For example, conventional ECD copper fill can create voids, especially in components that are less than 30 nm in size. As an example of a type of void formed using conventional ECD deposition, the opening of the component can be pinch off. Other types of voids can also be used for traditional parts in small parts. Produced by ECD copper filling process. The voids and other inherent properties of deposits formed using conventional ECD copper fill can increase the electrical resistance of the interconnect, thereby reducing the electrical performance of the device and degrading the reliability of the copper interconnect.

因此，存在對用於部件的改善的、實質上無空隙金屬填充製程的需要。所述實質上無空隙金屬填充可用於小部件中，例如，具有小於30nm的開口尺寸的部件。 Therefore, there is a need for an improved, substantially void-free metal fill process for components. The substantially void-free metal fill can be used in small parts, for example, parts having an opening size of less than 30 nm.

隨著部件大小變得越來越小，組成互連體的薄沉積物層趨向於具有非常高的薄層電阻(sheet resistance)，所述非常高的薄層電阻會在電化學沉積中產生困難。因此，存在對用於在薄層電阻值例如大於10歐姆/方(ohm/square)的導電層上電化學沉積的系統和方法的需要。 As component sizes become smaller and smaller, thin deposit layers that make up the interconnect tend to have very high sheet resistance, which can cause difficulties in electrochemical deposition. . Accordingly, a need exists for systems and methods for electrochemical deposition on a conductive layer having a sheet resistance value of, for example, greater than 10 ohms/square.

本案內容的實施方式涉及解決這些和其他問題。 The implementation of the content of this case involves addressing these and other issues.

提供此發明內容從而以簡化形式來介紹構思的選擇，在下文具體實施方式中進一步描述所述構思。本發明內容不意在辨識所要求保護的客體的關鍵特徵，也不意在用作決定所要求保護的客體的範圍的輔助內容。 The Summary is provided to introduce a selection of concepts in a simplified form, which is further described in the Detailed Description. This Summary is not intended to identify key features of the claimed subject matter, and is not intended to be used as an adjunct to the scope of the claimed subject matter.

根據本案內容的一個實施方式，提供一種用於至少部分填充工件上的部件的方法。所述方法大體包括以下步驟：獲得包括部件的工件；將第一導電層沉積在部件中，其中所述第一導電層的薄層電阻大於10歐姆/方；和通過電化學沉積將第二導電層沉積在部件中，其中電氣接觸件(electrical contact)至少部分地浸沒(immersed)在沉積化學品中。 According to one embodiment of the present disclosure, a method for at least partially filling a component on a workpiece is provided. The method generally includes the steps of: obtaining a workpiece comprising a component; depositing a first conductive layer in the component, wherein a sheet resistance of the first conductive layer is greater than 10 ohms/square; and conducting the second conductive by electrochemical deposition A layer is deposited in the component, wherein the electrical contacts are at least partially immersed in the deposition chemistry.

根據本案內容的一個實施方式，提供一種用於至少 部分填充工件上的部件的方法。所述方法大體包括以下步驟：獲得包括部件的工件；將種晶層沉積在部件中，其中第一導電層的薄層電阻大於10歐姆/方；和通過電化學沉積將導電層沉積在部件中並且在種晶層上，其中電氣接觸件至少部分地浸沒在沉積化學品中。 According to an embodiment of the present disclosure, a method is provided for at least A method of partially filling a part on a workpiece. The method generally includes the steps of: obtaining a workpiece comprising a component; depositing a seed layer in the component, wherein a sheet resistance of the first conductive layer is greater than 10 ohms/square; and depositing the conductive layer in the component by electrochemical deposition And on the seed layer, wherein the electrical contacts are at least partially submerged in the deposition chemistry.

根據本案內容的一個實施方式，提供一種工件。所述工件大體包括：部件；在部件中的第一導電層，其中第一導電層的薄層電阻大於10歐姆/方；和在部件中的第二導電層，其中第二導電層覆蓋第一導電層的整個表面。 According to one embodiment of the present disclosure, a workpiece is provided. The workpiece generally includes: a component; a first conductive layer in the component, wherein a sheet resistance of the first conductive layer is greater than 10 ohms/square; and a second conductive layer in the component, wherein the second conductive layer covers the first The entire surface of the conductive layer.

100‧‧‧反流製程 100‧‧‧Reflux process

102‧‧‧步驟 102‧‧‧Steps

104‧‧‧步驟 104‧‧‧Steps

106‧‧‧步驟 106‧‧‧Steps

108‧‧‧步驟 108‧‧‧Steps

110‧‧‧步驟 110‧‧‧Steps

112‧‧‧工件 112‧‧‧Workpiece

114‧‧‧阻擋層 114‧‧‧Block

115‧‧‧種晶層 115‧‧‧ seed layer

116‧‧‧ECD種晶材料 116‧‧‧ECD seed material

118‧‧‧填充物 118‧‧‧Filling

120‧‧‧額外材料 120‧‧‧Additional materials

122‧‧‧部件 122‧‧‧ Parts

在結合附圖考慮時，通過參考以下詳細描述將更易於理解本案內容的前述方面及許多伴隨優點，其中：圖1為圖示本案內容示例性實施方式的製程步驟及示例性特徵發展程序的示意性流程圖；圖2為可結合已有技術製程使用的示例性製程步驟與根據本案內容實施方式的製程的比較圖；圖3為圖示使用已有技術主要鑲嵌製程的製程步驟和示例性特徵發展程序的示意性流程圖，包括阻擋層沉積、種晶沉積及傳統ECD填充和覆蓋沉積；圖4為圖示使用已有技術SLE(也稱為ECD種晶)製程的製程步驟及示例性特徵發展程序的示意性流程圖，包括阻擋層沉積、種晶沉積、ECD種晶沉積和傳統的ECD填充及覆蓋沉積；圖5為圖示使用已有技術ECD種晶製程的製程步驟 和示例性特徵發展程序的示意性流程圖，包括阻擋層沉積、二次種晶沉積、ECD種晶沉積和傳統ECD填充及覆蓋沉積；圖6為圖示具有快閃層的二次種晶製程方面的使用已有技術沉積的製程步驟和示例性特徵發展程序的示意性流程圖，包括阻擋層沉積、二次種晶沉積、快閃物沉積和傳統的ECD填充及覆蓋沉積；圖7為圖示本案內容的若干示例性實施方式的製程步驟及示例性特徵發展程序的示意性流程圖；圖8為根據本案內容實施方式針對各種示例性晶片在鑲嵌部件中沉積的示例性製程步驟的圖表圖示，所述鑲嵌部件具有約30nm的部件直徑；圖9為從圖8中描述的示例性晶片中獲得的120微米長的線電阻器(line resistor)電阻結果的圖表圖示；圖10為從圖8中描述的示例性晶片中獲得的1米長的線電阻器電阻結果的圖表圖示；圖11為從圖8中描述的示例性晶片中獲得的1米長的電阻器阻容延遲結果的圖表圖示；圖12包括用於根據本案內容實施方式的鑲嵌部件的實質上無空隙間隙填充的透射電子顯微鏡(TEM)圖像，所述鑲嵌部件具有約30nm的部件直徑；和圖13A和13B是圖示根據本案內容實施方式的示例性工件的示意圖。 The foregoing aspects and many of the attendant advantages of the present disclosure will be more readily understood by reference to the following detailed description in which <RTIgt; FIG. 2 is a comparison diagram of an exemplary process step that can be used in conjunction with a prior art process and a process according to an embodiment of the present disclosure; FIG. 3 is a process diagram and exemplary features illustrating a main damascene process using the prior art; Schematic flow chart of development procedures, including barrier deposition, seed deposition, and conventional ECD fill and overlay deposition; Figure 4 is a process diagram and exemplary features illustrating the prior art SLE (also known as ECD seed crystal) process A schematic flow chart of the development process, including barrier deposition, seed deposition, ECD seed deposition, and conventional ECD fill and overlay deposition; FIG. 5 is a process diagram illustrating the use of prior art ECD seeding processes And a schematic flow chart of an exemplary feature development program, including barrier deposition, secondary seed deposition, ECD seed deposition, and conventional ECD fill and overlay deposition; FIG. 6 is a diagram illustrating a secondary seed process with a flash layer A schematic flow diagram of a process step and an exemplary feature development procedure using prior art deposition, including barrier deposition, secondary seed deposition, flash deposition, and conventional ECD fill and overlay deposition; FIG. A schematic flow diagram of process steps and exemplary feature development procedures for several exemplary embodiments of the present disclosure; FIG. 8 is a diagrammatic view of exemplary process steps for deposition of various exemplary wafers in a damascene component in accordance with an embodiment of the present disclosure. The damascene feature has a component diameter of about 30 nm; FIG. 9 is a graphical illustration of a 120 micron long line resistor resistance result obtained from the exemplary wafer depicted in FIG. 8; A graphical representation of the 1 meter long line resistor resistance result obtained in the exemplary wafer depicted in FIG. 8; FIG. 11 is a 1 meter long obtained from the exemplary wafer depicted in FIG. Graphical illustration of the resistance of the resistive resistance delay; FIG. 12 includes a transmission electron microscope (TEM) image for substantially void-free gap filling of a damascene member having an embodiment of the present disclosure, the damascene member having a component of about 30 nm Diameter; and Figures 13A and 13B are schematic diagrams illustrating exemplary workpieces in accordance with an embodiment of the present disclosure.

本案內容的實施方式涉及工件(例如半導體晶片) 、用於處理工件的裝置或處理元件以及處理所述工件的方法。術語工件、晶片或半導體晶片意指任何平坦的媒體或物件，包括半導體晶片和其他基板或晶片、玻璃、遮罩和光學或儲存媒體、MEMS基板或任何其他具有微電子、微機械或微機電裝置的工件。 Embodiments of the present disclosure relate to workpieces (eg, semiconductor wafers) A device or processing element for processing a workpiece and a method of processing the workpiece. The term workpiece, wafer or semiconductor wafer means any flat medium or object, including semiconductor wafers and other substrates or wafers, glass, masks and optical or storage media, MEMS substrates or any other device having microelectronics, micromechanics or microelectromechanical devices. The artifact.

本文述及之製程將用於工件部件中的金屬沉積或金屬合金沉積，所述部件包括溝槽和過孔。在本案內容的一個實施方式中，製程可用於小部件中，例如具有小於30nm的部件直徑或臨界尺寸(critical dimension)的部件。然而，應理解，本文述及之製程可適用於任何部件尺寸。本案中所論述的尺寸大小是在部件的頂部開口處的蝕刻後特徵尺寸。本文述及之製程可應用於例如鑲嵌應用中的各種形式的銅、鈷、鎳、金、銀、錳、錫、鋁和合金沉積。在本案內容的實施方式中，鑲嵌部件可選自由具有以下大小的部件組成的群組：小於30nm、約5nm到小於30nm、約10nm到小於30nm、約15nm到約20nm、約20nm到小於30nm、小於20nm、小於10nm及約5nm到約10nm。 The processes described herein will be used for metal deposition or metal alloy deposition in workpiece parts, including trenches and vias. In one embodiment of the present disclosure, the process can be used in small parts, such as parts having a component diameter or critical dimension of less than 30 nm. However, it should be understood that the processes described herein are applicable to any component size. The dimensions discussed in this case are post-etched feature sizes at the top opening of the component. The processes described herein can be applied to various forms of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, and alloy deposition, for example, in damascene applications. In embodiments of the present disclosure, the damascene member may be selected from the group consisting of: less than 30 nm, from about 5 nm to less than 30 nm, from about 10 nm to less than 30 nm, from about 15 nm to about 20 nm, from about 20 nm to less than 30 nm, Less than 20 nm, less than 10 nm, and about 5 nm to about 10 nm.

應理解，本文中所使用的描述性術語「微特徵工件」及「工件」包括先前已經在製程程序中沉積並形成在給定點的所有結構和層，並且並不僅限於圖1中所圖示的那些結構和層。 It should be understood that the descriptive terms "micro-feature workpiece" and "workpiece" as used herein include all structures and layers that have been previously deposited in a process program and formed at a given point, and are not limited to those illustrated in FIG. Those structures and layers.

應理解，也可修改本文述及之製程用於高深寬比部件(例如，穿透矽過孔(TSV)部件中的過孔)中的金屬或金屬合金沉積，如於2013年03月13日提出申請的美國申請第 13/801860號(卷號第017214USA02；SEMT-1-39699號)中描述的那樣，通過引用將所述美國申請的公開內容全部併入於此。 It should be understood that the processes described herein may also be modified for metal or metal alloy deposition in high aspect ratio components (eg, vias in through-via via (TSV) components), as of March 13, 2013. US application for filing The disclosure of the U.S. Application is hereby incorporated by reference in its entirety in its entirety by reference in its entirety in the the the the the the the the the the the the

儘管在本案中大致描述為金屬沉積，但應理解，術語「金屬」也涵蓋金屬合金。所述金屬及金屬合金可用於形成種晶層或用於完全或部分填充部件。示例性銅合金可包括但不限於銅錳和銅鋁。作為非限制實例，與主要合金金屬(例如Cu、Co、Ni、Ag、Au等)相比，合金成分配比可在約0.5%到約6%的次要合金金屬的範圍內。 Although generally described herein as metal deposition, it should be understood that the term "metal" also encompasses metal alloys. The metals and metal alloys can be used to form seed layers or for fully or partially filling components. Exemplary copper alloys can include, but are not limited to, copper manganese and copper aluminum. As a non-limiting example, the alloy may be distributed in a range of from about 0.5% to about 6% of the secondary alloy metal as compared to the primary alloying metal (e.g., Cu, Co, Ni, Ag, Au, etc.).

如上所述，金屬互連體的傳統製造可包括將阻擋層適當沉積在電媒體材料上以防止金屬擴散到電媒體材料中。合適的阻擋層可包括例如Ta、Ti、TiN、TaN、Mn或MnN。合適的阻擋層沉積方法可包括PVD、ALD及CVD；然而，PVD是用於阻擋層沉積的最常見製程。阻擋層通常用於使銅或銅合金與電媒體材料分隔開；然而，應理解，在其他金屬互連體的情況下，擴散可能不是問題並且可不需要阻擋層。 As noted above, conventional fabrication of metal interconnects can include properly depositing a barrier layer on the dielectric material to prevent diffusion of the metal into the dielectric material. Suitable barrier layers can include, for example, Ta, Ti, TiN, TaN, Mn or MnN. Suitable barrier deposition methods can include PVD, ALD, and CVD; however, PVD is the most common process for barrier deposition. The barrier layer is typically used to separate copper or copper alloy from the dielectric material; however, it should be understood that in the case of other metal interconnects, diffusion may not be an issue and a barrier layer may not be needed.

阻擋層沉積之後可以是可選的種晶層沉積。在將金屬沉積於部件中的情況下，對於種晶層有數個選擇。如上所述，種晶層可為(1)種晶層(作為非限制實例，是PVD銅種晶層)。種晶層可為金屬層，例如，銅、鈷、鎳、金、銀、錳、錫、鋁、釕和以上各物的合金。種晶層還可為(2)襯墊層與種晶層(作為非限制實例，是CVD Ru襯墊層及PVD銅種晶層)的堆疊膜，或(3)二次種晶層(作為非限制實例，是CVD或ALD Ru二次種晶層)。然而，應理解，本案內容也涵蓋沉 積所述示例性種晶層的其他方法。 The barrier layer deposition may be followed by an optional seed layer deposition. In the case where metal is deposited in the component, there are several options for the seed layer. As described above, the seed layer may be (1) a seed layer (as a non-limiting example, a PVD copper seed layer). The seed layer may be a metal layer such as copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, antimony, and alloys of the above. The seed layer may also be a stacked film of (2) a liner layer and a seed layer (as a non-limiting example, a CVD Ru liner layer and a PVD copper seed layer), or (3) a secondary seed layer (as A non-limiting example is a CVD or ALD Ru secondary seed layer). However, it should be understood that the content of this case also covers Shen Other methods of enumerating the exemplary seed layers.

如上文所論述，襯墊層是用在阻擋層與種晶層之間緩解不連續的種晶問題並改善種晶層粘附力的材料。襯墊通常是貴金屬，例如Ru、Pt、Pd和Os，但所述清單還可包括Co和Ni。當前，CVD Ru和CVD Co是常見的襯墊；然而，襯墊層也可通過使用其他沉積技術(例如，PVD或ALD)形成。對於鑲嵌應用，襯墊層的厚度可在大約5Å到50Å的範圍內。 As discussed above, the liner layer is a material used to mitigate discontinuous seeding problems between the barrier layer and the seed layer and to improve the adhesion of the seed layer. The liner is typically a precious metal such as Ru, Pt, Pd and Os, but the list may also include Co and Ni. Currently, CVD Ru and CVD Co are common liners; however, the liner layer can also be formed by using other deposition techniques (eg, PVD or ALD). For damascene applications, the thickness of the liner layer can range from about 5 Å to 50 Å.

同樣如上文所論述，二次種晶層類似於襯墊層，是因為二次種晶層通常由貴金屬(例如Ru、Pt、Pd和Os)形成，但該清單還可包括Co及Ni和最常見的CVD Ru及CVD Co。不同之處在於：二次種晶層用作種晶層，而襯墊層是介於阻擋層與種晶層之間的中間層。二次種晶層還可通過使用其他沉積技術(例如PVD或ALD)形成。 As also discussed above, the secondary seed layer is similar to the liner layer because the secondary seed layer is typically formed of noble metals (eg, Ru, Pt, Pd, and Os), but the list may also include Co and Ni and most Common CVD Ru and CVD Co. The difference is that the secondary seed layer is used as a seed layer, and the liner layer is an intermediate layer between the barrier layer and the seed layer. The secondary seed layer can also be formed by using other deposition techniques such as PVD or ALD.

可在純H₂氣體環境(或者在大氣壓下或者在減小的壓強下)或合成氣體(forming gas)環境(例如，氮氣中有3%-5%的氫氣或氦氣中有3%-5%的氫氣)中，在介於約100℃到約500℃之間的溫度下熱處理或退火襯墊或二次種晶沉積物，以去除任何表面氧化物、使二次種晶層或襯墊層緻密、並改善沉積物的表面性質。可通過在氣態氮(N₂氣體)或其他鈍化環境中浸漬來另外鈍化襯墊或二次種晶沉積物，以防止表面氧化。襯墊或二次種晶的鈍化描述於2013年01月22日發佈的美國專利第8357599號中，在此通過引用將所述美國專利的公開內容全部明確地併入。 It can be in a pure H ₂ gas environment (either at atmospheric pressure or under reduced pressure) or a forming gas environment (for example, 3%-5% of hydrogen or helium in nitrogen is 3%-5) Heat treatment or annealing of the liner or secondary seed deposit at a temperature between about 100 ° C and about 500 ° C to remove any surface oxide, secondary seed layer or liner The layer is dense and improves the surface properties of the deposit. The liner or secondary seed deposit may be additionally passivated by immersion in gaseous nitrogen (N ₂ gas) or other passivation environment to prevent surface oxidation. The pad or secondary seed passivation is described in U.S. Patent No. 8,357, 599 issued on Jan. 22, 2013, the entire disclosure of which is hereby incorporated by reference.

在已沉積種晶層(例如，PVD銅種晶、包括CVD Ru 襯墊或CVD Ru二次種晶的PVD銅種晶、或另一沉積金屬或金屬合金、層組合或沉積技術的非限制實例中的一個非限制實例)後，部件可包括在種晶層之後的共形金屬層。然而，還應理解，共形金屬層可直接沉積在阻擋層上，即沒有種晶層。 Seeding layers have been deposited (eg, PVD copper seed crystals, including CVD Ru After the liner or CVD Ru secondary seed PVD copper seed crystal, or another non-limiting example of a non-limiting example of a deposited metal or metal alloy, layer combination or deposition technique, the component may be included after the seed layer Conformal metal layer. However, it should also be understood that the conformal metal layer can be deposited directly on the barrier layer, i.e., without the seed layer.

在本案內容的一個實施方式中，使用ECD種晶製程沉積共形層，然後可使用包括熱處理步驟的被稱為ECD種晶「附加」沉積(或ECD種晶「附加」)的製程來修改所述共形層。在本案內容的其他實施方式中，可使用CVD、ALD或其他沉積技術(例如，無電沉積(electroless deposition))沉積共形層，然後可使共形層經受熱處理步驟。根據本案內容的實施方式，共形層在經受熱處理或退火時是「可流動的」或能夠移動的。 In one embodiment of the present disclosure, a conformal layer is deposited using an ECD seeding process, and then a process known as an ECD seed crystal "additional" deposition (or ECD seed crystal "addition") including a heat treatment step can be used to modify the The conformal layer. In other embodiments of the present disclosure, the conformal layer can be deposited using CVD, ALD, or other deposition techniques (eg, electroless deposition), and then the conformal layer can be subjected to a heat treatment step. According to embodiments of the present disclosure, the conformal layer is "flowable" or movable when subjected to heat treatment or annealing.

在此實施方式中，ECD種晶「附加」大致是指ECD金屬種晶沉積加上熱處理步驟(例如退火步驟)。在本案內容的一個實施方式中，熱處理步驟可導致一些或全部種晶沉積的反流。ECD種晶層中溫度的增加有助於層中原子的行動性並增強原子填充結構的能力。 In this embodiment, the "addition" of the ECD seed crystal generally refers to the ECD metal seed deposition plus a heat treatment step (eg, an annealing step). In one embodiment of the present disclosure, the heat treatment step can result in a reflux of some or all of the seed deposition. The increase in temperature in the ECD seed layer contributes to the mobility of the atoms in the layer and enhances the ability of the atom to fill the structure.

與傳統ECD金屬填充(使用酸性化學品)相對比，ECD種晶「附加」沉積類似於ECD種晶沉積(使用鹼性化學品)，但增加了熱處理步驟。此外，不是僅沉積種晶層，而是可執行ECD種晶「附加」以便部分填充或完全填充部件。可通過ECD種晶「附加」製程實現小部件的實質無空隙填充，如下文更詳細地描述的那樣(參見圖12中小部件中的實質無空 隙填充的圖像)。 In contrast to conventional ECD metal fills (using acidic chemicals), ECD seed crystal "additional" deposition is similar to ECD seed crystal deposition (using alkaline chemicals), but with an increased heat treatment step. Furthermore, instead of depositing only the seed layer, an ECD seed crystal "addition" can be performed to partially fill or completely fill the part. Substantial void-free filling of the widget can be achieved by the ECD seed crystal "additional" process, as described in more detail below (see Figure 12 for the absence of material in the widget) Gap filled image).

在用於ECD種晶「附加」沉積的ECD腔室中使用的化學品可包括鹼性化學品，例如，在約8到約11的範圍內的pH下的Cu(乙二胺)2，在本案內容的一個實施方式中pH為約8到約10，且在本案內容的一個實施方式中pH為約9.3。然而，應理解，使用適當有機添加劑的酸性化學品也可用於實現共形ECD種晶沉積。 The chemicals used in the ECD chamber for "additional" deposition of ECD seed crystals may include alkaline chemicals, for example, Cu (ethylenediamine) 2 at a pH in the range of from about 8 to about 11, in In one embodiment of the present disclosure the pH is from about 8 to about 10, and in one embodiment of the present disclosure the pH is about 9.3. However, it should be understood that acidic chemicals using suitable organic additives can also be used to achieve conformal ECD seed deposition.

在ECD種晶沉積之後，接著可使工件經受旋轉(spin)、沖洗及乾燥(SRD)製程或其他清潔製程。然後在足夠溫暖以使種晶反流的溫度下加熱ECD種晶，但該溫度並未過熱以致工件或工件上的元件損壞或退化。舉例來說，溫度可在約100℃到約500℃的範圍內以用於部件中的種晶反流。適當的熱處理溫度或退火溫度在約100℃到約500℃的範圍內，且可用能夠將持續溫度維持在約200℃到約400℃的範圍內並至少維持在約250℃到約350℃的溫度範圍內的設備實現所述適當的熱處理溫度或退火溫度。 After the ECD seed deposition, the workpiece can then be subjected to a spin, rinse and dry (SRD) process or other cleaning process. The ECD seed crystal is then heated at a temperature that is warm enough to cause the seed crystal to flow back, but the temperature is not overheated such that the components on the workpiece or workpiece are damaged or degraded. For example, the temperature can range from about 100 ° C to about 500 ° C for seed crystal reflux in the part. A suitable heat treatment temperature or annealing temperature is in the range of from about 100 ° C to about 500 ° C, and can be maintained at a temperature ranging from about 200 ° C to about 400 ° C and maintained at a temperature of from about 250 ° C to about 350 ° C. The equipment within the range achieves the appropriate heat treatment temperature or annealing temperature.

可使用合成氣體或惰性氣體、純氫、氫與氦的混合物、或還原性氣體(例如，氨(NH₃))執行熱處理製程或退火製程。在反流期間，沉積形狀改變，使得金屬沉積物可彙集(pool)在部件的底部，如圖7中所示。除了在熱處理製程期間的反流外，金屬沉積物還可產生較大晶粒並降低膜電阻係數。惰性氣體可用於冷卻加熱後的工件。 The heat treatment process or the annealing process may be performed using a synthesis gas or an inert gas, pure hydrogen, a mixture of hydrogen and ruthenium, or a reducing gas (for example, ammonia (NH ₃ )). During the reverse flow, the deposition shape changes such that the metal deposits can pool at the bottom of the component, as shown in FIG. In addition to backflow during the heat treatment process, metal deposits can also produce larger grains and reduce the film resistivity. An inert gas can be used to cool the heated workpiece.

在已完成ECD種晶「附加」沉積及熱處理製程以部分填充或完全填充部件之後，傳統的酸性化學品可用於完成 用於間隙填充及覆蓋沉積的沉積製程。酸性化學品金屬沉積步驟大致用於填充大結構並用於維持後續拋光步驟所需的適當薄膜厚度，因為所述酸性化學品金屬沉積步驟通常是比ECD種晶製程更快的製程，節省時間並降低處理成本。 Traditional acid chemicals can be used to complete the ECD seed crystal "additional" deposition and heat treatment process to partially fill or completely fill the part A deposition process for gap fill and overlay deposition. The acidic chemical metal deposition step is generally used to fill large structures and to maintain the proper film thickness required for subsequent polishing steps, as the acidic chemical metal deposition step is typically a faster process than the ECD seeding process, saving time and reducing Processing costs.

如圖1及圖7中所見，可重複ECD種晶沉積及反流步驟以確保完成用ECD種晶填充部件。在這方面，本文述及之製程可包括一或多個ECD種晶沉積、清潔(例如SRD)和熱處理循環。 As seen in Figures 1 and 7, the ECD seed deposition and backflow steps can be repeated to ensure completion of filling the part with ECD seed crystals. In this regard, the processes described herein can include one or more ECD seed deposition, cleaning (eg, SRD), and heat treatment cycles.

參照圖1，圖示了反流製程100和由所述反流製程產生的示例性部件。工件112在示例性實施方式中可為含有至少一個部件122的晶體矽工件上的電媒體材料。在示例性步驟102中，部件122襯有阻擋層114和種晶層115。在示例性步驟104中，工件112的部件122已接收種晶層115上的一層ECD種晶材料116。在示例性退火步驟106中，在適當溫度下使工件退火以誘導示例性反流步驟108促進部分填充或完全填充。在退火步驟期間，ECD種晶材料116流到部件122中以形成填充物118，同時如果對工件112或包括在工件112中的部件有不利影響的話使得該不利影響最小。在示例性實施方式中，可重複ECD種晶沉積步驟104、退火步驟106和反流步驟108以獲得填充物118的所期望特性。重複步驟的次數可取決於結構。一旦填充物118達到的期望的尺寸，則可使用示例性覆蓋步驟110來完成將額外材料120沉積在部件之上的製程，以為額外工件112處理做準備。 Referring to Figure 1, a reverse flow process 100 and exemplary components produced by the reverse flow process are illustrated. The workpiece 112 may be an electrically conductive material on a crystalline tantalum workpiece containing at least one component 122 in an exemplary embodiment. In the exemplary step 102, the component 122 is lined with a barrier layer 114 and a seed layer 115. In the exemplary step 104, the component 122 of the workpiece 112 has received a layer of ECD seed material 116 on the seed layer 115. In an exemplary annealing step 106, the workpiece is annealed at an appropriate temperature to induce an exemplary backflow step 108 to promote partial or full filling. During the annealing step, the ECD seed material 116 flows into the component 122 to form the filler 118 while minimizing this adverse effect if the workpiece 112 or components included in the workpiece 112 are adversely affected. In an exemplary embodiment, the ECD seed deposition step 104, the annealing step 106, and the reflux step 108 may be repeated to obtain the desired characteristics of the filler 118. The number of iterations can depend on the structure. Once the filler 118 reaches the desired size, an exemplary overlay step 110 can be used to complete the process of depositing additional material 120 over the component to prepare for additional workpiece 112 processing.

現參照圖2，提供處理流程實例，其中本案內容的實 施方式可結合其他工件表面沉積製程使用並融入到其他工件表面沉積製程中。將首先描述先前開發的製程。第一，TSV製程包括阻擋層、種晶層和傳統ECD填充的沉積。第二，ECD種晶(也稱為SLE)製程包括阻擋層、種晶層、ECD種晶層和傳統ECD填充的沉積。第三，伴隨襯墊的ECD種晶(SLE)製程包括阻擋層、襯墊層、種晶層、ECD種晶層和傳統ECD填充的沉積。第四，伴隨二次種晶的ECD種晶(SLE)製程包括阻擋層、二次種晶層、ECD種晶層和傳統ECD填充的沉積。第五，伴隨二次種晶和快閃物的ECD種晶(SLE)製程包括阻擋層、二次種晶層、快閃層、ECD種晶層和傳統ECD填充的沉積。第六，ECD種晶(DOB)製程包括阻擋層、ECD種晶層和傳統ECD填充的沉積。所述ECD種晶製程是DOB製程是因為沒有沉積二次種晶、襯墊或種晶層；相反，ECD種晶層直接沉積在可電鍍的(platable)阻擋層上。 Referring now to Figure 2, an example of a process flow is provided, wherein the content of the case is The application can be combined with other workpiece surface deposition processes and incorporated into other workpiece surface deposition processes. The previously developed process will be described first. First, the TSV process includes deposition of barrier layers, seed layers, and conventional ECD fills. Second, the ECD seed crystal (also known as SLE) process includes deposition of barrier layers, seed layers, ECD seed layers, and conventional ECD fills. Third, the ECD seeding (SLE) process associated with the liner includes deposition of a barrier layer, a liner layer, a seed layer, an ECD seed layer, and a conventional ECD fill. Fourth, the ECD seed crystal (SLE) process with secondary seeding includes deposition of a barrier layer, a secondary seed layer, an ECD seed layer, and a conventional ECD fill. Fifth, the ECD seeding (SLE) process with secondary seed crystals and flashes includes deposition of barrier layers, secondary seed layers, flash layers, ECD seed layers, and conventional ECD fills. Sixth, the ECD seed crystal (DOB) process includes deposition of barrier layers, ECD seed layers, and conventional ECD fills. The ECD seeding process is a DOB process because no secondary seed, pad or seed layer is deposited; instead, the ECD seed layer is deposited directly on the plateable barrier.

仍參考圖2，現將描述根據本案內容實施方式的製程。第七，ECD種晶附加(DOB)製程包括阻擋層、ECD種晶「附加」沉積物和傳統ECD填充及/或覆蓋的沉積。與上述第六實例相同，所述ECD種晶附加(DOB)製程也是DOB製程，是因為沒有沉積二次種晶、襯墊或種晶層；相反，ECD種晶層直接沉積在可電鍍的阻擋層上。第八，ECD種晶附加製程包括阻擋層、二次種晶層、ECD種晶「附加」沉積物和傳統ECD填充及/或覆蓋的沉積。第九，沒有ECD的ECD種晶附加製程包括阻擋層、二次種晶層、和ECD種晶「附加」沉積物的沉積。第十，沒有二次種晶的ECD種晶附加製程包括阻擋 層、種晶層、ECD種晶「附加」沉積物和傳統ECD填充及/或覆蓋的沉積。第十一，伴隨襯墊及種晶的ECD種晶附加製程包括阻擋層、襯墊層、種晶層、ECD種晶「附加」沉積物及傳統ECD填充及/或覆蓋的沉積。 Still referring to FIG. 2, a process in accordance with an embodiment of the present disclosure will now be described. Seventh, the ECD seed crystal addition (DOB) process includes barrier layers, ECD seed crystal "additional" deposits, and conventional ECD fill and/or overlay deposition. As with the sixth example above, the ECD seed addition (DOB) process is also a DOB process because no secondary seed, pad or seed layer is deposited; instead, the ECD seed layer is deposited directly on the electroplatable barrier. On the floor. Eighth, the ECD seed crystal addition process includes a barrier layer, a secondary seed layer, an ECD seed crystal "additional" deposit, and a conventional ECD fill and/or overlay deposition. Ninth, the ECD seed crystal addition process without ECD includes deposition of barrier layers, secondary seed layers, and ECD seed crystal "additional" deposits. Tenth, the ECD seed crystal addition process without secondary seeding includes blocking Layer, seed layer, ECD seed crystal "additional" deposits and conventional ECD fill and/or overlay deposition. Eleventh, ECD seeding additional processes associated with liners and seed crystals include barrier layers, liner layers, seed layers, ECD seed crystal "additional" deposits, and conventional ECD fill and/or overlay deposition.

參考圖7，提供根據本案內容實施方式的另一示例性製程。在第一步驟中，在ECD種晶步驟前熱處理或退火具有阻擋層及二次種晶層的工件以去除任何表面氧化物、使沉積物緻密並改善沉積物的表面性質。圖7中所示的種晶層為二次種晶層，但應理解，所述二次種晶層也可為種晶層或襯墊層與種晶層的堆疊膜。合適的熱處理條件或退火條件可包括有可能在合成氣體或純氫中在介於約200℃到約400℃之間的溫度歷時約一(1)分鐘到約十(10)分鐘。如上文所述，可在惰性氣體(例如，N₂、氬(Ar)或氦(He))中替代性地熱處理工件。還可使用還原性氣體，例如，氨(NH₃)。 Referring to Figure 7, another exemplary process in accordance with an embodiment of the present disclosure is provided. In the first step, the workpiece having the barrier layer and the secondary seed layer is heat treated or annealed prior to the ECD seeding step to remove any surface oxide, densify the deposit, and improve the surface properties of the deposit. The seed layer shown in FIG. 7 is a secondary seed layer, but it should be understood that the second seed layer may also be a seed layer or a stacked film of a liner layer and a seed layer. Suitable heat treatment conditions or annealing conditions may include the possibility of a temperature between about 200 ° C and about 400 ° C in the synthesis gas or pure hydrogen for about one (1) minute to about ten (10) minutes. As described above, the workpiece can be alternatively heat treated in an inert gas such as N ₂ , argon (Ar) or helium (He). A reducing gas such as ammonia (NH ₃ ) can also be used.

在第二步驟中，將工件轉移到沉積腔室用於ECD種晶層的共形沉積。所沉積薄膜的厚度根據金屬沉積物的期望性質和特徵尺寸而變化。 In a second step, the workpiece is transferred to a deposition chamber for conformal deposition of the ECD seed layer. The thickness of the deposited film varies depending on the desired properties and feature sizes of the metal deposit.

在第三步驟中，旋轉工件、用去離子(DI)水沖洗工件並乾燥(SRD)工件，以清潔工件。 In the third step, the workpiece is rotated, the workpiece is rinsed with deionized (DI) water and the workpiece is dried (SRD) to clean the workpiece.

在第四步驟中，在200℃到400℃的範圍內的溫度下熱處理或退火工件以使金屬反流到部件中。 In the fourth step, the workpiece is heat treated or annealed at a temperature in the range of 200 ° C to 400 ° C to reflux the metal into the component.

在第五步驟中，工件可經歷步驟2、步驟3和步驟4的有順序再處理，直到獲得工件上部件的期望填充輪廓為止。 In a fifth step, the workpiece can undergo sequential reprocessing of steps 2, 3 and 4 until a desired fill profile of the component on the workpiece is obtained.

在第六步驟中，使工件經受傳統的ECD酸性化學品沉積以達到期望的厚度。接著為後續處理而準備好工件，所述後續處理可包括額外熱處理、化學機械拋光和其他製程。 In a sixth step, the workpiece is subjected to conventional ECD acidic chemical deposition to achieve the desired thickness. The workpiece is then prepared for subsequent processing, which may include additional heat treatment, chemical mechanical polishing, and other processes.

製程的替代實施方式可包括本文已描述步驟的變型，且所述步驟、組合和排列可另外融入以下額外步驟。本案內容中設想，可在具有或沒有有機添加劑(例如，抑制劑、促進劑及/或調平劑)的在例如約4到約10、約3到約10或約2到約11的pH範圍內的鹼性溶液或酸性溶液中執行共形「種晶」沉積。可使用多個沉積步驟、清潔(例如SRD)步驟和熱處理步驟或退火步驟來執行反流，或可在單個步驟中然後通過在適當溫度下的熱處理或退火進行反流。 Alternative embodiments of the process may include variations of the steps already described herein, and the steps, combinations, and permutations may additionally incorporate the following additional steps. It is contemplated in the context that a pH range of, for example, from about 4 to about 10, from about 3 to about 10, or from about 2 to about 11 can be used with or without organic additives (e.g., inhibitors, promoters, and/or leveling agents). Conformal "seed" deposition is performed in an alkaline or acidic solution. The reverse flow may be performed using a plurality of deposition steps, a cleaning (eg, SRD) step, and a heat treatment step or an annealing step, or may be performed in a single step and then by heat treatment or annealing at a suitable temperature.

ECD種晶「附加」沉積對小部件的產生很重要，這是因為熱處理步驟或退火步驟及反流步驟提供實質無空隙的種晶沉積。如下文更詳細描述，部件中的空隙形成增加電阻(降低裝置的電氣性能)並使互連體的可靠性退化。 The "additional" deposition of ECD seed crystals is important for the generation of small parts because the heat treatment step or the annealing step and the reflux step provide substantial void-free seed deposition. As described in more detail below, the void formation in the component creates an increase in electrical resistance (reducing the electrical performance of the device) and degrades the reliability of the interconnect.

通過使用本文述及之製程實現其他優點。在這一方面，單個工具(例如，由Applied Materials,Inc.製造的Raider®電化學沉積、清潔(例如SRD)和熱處理或退火工具)可用於ECD種晶沉積步驟(或在重複時的多個ECD種晶沉積步驟)、清潔步驟(或在重複時的多個清潔步驟)、熱處理步驟(或在重複時的多個熱處理步驟)並用於最終ECD步驟。此外，結果顯示使用本文述及之製程對小部件的實質無空隙的間隙填充，導致較低的電阻及阻容(RC)延遲值。此外，本文述及之製程提供填充近似小於約30nm的級別的小部件的能力，然 而使用傳統製程可能無法實現填充。ECD種晶「附加」沉積在大於30nm的部件中也是有利的。 Other advantages are achieved through the use of the processes described herein. In this regard, a single tool (eg, Raider® electrochemical deposition, cleaning (eg, SRD) and heat treatment or annealing tools manufactured by Applied Materials, Inc.) can be used for ECD seed deposition steps (or multiple when repeating) ECD seed deposition step), cleaning step (or multiple cleaning steps at the time of repetition), heat treatment step (or multiple heat treatment steps at the time of repetition) and used in the final ECD step. In addition, the results show that the substantially void-free gap fill of the small parts using the process described herein results in lower resistance and RC delay values. In addition, the processes described herein provide the ability to fill small parts of the order of less than about 30 nm, Filling may not be possible with traditional processes. It is also advantageous that the ECD seed crystal "additional" is deposited in a component larger than 30 nm.

如上文所述，可施加ECD種晶的一或多個層，然後將所述ECD種晶的一或多個層暴露於高溫以填充更深的部件或高深寬比的部件。參照圖8，提供兩個示例性ECD種晶附加製程(包括退火步驟)(晶片4及晶片5)，與用於具有約30nm的部件直徑的鑲嵌部件中的沉積的兩個傳統ECD種晶製程(沒有退火步驟)[晶片1及晶片7]相比。參照圖9到圖11，結果顯示，與ECD種晶的單個步驟(即，沒有退火步驟)相比，ECD種晶在鑲嵌部件中的增量沉積(incremental deposition)導致電阻和阻容(RC)延遲值降低，其中一些或全部沉積步驟之後執行退火步驟。 As described above, one or more layers of ECD seed crystals can be applied and then one or more layers of the ECD seed crystals are exposed to high temperatures to fill deeper components or high aspect ratio components. Referring to Figure 8, two exemplary ECD seed crystal addition processes (including annealing steps) (wafer 4 and wafer 5) are provided, and two conventional ECD seeding processes for deposition in a damascene component having a component diameter of about 30 nm are provided. (No annealing step) [Comparative wafer 1 and wafer 7]. Referring to Figures 9 through 11, the results show that the incremental deposition of ECD seed crystals in the inlay component results in resistance and resistance (RC) compared to a single step of ECD seeding (i.e., no annealing step). The retardation value is reduced, with some or all of the deposition steps followed by an annealing step.

所有晶片1、晶片4、晶片5及晶片7包括以下初始製程條件：沉積10Å ALD TaN阻擋層，接著沉積30Å CVD Ru的種晶層(二次種晶)，並然後使工件經受300℃下的退火與10分鐘的氮鈍化。 All wafer 1, wafer 4, wafer 5, and wafer 7 include the following initial process conditions: depositing a 10 Å ALD TaN barrier layer, followed by deposition of a 30 Å CVD Ru seed layer (secondary seed), and then subjecting the workpiece to 300 ° C Annealed with 10 minutes of nitrogen passivation.

然後通過分別在2.1amp-min和0.5amp-min下的ECD銅種晶的單個步驟電鍍晶片1和晶片7，然後使用傳統的酸性ECD銅沉積製程使晶片1和晶片7完成填充和覆蓋。所得的工件產生厚的ECD銅種晶(晶片1)和薄的ECD銅種晶(晶片7)。 Wafer 1 and wafer 7 were then plated through a single step of ECD copper seeding at 2.1 amp-min and 0.5 amp-min, respectively, and then wafer 1 and wafer 7 were filled and covered using a conventional acidic ECD copper deposition process. The resulting workpiece produced thick ECD copper seed crystals (wafer 1) and thin ECD copper seed crystals (wafer 7).

使晶片4和晶片5經受ECD種晶「附加」條件。晶片4包括三個ECD銅種晶步驟，每個步驟在0.7amp-min下，其中前兩個步驟中的每一個步驟之後都有300℃退火並在第三步 驟後沒有退火，接著使用傳統的酸性ECD銅沉積製程完成填充和覆蓋。與具有接近30nm的部件尺寸的晶片4相關聯的顯微圖像提供在圖12中。儘管在第三步驟後沒有退火，但應理解，最終退火步驟也在本案內容的範圍內。 The wafer 4 and wafer 5 are subjected to ECD seed crystal "additional" conditions. Wafer 4 includes three ECD copper seeding steps, each step at 0.7 amp-min, wherein each of the first two steps is followed by 300 ° C annealing and in the third step There is no annealing after the step, followed by filling and covering using a conventional acidic ECD copper deposition process. A microscopic image associated with wafer 4 having a component size approaching 30 nm is provided in FIG. Although there is no annealing after the third step, it should be understood that the final annealing step is also within the scope of the present disclosure.

晶片5包括四個ECD銅種晶步驟，每個步驟在0.5amp-min下，其中前三個步驟中的每一個步驟之後都有300℃退火並在第四步驟後沒有退火，接著使用傳統的酸性ECD銅沉積製程完成填充和覆蓋。像晶片4一樣，應理解，最終退火步驟也在本案內容的範圍內。 Wafer 5 includes four ECD copper seeding steps, each step at 0.5 amp-min, wherein each of the first three steps has an annealing of 300 ° C and no annealing after the fourth step, followed by conventional The acid ECD copper deposition process completes the filling and coverage. Like wafer 4, it should be understood that the final annealing step is also within the scope of this disclosure.

現參照圖9到圖11，提供晶片1、晶片4、晶片5和晶片7的比較電阻及RC延遲資料。在圖9到圖11中可見，與使用先前開發的技術形成的工件(晶片1及晶片7)相比，根據本文所述方法使用ECD種晶「附加」形成的工件(晶片4及晶片5)具有顯著降低的電阻及電阻/電容(RC)延遲。 Referring now to Figures 9 through 11, comparative resistance and RC delay data for wafer 1, wafer 4, wafer 5, and wafer 7 are provided. It can be seen in Figures 9 through 11 that the workpieces (wafer 4 and wafer 5) formed using the ECD seed crystal "addition" according to the method described herein are compared to the workpieces formed using the previously developed techniques (wafer 1 and wafer 7). Has significantly reduced resistance and resistance/capacitance (RC) delay.

參照圖9及圖10，與使用ECD種晶形成但沒有ECD種晶加退火循環的工件相比，根據本案內容實施方式形成的工件實現在以下範圍內的電阻值降低：0到約40%、大於0到約30%、大於0到約20%、約10%到約20%及約10%到約15%。 Referring to FIGS. 9 and 10, the workpiece formed according to the embodiment of the present invention achieves a reduction in resistance value in the following range: 0 to about 40%, compared to a workpiece formed using ECD seed crystals but without an ECD seed crystal addition annealing cycle. More than 0 to about 30%, greater than 0 to about 20%, from about 10% to about 20%, and from about 10% to about 15%.

參照圖11，與使用ECD種晶形成但沒有ECD種晶附加退火循環的工件相比，根據本案內容實施方式形成的工件實現RC延遲值降低。較低RC延遲可導致對部件中的低K金屬間電媒體的較低損傷或沒有損傷。 Referring to Figure 11, the workpiece formed in accordance with an embodiment of the present disclosure achieves a reduction in RC retardation value as compared to a workpiece formed using ECD seed crystals without an ECD seed crystal additional annealing cycle. Lower RC delays can result in lower or no damage to the low K intermetal dielectric in the component.

根據本案內容的其他實施方式，提供用於在具有高薄片電阻的工件上電化學沉積的系統和方法。回到圖1，隨著 部件大小變得越來越小(例如，小於30nm)，組成互連體的薄沉積物層趨向於具有非常高的薄層電阻。高的薄層電阻會在隨後金屬層的電化學沉積(ECD)中(特別是當使用「乾」電氣接觸件時)產生困難。本案內容的實施方式可應用到在工件上的ECD種晶、ECD種晶附加(包括如上述及之退火步驟)、ECD填充和覆蓋的ECD沉積或任何其他ECD沉積製程。 In accordance with other embodiments of the present disclosure, systems and methods are provided for electrochemical deposition on workpieces having high sheet resistance. Go back to Figure 1, along with As component sizes become smaller (eg, less than 30 nm), the thin deposit layers that make up the interconnect tend to have very high sheet resistance. High sheet resistance can cause difficulties in subsequent electrochemical deposition (ECD) of the metal layer (especially when using "dry" electrical contacts). Embodiments of the present disclosure can be applied to ECD seed crystals on a workpiece, ECD seed crystal addition (including annealing steps as described above), ECD fill and overlay ECD deposition, or any other ECD deposition process.

在工件上執行ECD金屬沉積之前，例如使用PVD、CVD、ALD或無電沉積製程之一將金屬薄種晶層形成在微電子工件的表面上。如上所述，種晶層可為(1)種晶層(作為非限制實例，是PVD銅種晶層)。種晶層可為金屬層，例如，銅、鈷、鎳、金、銀、錳、錫、鋁、釕和以上各物的合金。種晶層還可為共鍍(co-plated)金屬層，例如CoCu或MnCu混合物、固溶體(solid solution)或合金。種晶層還可為(2)襯墊層與種晶層(作為非限制實例，是CVD Ru襯墊層與PVD銅種晶層)的堆疊膜，或(3)二次種晶層(作為非限制實例，是CVD或ALD Co二次種晶層)。然而，應理解，本案內容也涵蓋沉積這些示例性種晶層的其他方法。 Prior to performing ECD metal deposition on the workpiece, a thin metal seed layer is formed on the surface of the microelectronic workpiece, such as using one of a PVD, CVD, ALD, or electroless deposition process. As described above, the seed layer may be (1) a seed layer (as a non-limiting example, a PVD copper seed layer). The seed layer may be a metal layer such as copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, antimony, and alloys of the above. The seed layer may also be a co-plated metal layer, such as a CoCu or MnCu mixture, a solid solution or an alloy. The seed layer may also be (2) a liner layer and a seed layer (as a non-limiting example, a stacked film of a CVD Ru liner layer and a PVD copper seed layer), or (3) a secondary seed layer (as A non-limiting example is a CVD or ALD Co secondary seed layer). However, it should be understood that the present disclosure also encompasses other methods of depositing these exemplary seed layers.

在已根據上述實例中的一個實例沉積種晶層之後，部件可包括SLE層(或ECD種晶)。參見例如用於說明包括PVD種晶沉積及ECD種晶沉積的製程的圖4。參見例如用於說明包括二次種晶沉積及ECD種晶沉積的製程的圖5。如圖4及圖5中所見，ECD種晶可為共形沉積層。 After the seed layer has been deposited according to one of the above examples, the component may include an SLE layer (or ECD seed crystal). See, for example, Figure 4 for illustrating a process including PVD seed deposition and ECD seed deposition. See, for example, Figure 5 for illustrating a process including secondary seed deposition and ECD seed deposition. As seen in Figures 4 and 5, the ECD seed crystal can be a conformal deposited layer.

如上所論述的那樣，通常使用包括濃度很低的銅乙二胺(EDA)絡合物的鹼性化學品沉積ECD銅種晶。還可使用 其他銅絡合物(例如，檸檬酸銅、酒石酸銅和尿素銅等)沉積ECD銅種晶，且可在約2到約11、約3到約10的pH範圍內或在約4到約10的pH範圍內沉積ECD銅種晶。 As discussed above, ECD copper seed crystals are typically deposited using an alkaline chemical comprising a very low concentration of copper ethylene diamine (EDA) complex. Can also be used Other copper complexes (eg, copper citrate, copper tartrate, and urea copper, etc.) deposit ECD copper seed crystals and may range from about 2 to about 11, from about 3 to about 10, or from about 4 to about 10 ECD copper seed crystals are deposited in the pH range.

在已根據上述實例中的一個實例沉積種晶層之後，能將種晶層用作為陰極以使用ECD沉積製程將金屬層沉積到工件上，同時電極用作用於金屬沉積的陽極。ECD金屬沉積物可為ECD種晶、ECD填充或ECD覆蓋沉積物。雖然通常使用鹼性化學品沉積ECD種晶，但例如可使用酸性沉積化學品在工件中執行傳統的ECD填充和覆蓋。傳統的ECD銅酸性化學品可包括例如硫酸銅、硫酸、甲磺酸、鹽酸和有機添加劑(例如，促進劑、抑制劑及調平劑)。 After the seed layer has been deposited according to one of the above examples, the seed layer can be used as a cathode to deposit a metal layer onto the workpiece using an ECD deposition process while the electrode is used as an anode for metal deposition. The ECD metal deposit can be an ECD seed crystal, an ECD fill or an ECD overlay deposit. While ECD seed crystals are typically deposited using alkaline chemicals, conventional ECD fills and overlays can be performed in the workpiece using, for example, acidic deposition chemicals. Conventional ECD copper acid chemicals can include, for example, copper sulfate, sulfuric acid, methanesulfonic acid, hydrochloric acid, and organic additives (eg, accelerators, inhibitors, and leveling agents).

在製造微電子裝置中使用的ECD工具常常具有數個單晶片電鍍腔室。典型的腔室包括用於存放ECD化學品的容器、在容器內以接觸化學品的陽極和具有接觸元件的支撐機構，接觸元件具有接合種晶層的電氣接觸件。這些電氣接觸件耦接至電源以施加電壓至種晶層。在操作中，將工件的表面浸沒到化學品中以使陽極與種晶層建立電場，電場使工件的前表面處的擴散層中的金屬離子電鍍到種晶層上。 ECD tools used in the fabrication of microelectronic devices often have several single wafer plating chambers. A typical chamber includes a container for storing ECD chemicals, an anode within the container to contact the chemical, and a support mechanism having contact elements having electrical contacts that engage the seed layer. These electrical contacts are coupled to a power source to apply a voltage to the seed layer. In operation, the surface of the workpiece is immersed in the chemical to establish an electric field between the anode and the seed layer, and the electric field causes metal ions in the diffusion layer at the front surface of the workpiece to be electroplated onto the seed layer.

接觸元件的結構會影響電鍍的金屬層的均勻性，因為在種晶層各處的電流的分佈(「電流密度」)影響在微電子工件的表面各處的電鍍速率(plating rate)。影響電流密度的一個因素是圍繞工件周邊的電氣接觸件的分佈。通常，能使用大量分離的電氣接觸件來接觸靠近工件周邊的種晶層以提供圍繞工件周邊的電流的均勻分佈。 The structure of the contact elements affects the uniformity of the plated metal layer because the distribution of current across the seed layer ("current density") affects the plating rate throughout the surface of the microelectronic workpiece. One factor that affects current density is the distribution of electrical contacts around the perimeter of the workpiece. In general, a large number of separate electrical contacts can be used to contact the seed layer near the perimeter of the workpiece to provide a uniform distribution of current around the perimeter of the workpiece.

一種類型的接觸元件是具有多個被密封而與ECD化學品隔絕的電氣接觸件的「乾接觸」元件。例如，美國專利第5227041號(頒發給Brogden等人)描述乾接觸ECD結構，所述乾接觸ECD結構具有用於浸沒到ECD化學品內的基礎構件(base member)、被安置成與基礎構件中的孔相鄰的密封環、佈置在圍繞密封環的圓內的多個接觸件和附裝至基礎構件的蓋。在操作中，將工件放置在基礎構件中以使工件的前表面接合接觸件和密封環。當工件的前表面浸沒在ECD化學品中時，密封環防止ECD化學品接合基礎構件內部的接觸件。 One type of contact element is a "dry contact" element having a plurality of electrical contacts that are sealed from the ECD chemical. For example, U.S. Patent No. 5,216, 041 (issued to Brogden et al.) describes a dry contact ECD structure having a base member for immersion into an ECD chemical, placed in a base member The holes are adjacent to the seal ring, the plurality of contacts disposed within the circle surrounding the seal ring, and the cover attached to the base member. In operation, the workpiece is placed in the base member such that the front surface of the workpiece engages the contact and the seal ring. The seal ring prevents the ECD chemical from engaging the contacts inside the base member when the front surface of the workpiece is submerged in the ECD chemical.

另一類型的接觸元件是「濕接觸」元件，其中允許電氣接觸件接觸ECD化學品。例如，美國專利第7645366號(頒發給Hanson等人)描述浸沒在ECD化學品內的濕接觸元件。 Another type of contact element is a "wet contact" element in which the electrical contacts are allowed to contact the ECD chemical. For example, U.S. Patent No. 7,645,366 (issued to Hanson et al.) describes a wet contact element that is immersed in an ECD chemical.

當種晶層的薄層電阻高時，難以在種晶層上電化學沉積金屬。在這方面，非常薄的金屬層的薄層電阻與厚度的約2次方或更高次方成反比。例如，厚度介於50埃與300埃之間的銅膜的薄層電阻在1.2歐姆/方與45歐姆/方之間變化且與膜厚度的約2.2次方成反比。在一個非限制實例中，10埃釕種晶層的薄層電阻能夠大於600歐姆/方。相比之下，50埃釕種晶層的薄層電阻小於100歐姆/方。 When the sheet resistance of the seed layer is high, it is difficult to electrochemically deposit metal on the seed layer. In this respect, the sheet resistance of a very thin metal layer is inversely proportional to the thickness of about 2 or higher. For example, a sheet resistance of a copper film having a thickness between 50 angstroms and 300 angstroms varies between 1.2 ohms/square and 45 ohms/square and is inversely proportional to a film thickness of about 2.2. In one non-limiting example, the sheet resistance of the 10 angstrom seed layer can be greater than 600 ohms/square. In contrast, the sheet resistance of the 50 angstrom seed layer is less than 100 ohms/square.

此外，非常薄的膜的薄層電阻還能夠根據沉積方法、沉積後處理(post-deposition treatment)和製程步驟之間的時間而變化。在這方面，通過CVD或ALD方法沉積的金屬趨向於具有比通過PVD或電鍍手段沉積的金屬更高的薄層電阻。 這種差別可以是一或多個因素的結果，例如較高的雜質水平、不同的顆粒結構和與大氣的氧或濕氣的反應。對於Co、Ru、TiN、Mn和許多其他金屬也顯現這種現象。例如，與相同厚度的PVD Co膜具有較低值相比，測量CVD Co膜為高於1000歐姆/方。 In addition, the sheet resistance of a very thin film can also vary depending on the time between the deposition method, the post-deposition treatment, and the process steps. In this regard, metals deposited by CVD or ALD methods tend to have higher sheet resistance than metals deposited by PVD or electroplating. This difference can be the result of one or more factors, such as higher impurity levels, different particle structures, and reactions with atmospheric oxygen or moisture. This phenomenon also occurs for Co, Ru, TiN, Mn, and many other metals. For example, the CVD Co film is measured to be above 1000 ohms/square compared to a PVD Co film of the same thickness having a lower value.

電化學沉積需要經由電鍍表面的電流傳導(current conduction)。電流提供那些減少電鍍金屬的離子的電子以形成金屬片或電鍍膜。沉積速率與電流成比例。因此，為了適應和維持足夠的沉積速率，必須向工件供給大電流。系統中的電路使用陽極、電解液和陰極。通常工件為陰極，且隨著電流從陽極流至陰極，電子從陰極轉移至電解質中的離子以還原那些離子並在陰極上沉積膜。根據製程條件和將要沉積的金屬，電流水平能夠變化，但在大塊沉積(bulk deposition)期間電流水平通常在10A與40A之間。 Electrochemical deposition requires current conduction through the plated surface. The current provides electrons that reduce the ions of the plated metal to form a metal sheet or a plated film. The deposition rate is proportional to the current. Therefore, in order to accommodate and maintain a sufficient deposition rate, a large current must be supplied to the workpiece. The circuits in the system use an anode, an electrolyte, and a cathode. Typically the workpiece is a cathode and as current flows from the anode to the cathode, electrons are transferred from the cathode to the ions in the electrolyte to reduce those ions and deposit a film on the cathode. The current level can vary depending on the process conditions and the metal to be deposited, but the current level is typically between 10A and 40A during bulk deposition.

借助接觸環來實現與工件的電氣接觸。已有技術中存在用於接觸環的各種設計。有四種主要類別的接觸環：線(或斷路接觸(open contact))接觸環、密封接觸環、遮罩式(shielded)接觸環和嵌入式(embedded)接觸環。在非密封(unsealed)接觸環的情況下，將工件與環之間的電氣接觸件浸沒在電解液中。在密封環的情況下，密封使接觸件與溶液隔開。因此密封環的電氣接觸件為「乾」的而(所有排列(permutation)的)非密封環中的電氣接觸件為「濕」的。 Electrical contact with the workpiece is achieved by means of a contact ring. Various designs for contact rings exist in the prior art. There are four main categories of contact rings: wire (or open contact) contact rings, sealed contact rings, shielded contact rings, and embedded contact rings. In the case of an unsealed contact ring, the electrical contact between the workpiece and the ring is immersed in the electrolyte. In the case of a sealing ring, the seal separates the contact from the solution. Thus the electrical contacts of the seal ring are "dry" and the electrical contacts in the (permutation) non-seal ring are "wet".

密封接觸件與非密封接觸件之間明顯的區別是，在密封接觸件的情況下，沒有材料電鍍或沉積在密封的區域內 ，因為在電化學沉積製程期間密封的區域沒有暴露給電媒體。圖13B中提供了關於「乾」接觸件的示例性工件沉積方案。在這方面，第一導電層或種晶層沉積在基板上，且第二導電層或ECD種晶層沉積在第一導電層上。能夠從圖13B中看到，在接觸件位置處的第二導電層中有空隙。 The obvious difference between a sealed contact and a non-sealed contact is that in the case of a sealed contact, no material is plated or deposited in the sealed area. Because the area sealed during the electrochemical deposition process is not exposed to the electrical medium. An exemplary workpiece deposition scheme for a "dry" contact is provided in Figure 13B. In this aspect, the first conductive layer or seed layer is deposited on the substrate, and the second conductive layer or ECD seed layer is deposited on the first conductive layer. As can be seen from Figure 13B, there is a void in the second conductive layer at the location of the contacts.

相比之下，非密封接觸件在暴露至電解質的工件的整個表面上產生沉積或電鍍，所述整個表面包括接觸區域。圖13A中提供了關於「濕」接觸件的示例性工件沉積圖。在這方面，第一導電層或種晶層沉積在基板上，且第二導電層或ECD種晶層沉積在種晶層上。與圖13B中的工件不同，在圖13A中工件上的接觸件位置處，第二導電層中沒有空隙。 In contrast, a non-sealed contact creates a deposit or plating on the entire surface of a workpiece that is exposed to the electrolyte, the entire surface including the contact area. An exemplary workpiece deposition map for a "wet" contact is provided in Figure 13A. In this aspect, a first conductive layer or seed layer is deposited on the substrate, and a second conductive layer or ECD seed layer is deposited on the seed layer. Unlike the workpiece in Fig. 13B, there is no void in the second conductive layer at the contact position on the workpiece in Fig. 13A.

如以上所論述的那樣，由不同於銅的金屬製成的種晶層或者薄種晶層趨向於具有高薄片電阻。並且，如以上所解釋的那樣，通到陰極的電流必須通過種晶層。有用於ECD的至少四種不同接觸件配置，列舉如下。第一，接觸件可來自密封環，為此所有電流必須流過薄種晶且在密封環的周邊外側不發生沉積。對於示例性的密封接觸環配置，參考美國專利第5227041號(頒發給Brogden等人)。 As discussed above, a seed layer or a thin seed layer made of a metal other than copper tends to have a high sheet resistance. Also, as explained above, the current to the cathode must pass through the seed layer. There are at least four different contact configurations for ECD, listed below. First, the contacts can come from the seal ring, for which all current must flow through the thin seed crystals and no deposition occurs outside the perimeter of the seal ring. For an exemplary sealed contact ring configuration, reference is made to U.S. Patent No. 5,207,041 (issued to Brogden et al.).

第二，接觸件可由非密封環製成，為此沉積發生在工件的整個表面上。對於示例性的非密封接觸環配置，參考美國專利公開檔第2013/0134035號(頒發給Harris)。 Second, the contacts can be made of a non-seal ring for which deposition occurs over the entire surface of the workpiece. For an exemplary unsealed contact ring configuration, reference is made to U.S. Patent Publication No. 2013/0134035 (issued to Harris).

第三，在另一實施方式中，非密封接觸環可具有「遮罩式」接觸件以在系統中提供額外的控制，例如，控制系統中氣泡的產生及/或化學品的流動。 Third, in another embodiment, the unsealed contact ring can have "masked" contacts to provide additional control in the system, such as controlling the generation of bubbles and/or the flow of chemicals in the system.

第四，接觸件可由具有嵌入式接觸件的密封環製成。大體將嵌入式接觸件安置在密封環的內部以使工件的外周邊緣保持乾燥。金屬接觸件可要麼從密封件伸出要麼與密封件齊平以使金屬接觸件的頂端接觸工件和密封環周邊內的化學品溶液。在這第三種配置中，在密封環周邊外的乾區域上沒有發生電化學沉積；但是，在發生反應時，接觸件的頂端暴露給電解質和正在被電化學沉積的膜。 Fourth, the contacts can be made of a sealing ring with embedded contacts. The embedded contact is generally placed inside the seal ring to keep the peripheral edge of the workpiece dry. The metal contact may either extend from the seal or be flush with the seal such that the top end of the metal contact contacts the chemical solution within the periphery of the workpiece and the seal ring. In this third configuration, no electrochemical deposition occurs on the dry areas outside the perimeter of the seal ring; however, upon reaction, the tips of the contacts are exposed to the electrolyte and the film being electrochemically deposited.

高薄片電阻在工件上產生高熱條件。基本原理(first principles)計算和類比顯示，經過非常薄的種晶層(所述非常薄的種晶層的厚度在約1nm與10nm之間變化且薄層電阻從約1000歐姆/方變化到小於10歐姆/方)的功率損耗(power dissipation)可超過400W。例如，具有約10微歐姆-釐米的電阻率且在約40A的正常操作條件下運行的1.5nm厚的膜會損耗約100W。考慮到與薄膜性質和載荷子的分散有關的電阻率的增大，類比顯示這種膜的熱損耗可超過400W。此外，假設接觸件覆蓋工件周圍區域的50%，我們計算電流密度為約20MA/cm²。此電流密度值大幅超過薄膜的安培容量(ampacity)，根據國際半導體技術藍圖(International Technology Roadmap for Semiconductors,ITRS)，所述安培容量在2MA/cm²和3MA/cm²之間。假設絕熱條件，我們計算這種膜的加熱速率(dT/dt)會超過1億K/s。 High sheet resistance creates high heat conditions on the workpiece. The first principles calculations and analogy show that after a very thin seed layer (the thickness of the very thin seed layer varies between about 1 nm and 10 nm and the sheet resistance changes from about 1000 ohms/square to less than The power dissipation of 10 ohms/square can exceed 400W. For example, a 1.5 nm thick film having a resistivity of about 10 micro ohm-cm and operating at about 40 A of normal operating conditions would lose about 100 W. Considering the increase in resistivity associated with film properties and dispersion of charge carriers, the analogy shows that the heat loss of such films can exceed 400W. Furthermore, assuming that the contacts cover 50% of the area around the workpiece, we calculate a current density of about 20 MA/cm ² . This value is significantly more than the current density ampacity film (ampacity), according to the International Technology Roadmap for Semiconductors (International Technology Roadmap for Semiconductors, ITRS ), the capacity between 2MA / cm ² and 3MA / cm ² amperes. Assuming adiabatic conditions, we calculate that the heating rate (dT/dt) of this film will exceed 100 million K/s.

雖然所討論的膜並非在絕熱條件下操作，但沒有已知材料能耐受這樣高的加熱速率且沒有已知材料能驅散在足夠高的速率下產生的熱以防止快速局部加熱。在試驗中，發 明人發現局部加熱如此大以致在電化學沉積期間能夠損壞5nm Co膜的乾部分，例如，容易氧化或快速退化。在這樣高溫的情況下薄膜能夠氧化，引起開路和電化學製程的停止。因此，難以使用乾接觸件在包含具有高薄片電阻的導電層的工件上沉積金屬，特別是在電流或電流密度很大(例如超過3MA/cm²)的情況下。高薄片電阻可為大於10歐姆/方、50歐姆/方或100歐姆/方。 Although the membrane in question is not operated under adiabatic conditions, no known materials are able to withstand such high heating rates and no known materials are capable of dissipating heat generated at a sufficiently high rate to prevent rapid localized heating. In the test, the inventors found that the local heating is so large that it can damage the dry portion of the 5 nm Co film during electrochemical deposition, for example, easily oxidized or rapidly degraded. At such high temperatures, the film can oxidize, causing an open circuit and a stop in the electrochemical process. Therefore, it is difficult to deposit a metal on a workpiece including a conductive layer having a high sheet resistance using a dry contact, particularly in the case where the current or current density is large (for example, more than 3 MA/cm ² ). The high sheet resistance can be greater than 10 ohms/square, 50 ohms/square, or 100 ohms/square.

本案內容的實施方式涉及防止這樣的過度加熱。在接觸件暴露給電解質的情況下，電化學沉積的膜產生連接插腳與沉積在工件上的膜的連續膜。例如，在非密封環和嵌入式密封環的情況下，在接觸點處、附近和周圍發生膜的電化學沉積。在電化學沉積製程期間，隨著電化學沉積的膜變厚，膜的薄層電阻迅速降低且功率損耗快速下降到接近於零。此外，在接觸點處的液體提供額外的冷卻和對大氣的氧的遮罩，有效地防止種晶層的氧化。因為熱損耗快速降低，因此不發生種晶層的顯著加熱。 Embodiments of the present disclosure relate to preventing such overheating. In the case where the contacts are exposed to the electrolyte, the electrochemically deposited film creates a continuous film that connects the pins to the film deposited on the workpiece. For example, in the case of a non-seal ring and an embedded seal ring, electrochemical deposition of the film occurs at, near, and around the contact point. During the electrochemical deposition process, as the electrochemically deposited film becomes thicker, the sheet resistance of the film decreases rapidly and the power loss drops rapidly to near zero. In addition, the liquid at the point of contact provides additional cooling and a mask of oxygen to the atmosphere, effectively preventing oxidation of the seed layer. Since the heat loss is rapidly reduced, significant heating of the seed layer does not occur.

此外，能將電流曲線(current profile)調整為在初始步驟允許低電流沉積且隨著電阻下降允許較高電流沉積。因為熱損耗與I²成比例，因此低初始電流是避免種晶損傷的有效方式。在這樣的電流曲線中的電流在450mm晶片上能在約小於1A至約80A的範圍內變化。 In addition, the current profile can be adjusted to allow for low current deposition in the initial step and higher current deposition as the resistance drops. Since heat loss is proportional to I ² , low initial current is an effective way to avoid seed damage. The current in such a current curve can vary from less than about 1 A to about 80 A on a 450 mm wafer.

根據本案內容的實施方式，高薄片電阻在大於10歐姆/方、大於50歐姆/方、大於100歐姆/方等的範圍內。 According to an embodiment of the present disclosure, the high sheet resistance is in a range greater than 10 ohms/square, greater than 50 ohms/square, greater than 100 ohms/square, and the like.

根據本案內容的一個實施方式，ECD種晶層沉積在 具有高薄片電阻的種晶層上。 According to one embodiment of the present disclosure, the ECD seed layer is deposited on On a seed layer with high sheet resistance.

根據本案內容的另一實施方式，ECD層(例如，ECD填充或ECD覆蓋)沉積在具有高薄片電阻的種晶層上。 According to another embodiment of the present disclosure, an ECD layer (eg, ECD fill or ECD overlay) is deposited on a seed layer having a high sheet resistance.

根據本案內容的另一實施方式，ECD層(例如，ECD種晶、ECD填充或ECD覆蓋)沉積在具有高薄片電阻的ECD種晶層上。 According to another embodiment of the present disclosure, an ECD layer (eg, ECD seed crystal, ECD fill, or ECD cover) is deposited on an ECD seed layer having a high sheet resistance.

根據本案內容的實施方式，(將要在上面沉積的)ECD種晶層根據本案內容的其他實施方式可首先經受退火製程以至少部分填充部件或可為共形層。 In accordance with embodiments of the present disclosure, the ECD seed layer (to be deposited thereon) may be first subjected to an annealing process to at least partially fill the component or may be a conformal layer, in accordance with other embodiments of the present disclosure.

雖然已說明及描述說明性實施方式，但將理解，能在不背離本案內容的精神及範圍的情況下在本文中作出各種變化。 While the illustrative embodiments have been illustrated and described, it will be understood that various changes may be made herein without departing from the spirit and scope of the invention.

Claims (16)

一種用於至少部分填充工件上的部件的方法，該方法包括以下步驟：(a)取得包括一部件的工件，該部件中具有一第一導電層，其中該第一導電層為含有鈷、釕、或其組合之一種晶層，且其中該第一導電層的薄層電阻大於10歐姆/方；(b)藉由電化學沉積將一第二導電層直接沉積在該部件中之該第一導電層上，其中用來在電化學沉積處理中產生與該工件之電氣連接的電氣接觸件至少部分地浸沒在沉積化學品中，其中該第二導電層是通過電化學沉積所沉積的共形導電層；以及(c)熱處理該工件以使該第二導電層反流以至少部分填充該部件。 A method for at least partially filling a component on a workpiece, the method comprising the steps of: (a) obtaining a workpiece comprising a component having a first conductive layer therein, wherein the first conductive layer comprises cobalt, germanium Or a combination thereof, and wherein the first conductive layer has a sheet resistance greater than 10 ohms/square; (b) a first conductive layer deposited directly in the component by electrochemical deposition On the electrically conductive layer, wherein the electrical contacts for creating an electrical connection to the workpiece in the electrochemical deposition process are at least partially submerged in the deposition chemistry, wherein the second electrically conductive layer is conformed by electrochemical deposition a conductive layer; and (c) heat treating the workpiece to cause the second conductive layer to flow back to at least partially fill the component. 如請求項1述及之方法，其中該種晶層選自由以下各物組成的群組：種晶、二次種晶、和種晶與襯墊的堆疊膜。 The method of claim 1, wherein the seed layer is selected from the group consisting of seed crystals, secondary seed crystals, and a stacked film of seed crystals and liners. 如請求項1述及之方法，其中通過選自由物理氣相沉積、化學氣相沉積、原子層沉積和無電沉積組成的群組的製程來沉積該第一導電層。 The method of claim 1, wherein the first conductive layer is deposited by a process selected from the group consisting of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and electroless deposition. 如請求項1述及之方法，其中該第二導電層是通過電化學沉積所沉積的覆蓋或填充層。 The method of claim 1, wherein the second conductive layer is a cover or fill layer deposited by electrochemical deposition. 如請求項4述及之方法，其中使用酸性化學品沉積該第二導電層。 The method of claim 4, wherein the second conductive layer is deposited using an acidic chemical. 如請求項1述及之方法，其中使用鹼性化學品沉積該第二導電層。 The method of claim 1, wherein the second conductive layer is deposited using an alkaline chemical. 如請求項1所示的方法，其中該第二導電層具有大於約10歐姆/方的薄層電阻。 The method of claim 1, wherein the second conductive layer has a sheet resistance greater than about 10 ohms/square. 如請求項1述及之方法，該方法還包括以下步驟：將覆蓋、填充層或另一共形導電層沉積在反流的該第二導電層上。 The method of claim 1, the method further comprising the step of depositing a capping, filling layer or another conformal conductive layer on the second conductive layer of the reverse flow. 如請求項1述及之方法，該方法還包括以下步驟：在沉積該第一導電層之前將阻擋層沉積在該部件中。 The method of claim 1, the method further comprising the step of depositing a barrier layer in the component prior to depositing the first conductive layer. 如請求項9述及之方法，其中將該第一導電層直接沉積在該阻擋層上。 The method of claim 9, wherein the first conductive layer is deposited directly on the barrier layer. 如請求項1述及之方法，其中該第一導電層的薄層電阻大於50歐姆/方。 The method of claim 1, wherein the first conductive layer has a sheet resistance greater than 50 ohms/square. 如請求項1述及之方法，其中該部件的臨界尺寸小於30nm。 The method of claim 1 wherein the critical dimension of the component is less than 30 nm. 如請求項1述及之方法，其中將該第二導電層沉積在該第一導電層的整個表面之上。 The method of claim 1, wherein the second conductive layer is deposited over the entire surface of the first conductive layer. 如請求項1述及之方法，其中該電氣接觸件選自由以下各接觸件組成的群組：開路接觸件、非密封接觸件、嵌入式接觸件和遮罩式接觸件。 The method of claim 1, wherein the electrical contact is selected from the group consisting of an open contact, a non-sealed contact, an embedded contact, and a masked contact. 如請求項1述及之方法，其中該種晶層沉積在該部件中。 The method of claim 1, wherein the seed layer is deposited in the component. 一種工件，該工件包括：(a)一部件；(b)位於該部件中的一第一導電層，其中該第一導電層為含有鈷、釕、或其組合之一種晶層，且其中該第一導電層的薄層電阻大於10歐姆/方；以及(c)位於該部件中的一第二導電層，該第二導電層係直接沉積在該第一導電層上，其中該第二導電層為一銅金屬化層，且其中該第二導電層覆蓋該第一導電層的整個表面，其中該第二導電層是通過電化學沉積所沉積的共形導電層；以及該工件是進行熱處理以使該第二導電層反流以至少部分填充該部件。 A workpiece comprising: (a) a component; (b) a first conductive layer in the component, wherein the first conductive layer is a crystalline layer containing cobalt, germanium, or a combination thereof, and wherein the a first conductive layer having a sheet resistance greater than 10 ohms/square; and (c) a second conductive layer in the component, the second conductive layer being deposited directly on the first conductive layer, wherein the second conductive layer The layer is a copper metallization layer, and wherein the second conductive layer covers the entire surface of the first conductive layer, wherein the second conductive layer is a conformal conductive layer deposited by electrochemical deposition; and the workpiece is heat treated The second conductive layer is reversed to at least partially fill the component.