511242 8552twfl.doc/〇〇6 A7511242 8552twfl.doc / 〇〇6 A7
^_I_I_ 經濟部智慧財產局員工消費合作社印製 發明說明（I ) 本發明是有關於一種晶片結構及其製程，且特別是 有關於改善電阻-電容遲緩問題的晶片結構及其製程。 現今積體電路元件發展的趨勢，無不朝向高積集 度、高密度、小體積、多功能等方向發展，因此晶片的體 積、封裝的體積均朝向縮小化設計，就半導體製程而言， 〇·18微米線寬的半導體元件已進入量產，然而對於其內部 極細的金屬連線會對晶片效能產生負面地衝擊，例如會產 生匯流排之壓降，以及關鍵訊號路徑的電阻-電容遲緩(RC delay)與雜訊等問題。 請參照第1圖’其繪示習知半導體具有內連線的晶 片結構剖面示意圖。 如第1圖所示，晶片結構100具有一基底110、一 積層120及一保護層130，基底11〇具有一表面112，在 基底110之表面112的表層具有多個電子元件114，比如 是電晶體等，而基底110比如是矽基底。積層120係形成 在基底U免上，而積層120具有一介電結構-122及一線 路結構體124，線路結構體124係交錯於介電結構體I22 中，而線路結構體124分別與電子元件114電性連接，並 且線路結構體124還包括多個焊墊126，暴露於介電結構 體122外，並且透過焊墊126，可以使線路結構體124與 外界電路電性連接，而介電結構體122的材質係爲氮化矽 或氧化砂。另外’保護層130係沉積在積層上’而保 護層II4會暴露出焊墊126。其中，線路結構體124之金 屬層可以作爲電源匯流排(power bus)或接地匯流排(groimd 3 本纸張尺度適用中國國豕標準（CNS)A4規格（210 X 297公楚) (請先閱讀背面之注意事項再填寫本頁) # -emmmm MmmB mtm t§ n · flu ft— n 言 線_· 511242 85 52twf 1 .doc/006 A7 B7 五、發明說明（Z) bus)之用，而電源匯流排或接地匯流排會連接到至少一焊 墊126，而與外界電路電性連接。 然而，就現今製程而言，由於積層120中線路結構 體124的線寬太細，約爲0.3微米以下，並且線路結構體 121的路徑厚度亦甚薄，而介電結構體122之介電常數甚 高，約爲4左右，故容易產生電阻_電容遲緩的問題，顯 著降低晶片的效能，特別是在電源匯流排、接地匯流排或 其他需共同分享訊號傳輸的金屬連線上，影響更爲嚴重。 並且由於線路結構體124之線寬甚細，需要精度甚高的設 備從事生產，如此成本將大幅地增加。 因此本發明目的之一就是提供一種晶片結構及墓盤 程_，可以改善電阻-電容遲緩的問題及降低晶片之功率消 耗。 本發明的目的之二就是提供一種晶片結構及甚^ 璧，可以使用精度較低的設備從事生產，因而降低製造成 本。 在敘述本發明之前，先對空間介詞的用法做界定， 所謂空間介詞“上”係指兩物之空間關係係爲可接觸或不 可接觸均可。舉例而言，A物在B物上，其所表達的意思 係爲A物可以直接配置在B物上，A物有與B物接觸； 或者A物係配置在B物上的空間中，A物沒有與B物接 觸。 依照本發明之上述及其他之目的，提出一種晶片結 構，包括一基底、一第一積層、一保護層及一第二積層。 (請先閱讀背面之注意事項再填寫本頁) --------訂· — 1 ϋ Β— 1 an n I 線“ 經濟部智慧財產局員工消費合作社印製 1 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 511242 8552twfl .doc/006 A7 ___ B7 五、發明說明（>) 其中基底包括複數個電子元件，配置在基底之表層。第一 積層位在基底上，第一簠^包括一第一介電結構體及一第 一線路結構體，第一線路結構體係交錯於第一介電結構體 中，而第一線路結構體與電子元件電性連接，第一線路結 構體係由多個第一金屬層及多個第一插塞所構成，藉由第 一插塞使相鄰的第一金屬層電性連接。保護層配置在第一 積層上，且保護層暴露出第一線路結構體。第二積層係配 置在保護層上，第二積層包括一第二介電結構體及一第二 線路結構體’第二線路結構體係交錯於第二介電結構體 中’而第一線路結構體與第一線路結構體電性連接，第二 線路結構體係由至少一第二金屬層及至少一第二插塞所構 成’弟一插塞與弟一金屬層電性連接。其中第二金屬層的 路徑厚度、寬度及截面積分別大於該第一金屬層的路徑厚 度、寬度及截面積。而第一介電結構體係由至少一第一介 電層所構成，第二介電結構體係由至少一第二介電層所構 成，其中任一第二介電層之厚度係大於任—第—介電層之 厚度。 依照本發明之較佳實施例，其中第二金屬層之路徑 厚度係界於1微米到50微米之間；路徑寬度係界於1微 米到1公分之間，而路徑截面積係界於1平方微米到〇 5 平方公厘之間。而第一積層之介電結構體的材質係爲無機 化合物，比如是氮矽化合物或氧矽化合物。另外，第二介 電結構體係爲有機化合物’比如是聚醯亞胺、苯基環丁烯、 多孔性介電材質或彈性體。 5 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） <請先閱讀背面之注意事項再填寫本頁) n 1- 1 >1 n n I n n mmmme MmMmw n 1 n I · 經濟部智慧財產局員工消費合作社印製 511242 8552twf 1 .doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（¥) 綜上所述，本發明之晶片結構，由於第二線路結構 體之第二金屬層的線路路徑截面積甚大、寬度甚寬'厚度 夠厚，且第二插塞的截面積亦甚大，同時可以使用低電阻 的材質作爲第二線路結構體的主要導電材質’比如是銅或 金，並且第二介電結構體之材質可以是有機化合物’其厚 度可以比較厚，而其介電常數甚低，約爲1〜3之間’其數 據依採用的材質之不同而不同。因此藉由上述的晶片結構 設計，可以降低電阻電容時間延遲的效應，同時還可以降 低晶片的功率及晶片所產生的溫度。 另外，本發明之晶片結構，可以透過第二線路結構 體，使得晶片結構的接點配置可以重新定位，以配合基板 的設計，並且僅需使用少數用以接地的接點及用以接電源 的接點，如此可以大幅簡化基板的設計。再者，若是將多 種晶片透過第二線路結構體而將其接點重配置，使得不同 的晶片可以具有相同的接點配置，如此可以將基板的接點 配置標準化，而大幅降低基板的成本。 再者，本發明之晶片結構，由於第二線路結構體之 製程的精度要求不高，故可以使用精度等級較低的設備從 事生產，以降低製造成本。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） {請先閱讀背面之注意事項再填寫本頁) i!— 訂·！ 1·線 511242 8552twfl .doc/006 A7 B7 五、發明說明（f) 第1圖繪示爲習知半導體具有內連線的晶片結構剖 面示意圖。 第2圖繪示依照本發明一較佳實施例之晶片結構的 立體剖面示意圖。 第3圖繪示依照本發明另一較佳實施例之晶片結構 的剖面示意圖。 · 第4圖繪示依照本發明再一較佳實施例之晶片結構 的剖面示意圖。 第5圖到第11圖繪示依照本發明一較佳實施例之 晶片結構製程的剖面放大示意圖。 第12圖到第18圖繪示依照本發明另一較佳實施例 之晶片結耩製程的剖面放大示意圖。 圖式之標記說明： 110 :基底 112:表面 114 :電子元件 120:積層 122 :介電結構體 124 :線路結構體 126 :焊墊 200 :晶片結構 210 :基底 212 :表面 7 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公爱） f請先閱讀背面之注意事項再填寫本頁) H ϋ n κ· ϋ n n · n 1 ϋ «I ϋ ϋ I · 經濟部智慧財產局員工消費合作社印製 511242 五、發明說明（‘） (請先閱讀背面之注意事項再填寫本頁) 214 :電子元件 220 ··第一積層 222 :第一線路結構體 224 :第一介電結構體 226 :第一金屬層 227 :焊墊 · 228 :第一插塞 230 :保護層 240 :第二積層 241 :第二介電層 242 :第二線路結構體 244 :第二介電結構體 246 ··第二金屬層 247 :接點 248 :第二插塞 322 :第一線路結構體 327 :焊墊 330 :保護層 經濟部智慧財產局員工消費合作社印製 342 :第二線路結構體 346 :第二金屬層 422 :第一線路結構體 427 :焊墊 430 :保護層 446 :第二金屬層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511242 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 5〇〇 :晶片結構 502 :晶圓 510 :基底 512 :表面 514 :電子元件 520 ··第一積層· 521 :介電層 522 :第一線路結構體 524 :第一介電結構體 526 :第一金屬層 527 :焊墊 528 :第一插塞 530 :保護層 532 :保護層開口 540 :第二積層 541 :第二介電層 542 :第二線路結構體 543 :插塞開口 544 :第二介電結構體 546 ··第二金屬層 547 :接點 548 :第二插塞 550 :光阻 552 :光阻開口 (請先閱讀背面之注意事項再填寫本頁) 丨！！ —訂·1丨— I!·線 Α· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511242 經濟部智慧財產局員工消費合作社印製 五、發明說明（义） 560 :黏著層 570 :第二介電層 572 :接點開口 580 :導電金屬 600 :晶片結構 . 602 :晶圓· 627 :焊墊 630 :保護層 632 :保護層開口 641 :第二介電層 643 :插塞開口 647 :接點 650 :光阻 660 :黏著層 670 :第二介電層 672 :接點開口 680 :導電金屬 A1 :第一金屬層之線路路徑的截面積 A2 :第二金屬層之線路路徑的截面積 a:第二插塞的截面積 dl :第一金屬層之線路路徑的寬度 d2 :第二金屬層之線路路徑的寬度 tl :第一金屬層之線路路徑的厚度 t2 :第二金屬層之線路路徑的厚度 (請先閒讀背面之注意事項再填寫本頁) —---—訂 i -------線·- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511242 經濟部智慧財產局員工消費合作社印製 8552twfJ .doc/006 A7 五、發明說明（l ) LI :第一介電層的厚度 L2 :第二介電層的厚度 實施例 在敘述本發明之較佳實施例之前，先介紹影響電阻 電容時間延遲(RC delay)效應的因子及影響功率消耗的因 子。請參照下列之方程式： = RC = 2 L [ L / (Tu.d.Tm) + L / (WS)] P 〇c 2 fV2k (tan) 其中，：電阻電容時間延遲效應 P:功率消耗 :介電材質的介電常數 :金屬導線的電阻係數 L:金屬導線的長度 W:金屬導線的寬度 S:金屬導線的間距 Tu.d.:介電薄膜厚度 Tm :金屬導線厚度， tan :介電損耗 V :外加電壓 f :頻率 k:電容結構因子 <請先閱讀背面之注意事項再填寫本頁) -1 Ml n n Mil 1 .1^β-馨^^ 一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511242 8552twf 1 .doc/006 A7 B7 五、發明說明（β) 由上述的方程式可知，影響電阻電容時間延遲效應 的因子及影響功率消耗的因子。故藉由增加每一介電層的 厚度、採用低介電常數之介電材質及低電阻係數的金屬導 線，並且同時增加金屬導線的寬度及厚度，如此可以降低 電阻電容時間延遲效應及晶片功率的消耗。 本發明係透過上述之電路設計理念，來針對晶片結 構作改良。請參照第2圖，其繪示依照本發明一較佳實施 例之晶片結構的立體剖面示意圖。晶片結構200具有一基 底210、一第一積層220、一保護層230、一第二積層240。 其中基底210比如是矽基底，而基底210具有多個電子元 件214，比如是電晶體，其配置在基底210的一表面212 上。第一積層220係配置在基底210上，而第一積層220 係由多層第一金屬層226(僅繪示其中的一個）及多層第一 介電層交互疊合而成，並透過多個第一插塞228(vias)使 上、下層之第一金屬層226電性連接，或者使第一金屬層 226與電子元件214電性連接，而第一金屬層226及第一 插塞228構成一第一線路結構體222，多層第一介電層構 成一第一介電結構體224，第一線路結構體222係交錯於 第一介電結構體224中，並且第一線路結構體222與電子 元件214電性連接。而第一線路結構體222包括多個焊墊 227(僅繪示其中的一個），暴露於第一介電結構體224之 外，而透過焊墊227可以使第一線路結構體222與其他電 路電性連接。第一介電結構體224之材質可以是無機化合 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·# • 1 1 n 1 IB MMamm ΛΜ§ 訂---------線 ·- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 511242 85 52twf 1 .doc/006 幻 __ B7 五、發明說明（（I ) 物，比如氧矽化合物或氮矽化合物，而第一線路結構體222 之材質可以包括銅、鋁或鎢，其中若是利用銅製程所製作 的第一線路結構體222,可以利用銅作爲第一線路結構體 222之第一金屬層226及第一插塞228 ;而若是利用一般 製程所製作的第一線路結構體222,可以利用鋁作爲第一 線路結構體222之第一金屬層226，·及利用鎢作爲第一線 路結構體222之第一插塞228。 保護層230係位在第一積層220上，並且保護層230 會暴露出焊墊@2。而保護層230係爲無機化合物，比如 是氧矽化合物、氮矽化合物、磷矽玻璃（PSG)、氧氮矽化 合物、或是上述材質所組成的複合層等。 第二積層240係配置在保護層230上，而第二積層 24〇係由多層第二金屬層246及多層第二介電層241交互 疊合而成，並透過多個第二插塞248使上、下層之第二金 屬層246電性連接，或者使第二金屬層246與焊墊227電 性連接，而第二金屬層246及第二插塞248學成一第二線 路結構體242,多層第二介電層241構成一第二介電結構 體244，第二線路結構體242係交錯於第二介電結構體244 中，並且第二線路結構體242與焊墊· 227電性連接。而第 二線路結構體242包括多個接點247，而第二介電結構體 244具有多個開口 249，以暴露出第二線路結構體242之 接點247，如此透過接點247可以使第二線路結構體242 與外界電路電性連接。第二介電結構體244之材質可以是 有機化合物，比如是聚醯亞胺(polyimide，PI)、苯基環丁 (請先閱讀背面之注意事項再填寫本頁) I-丨！ 訂---------線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511242 8552twf 1 .doc/006 A7 B7 五、發明說明（fz) 烯（benzocyclobutene，BCB)、多孔性介電材質、聚亞芳香 基醚(parylene)或彈性體等之高分子聚合物，而第二線路結 構體242之材質可以包括銅、鋁、金、鎳、鈦鎢合金、鈦 或鉻等。由於第二積層240係形成在保護層230上，因此 第二介電結構體2料中的移動離子(mobile ions)及濕氣並 不會滲入到第一積層2·2〇及電子元件214中，故在保護層 230上形成有機化合物或各種過渡金屬是可行的。其中第 二金屬層246之線路路徑的截面積人2係大於第一金屬層 226之線路路徑的截面積Α1及第一插塞228的截面積， 並且第二插塞248的截面積a亦大於第一金屬層226之線 路路徑的截面積A1及第一插塞228的截面積。第二金屬 層246之線路路徑的寬度d2係大於第一金屬層226之線 路路徑的寬度dl ;第二金屬層246之線路路徑的厚度t2 係大於第一金屬層226之線路路徑的厚度tl。而第二金屬 層246之線路路徑的寬度d2係大於1微米，在較佳的情 況下係介於1微米到1公分之間。第二金屬層246之線路 路徑的厚度t2係大於1微米，在較佳的情況下係介於1 微米到50微米之間。第二金屬層246之線路路徑的截面 積系介於1平方微米到〇·5平方公厘之間。而每一第 二介電層241的厚度L2係相當程度地大於第一積層220 之每一第一介電層的厚度L1。另外，第二插塞248之截 面積a比如係界於1平方微米到1〇,〇〇〇平方微米之間。此 外，每一第二介電層241的厚度L2比如是介於1微米到 1〇〇微米之間。由於第二線路結構體之製程的精度要求不 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先間讀背面之注意事項再填寫本頁) ·# • 1 —Hi 1 KB ϋ Mmmt^-^· Μ·— n mmmmm n 1- Βϋ ·1 I 線· 經濟部智慧財產局員工消費合作社印製 511242 85 52twf 1.doc/006 A7 B7 五、發明說明（$) 高，故可以使用精度等級較低的設備從事生產，以降低製 造成本。而第二插塞248之截面積a係大於焊墊227暴露 於保護層230外的面積。 由於第二線路結構體242之第二金屬層2私的線路 路徑截面積甚大、寬度甚寬、厚度夠厚，且第二插塞248 的截面積亦甚大，同時可以使用低電阻的材質作爲第二線 路結構體242的主要導電材質，比如是銅或金，並且第二 介電結構體244之材質可以是有機化合物，而其介電常數 甚低，約爲1〜3之間，其數據依採用的材質之不同而不同， 而第二介電層241的厚度亦甚厚。因此藉由上述的晶 片結構設計，可以降低電阻電容時間延遲的效應，同時還 可以降低晶片的功率及晶片所產生的溫度。 再者，第二積層240之第二線路結構體242的路徑 寬度甚寬、厚度甚厚，且第二插塞248的截面積亦甚大， 因此就製程上而言，精度並不需太精確，利用電鍍、無電 電鍍或濺鍍的方式便可以製造完成，而利用上述方式所製 造的第二線路結構體242，其成本並不高。並且在製作本 發明之第二積層時，其潔淨室的要求並不需太高，僅需等 級10到等級1〇〇之間（Class 10〜Class 100)即可，大幅降 低潔淨室的建構成本。 本發明可以透過第二線路結構體242,使得晶片結 構的接點247配置可以重新定位，以配合基板的設計，並 且僅需使用少數用以接地的接點及用以接電源的接點，如 此可以大幅簡化基板的設計。再者，若是將多種晶片透過 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閱讀背面之注意事項再填寫本頁) * ϋ 1 a— I ·1 mmMm mma§^"J· n 1 i mmmmm «I .1 · 一 經濟部智慧財產局員工消費合作社印製 511242 經濟部智慧財產局員工消費合作社印製 8552twfl.doc/006 A7 五、發明說明（/屮） 第二線路結構體242而將其接點247重配置，使得不同的 晶片可以具有相同的接點配置(layout)，如此可以將基板的 接點配置(layout)標準化，而大幅降低基板的成本。 請參照第3圖，其繪示依照本發明另一較佳實施例 之晶片結構的剖面示意圖。其中，第二線路結構體342之 第二金屬層346亦可以直接形成在保護層330上，使得第 二線路結構體342之第二金屬層346能夠直接與第一線路 結構體322暴露於保護層330外的焊墊327電性連接。另 外，本發明可以將第二線路結構體342之第二金屬層346 設計成電源匯流排(power bus)或接地匯流排(ground bus)， 其係配置在保護層330上的第二積層340中，並且透過接 點347與外界電路之電源端或接地端電性連接，而電源匯 流排或接地匯流排可以設計成平面的樣式。 在前述的較佳實施例中，第二積層係由第二介電結 構體及第二線路結構體所構成。然而，第二積層亦可以僅 由第二線路結構體所構成，如第4圖所示，其繪示依照本 發明再一較佳實施例之晶片結構的剖面示意圖。其中，第 二線路結構體之第二金屬層446係直接形成在保護層430 上，並且直接與第一線路結構體422的焊墊427電性連接， 而第二線路結構體之第二金屬層446係暴露於外。另外， 就本發明晶片結構的訊號傳輸路徑而言，第二線路結構體 可以作爲電子元件414間的訊號傳輸（interconnection)之 用’亦即其訊號可以從其中之一的電子元件414，透過第 一線路結構體422,再傳到第二線路結構體之第二金屬層 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------• «I I Bn 1 n n mmmmm 訂---------線· (請先閱讀背面之注意事項再填寫本頁) 511242 8552twfl .doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ff) 446，然後再傳到第一線路結構體422，使得其訊號可以傳 達到其他的電子元件414。 本發明之晶片結構可以利用打線的方式，使得第二 線路結構體的接點可以與基板或導線架電性連接；或者亦 可以在接點上形成凸塊，與基板之接點電性連接。 接下來，敘述本發明之第二積層的製作方法。請參 照第5圖到第11圖，其繪示依照本發明一較佳實施例之 晶片結構製程的剖面放大示意圖。 請先參照第5圖，首先提供一晶圓502，其係由一 基底510、一第一積層520及一保護層530所構成。而基 底510具有至少一電子元件514，配置在基底510之一表 面512上。第一積層520係形成在基底510上，第一積層 520包括一第一線路結構體522及一第一介電結構體524， 第一線路結構體522係交錯於第一介電結構體524中。第 一介電結構體524係由多個第一介電層521疊合而成，而 第一線路結構體522包括多個第一金屬層526及多個第一 插塞528，透過第一插塞528可以使第一金屬層526與電 子元件514電性連接，亦可以使相鄰之第—金屬層526電 性連接，而第一線路結構體522還包括有至少一焊墊527， 位在第一積層520之表層。保護層530係形成在第一積層 52〇上，而保護層530具有至少一保護層開口 532，以暴 露出焊墊527，其中保護層開口 532的最大寬度比如是介 於〇·5微米到200微米之間。 接下來，以旋塗的方式形成一第二介電層541到保 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)^ _I_I_ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics. Description of the Invention (I) The present invention relates to a chip structure and a process for the same, and more particularly to a chip structure and a process for improving resistance-capacitance retardation. At present, the trend of the development of integrated circuit components is all in the direction of high accumulation, high density, small volume, multi-function, etc. Therefore, the volume of the chip and the volume of the package are all designed to be reduced. As far as the semiconductor process is concerned, 〇 · 18-micron line-width semiconductor components have entered mass production, but the extremely thin metal wiring inside will have a negative impact on chip performance, such as the voltage drop of busbars and the slow resistance-capacitance of critical signal paths ( RC delay) and noise. Please refer to FIG. 1 ', which illustrates a schematic cross-sectional view of a conventional semiconductor wafer structure having interconnects. As shown in FIG. 1, the wafer structure 100 has a substrate 110, a build-up layer 120, and a protective layer 130. The substrate 110 has a surface 112. The surface layer of the surface 112 of the substrate 110 has a plurality of electronic components 114. Crystal, etc., and the substrate 110 is, for example, a silicon substrate. The laminated layer 120 is formed on the substrate U, and the laminated layer 120 has a dielectric structure -122 and a circuit structure 124. The circuit structure 124 is interlaced in the dielectric structure I22, and the circuit structure 124 and the electronic component are respectively 114 is electrically connected, and the line structure body 124 further includes a plurality of bonding pads 126 exposed to the dielectric structure body 122. Through the bonding pads 126, the line structure body 124 can be electrically connected to an external circuit, and the dielectric structure The material of the body 122 is silicon nitride or sand oxide. In addition, the 'protective layer 130 is deposited on the build-up layer' and the protective layer II4 exposes the pad 126. Among them, the metal layer of the circuit structure 124 can be used as a power bus or a ground bus (groimd 3) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 cm) (Please read first Note on the back, please fill in this page again) # -emmmm MmmB mtm t§ n · flu ft— n speech line · 511242 85 52twf 1 .doc / 006 A7 B7 V. For the purpose of the invention (Z) bus), and the power supply The bus bar or the ground bus bar is connected to at least one solder pad 126 and is electrically connected to an external circuit. However, as far as the current process is concerned, since the line width of the circuit structure 124 in the laminate 120 is too thin, about 0.3 micrometers or less, and the path thickness of the circuit structure 121 is also very thin, and the dielectric constant of the dielectric structure 122 Very high, about 4, so it is easy to cause the problem of slow resistance and capacitance, which significantly reduces the performance of the chip, especially on power buses, ground buses, or other metal connections that need to share signal transmission. serious. In addition, since the line structure 124 has a very thin line width, it requires highly accurate equipment to engage in production, so the cost will increase significantly. Therefore, one of the objectives of the present invention is to provide a chip structure and a tombstone process, which can improve the problem of slow resistance-capacitance and reduce the power consumption of the chip. Another object of the present invention is to provide a wafer structure and, moreover, it is possible to use low-precision equipment for production, thereby reducing the manufacturing cost. Before describing the present invention, the usage of the spatial preposition is defined. The so-called spatial preposition "up" refers to whether the spatial relationship between the two objects is accessible or inaccessible. For example, object A is on object B, which means that object A can be directly disposed on object B, and object A is in contact with object B; or object A is located in the space on object B, and A The object is not in contact with the B object. According to the above and other objects of the present invention, a wafer structure is provided, which includes a substrate, a first laminated layer, a protective layer, and a second laminated layer. (Please read the notes on the back before filling in this page) -------- Order · — 1 ϋ Β— 1 an n I Line “Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economy 1 This paper size is applicable China National Standard (CNS) A4 specification (210 X 297 public love) 511242 8552twfl .doc / 006 A7 ___ B7 V. Description of the invention (>) The substrate includes a plurality of electronic components and is arranged on the surface layer of the substrate. The first layer On the substrate, the first substrate includes a first dielectric structure and a first circuit structure. The first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure and the electronic component are electrically conductive. Connection, the first circuit structure system is composed of a plurality of first metal layers and a plurality of first plugs, and the adjacent first metal layers are electrically connected by the first plugs. The protective layer is arranged on the first build-up layer. And the protective layer exposes the first circuit structure. The second laminate is disposed on the protective layer, and the second laminate includes a second dielectric structure and a second circuit structure. In the dielectric structure, and the first wiring structure and The first circuit structure is electrically connected, and the second circuit structure system is composed of at least one second metal layer and at least one second plug. The first plug is electrically connected to the first metal layer. The path thickness, width, and cross-sectional area are greater than the path thickness, width, and cross-sectional area of the first metal layer, respectively. The first dielectric structure system is composed of at least one first dielectric layer, and the second dielectric structure system is composed of at least one Consisting of a second dielectric layer, the thickness of any second dielectric layer is greater than the thickness of any-first dielectric layer. According to a preferred embodiment of the present invention, the path thickness of the second metal layer is bounded by 1 micrometer to 50 micrometers; the path width is bounded between 1 micrometer and 1 cm, and the path cross-sectional area is bounded between 1 square micrometer and 0.05 square millimeters. The material is an inorganic compound, such as a nitrogen silicon compound or an oxy silicon compound. In addition, the second dielectric structure system is an organic compound, such as polyimide, phenylcyclobutene, a porous dielectric material, or an elastomer. 5 paper sizes Applicable to Chinese National Standards (CNS > A4 specification (210 X 297 mm) < Please read the notes on the back before filling this page) n 1- 1 > 1 nn I nn mmmme MmMmw n 1 n I Printed by the Consumer Cooperative of the Property Bureau 511242 8552twf 1 .doc / 006 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (¥) In summary, the wafer structure of the present invention is due to the second circuit structure The cross-sectional area of the circuit path of the second metal layer is very large and the width is very wide. The thickness is thick enough, and the cross-sectional area of the second plug is also very large. At the same time, a low-resistance material can be used as the main conductive material of the second circuit structure. It is copper or gold, and the material of the second dielectric structure can be an organic compound. Its thickness can be relatively thick, and its dielectric constant is very low, about 1 to 3. The data depends on the material used. different. Therefore, with the above-mentioned chip structure design, the effect of the time delay of the resistor and capacitor can be reduced, and at the same time, the power of the chip and the temperature generated by the chip can be reduced. In addition, the wafer structure of the present invention can pass through the second circuit structure, so that the contact configuration of the wafer structure can be repositioned to match the design of the substrate, and only a few contacts for grounding and power for The contacts can greatly simplify the design of the substrate. Furthermore, if multiple kinds of wafers are re-arranged through the second circuit structure, different wafers can have the same contact arrangement, so that the contact arrangement of the substrate can be standardized, and the cost of the substrate can be greatly reduced. Furthermore, since the wafer structure of the present invention requires low precision in the manufacturing process of the second circuit structure, it can be produced using equipment with a lower precision level to reduce manufacturing costs. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: A brief description of the drawings: 6 paper dimensions Applicable to China National Standard (CNS) A4 (210 X 297 mm) {Please read the notes on the back before filling this page) i! — Order ·! 1 · Line 511242 8552twfl .doc / 006 A7 B7 V. Description of the Invention (f) Figure 1 shows a schematic cross-sectional view of a conventional semiconductor wafer structure with interconnects. FIG. 2 is a schematic three-dimensional cross-sectional view of a wafer structure according to a preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a wafer structure according to another preferred embodiment of the present invention. Figure 4 is a schematic cross-sectional view of a wafer structure according to yet another preferred embodiment of the present invention. 5 to 11 are enlarged schematic cross-sectional views of a wafer structure manufacturing process according to a preferred embodiment of the present invention. FIG. 12 to FIG. 18 are enlarged schematic cross-sectional views of a wafer scribing process according to another preferred embodiment of the present invention. Description of drawing symbols: 110: substrate 112: surface 114: electronic component 120: laminated layer 122: dielectric structure 124: circuit structure 126: pad 200: wafer structure 210: substrate 212: surface 7 This paper size is applicable to China National Standard (CNS) A4 (21〇X 297 public love) f Please read the notes on the back before filling in this page) H ϋ n κ · ϋ nn · n 1 «I ϋ ϋ I · Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative 511242 V. Description of Invention (') (Please read the notes on the back before filling this page) 214: Electronic components 220 ·· First buildup 222: First circuit structure 224: First dielectric Structure 226: First metal layer 227: Solder pads 228: First plug 230: Protective layer 240: Second build-up layer 241: Second dielectric layer 242: Second circuit structure 244: Second dielectric structure 246 ·· Second metal layer 247: Contact 248: Second plug 322: First circuit structure 327: Solder pad 330: Protective layer Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 342: Second circuit structure 346 : Second metal layer 422: First circuit structure 427: Pad 430: Protection 446: The second metal layer is the size of the paper applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 511242 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (q) 500: Wafer structure 502 : Wafer 510: Substrate 512: Surface 514: Electronic component 520 ·· First buildup · 521: Dielectric layer 522: First circuit structure 524: First dielectric structure 526: First metal layer 527: Pad 528: first plug 530: protective layer 532: protective layer opening 540: second buildup 541: second dielectric layer 542: second circuit structure 543: plug opening 544: second dielectric structure 546 ... Second metal layer 547: contact 548: second plug 550: photoresist 552: photoresist opening (please read the precautions on the back before filling this page) 丨! !! —Order · 1 丨 — I! · Line A · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 511242 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (meaning) 560 : Adhesive layer 570: Second dielectric layer 572: Contact opening 580: Conductive metal 600: Wafer structure. 602: Wafer · 627: Pad 630: Protective layer 632: Protective layer opening 641: Second dielectric layer 643 : Plug opening 647: contact 650: photoresist 660: adhesive layer 670: second dielectric layer 672: contact opening 680: conductive metal A1: cross-sectional area of the path of the first metal layer A2: second metal layer The cross-sectional area of the circuit path a: the cross-sectional area of the second plug dl: the width of the circuit path of the first metal layer d2: the width of the circuit path of the second metal layer tl: the thickness of the circuit path of the first metal layer t2: The thickness of the circuit path of the second metal layer (please read the precautions on the reverse side before filling this page) —————— Order i ------- Line ·-This paper size applies to Chinese National Standard (CNS) A4 size (210 X 297 mm) 511242 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8552twf J.doc / 006 A7 V. Description of the invention (l) LI: thickness of the first dielectric layer L2: thickness of the second dielectric layer Before describing the preferred embodiment of the present invention, first introduce the influence of the resistance and capacitance time Factors of RC delay effect and factors that affect power consumption. Please refer to the following equation: = RC = 2 L [L / (Tu.d.Tm) + L / (WS)] P 〇c 2 fV2k (tan) where: the delay time effect of the resistor and capacitor P: power consumption: dielectric Dielectric constant of electrical material: resistivity of metal wire L: length of metal wire W: width of metal wire S: pitch of metal wire Tu.d .: thickness of dielectric film Tm: thickness of metal wire, tan: dielectric loss V: Applied voltage f: Frequency k: Capacitance structure factor < Please read the notes on the back before filling this page) -1 Ml nn Mil 1. .1 ^ β- 馨 ^^ A paper size applies Chinese National Standard (CNS ) A4 specification (210 X 297 mm) 511242 8552twf 1 .doc / 006 A7 B7 V. Description of the invention (β) According to the above equations, we can know the factors that affect the time delay effect of resistors and capacitors and the factors that affect power consumption. Therefore, by increasing the thickness of each dielectric layer, using a low dielectric constant dielectric material and a low resistivity metal wire, and simultaneously increasing the width and thickness of the metal wire, this can reduce the time delay effect of the resistor and capacitor and the chip power. Consumption. The present invention aims at improving the structure of the chip through the above-mentioned circuit design concept. Please refer to FIG. 2, which illustrates a schematic three-dimensional cross-sectional view of a wafer structure according to a preferred embodiment of the present invention. The wafer structure 200 has a substrate 210, a first build-up layer 220, a protective layer 230, and a second build-up layer 240. The substrate 210 is, for example, a silicon substrate, and the substrate 210 has a plurality of electronic components 214, such as transistors, which are disposed on a surface 212 of the substrate 210. The first build-up layer 220 is disposed on the substrate 210, and the first build-up layer 220 is formed by alternately stacking a plurality of first metal layers 226 (only one of which is shown) and a plurality of first dielectric layers, and passing through a plurality of first layers. A plug 228 (vias) electrically connects the upper and lower first metal layers 226, or electrically connects the first metal layer 226 and the electronic component 214, and the first metal layer 226 and the first plug 228 form a The first circuit structure 222, a plurality of first dielectric layers constitute a first dielectric structure 224, the first circuit structure 222 is intersected in the first dielectric structure 224, and the first circuit structure 222 and the electrons The element 214 is electrically connected. The first circuit structure 222 includes a plurality of solder pads 227 (only one of which is shown), and is exposed outside the first dielectric structure 224. The first circuit structure 222 and other circuits can be made through the solder pads 227. Electrical connection. The material of the first dielectric structure 224 may be an inorganic compound. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) · # • 1 1 n 1 IB MMamm ΛΜ§ Order --------- Line ·-Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Ministry of Economic Affairs' Intellectual Property Bureau Printed by 511242 85 52twf 1 .doc / 006 Magic__ B7 V. Invention description ((I), such as oxygen silicon compound or nitrogen silicon compound, and the material of the first circuit structure 222 may include copper, aluminum, or tungsten. Among them, if the first circuit structure is made by copper process, 222, copper can be used as the first metal layer 226 and the first plug 228 of the first circuit structure 222; and if the first circuit structure 222 is produced by a general process, aluminum can be used as the first circuit structure 222 The first metal layer 226, and the first plug 228 using tungsten as the first circuit structure 222. The protective layer 230 is located on the first build-up layer 220, and the protective layer 230 will expose the pad @ 2. The protective layer 230 is an inorganic compound. It is an oxygen silicon compound, a nitrogen silicon compound, a phosphosilicate glass (PSG), an oxygen nitrogen compound, or a composite layer composed of the above materials, etc. The second laminated layer 240 is disposed on the protective layer 230, and the second laminated layer 24. It is formed by overlapping a plurality of second metal layers 246 and a plurality of second dielectric layers 241 alternately, and electrically connecting the upper and lower second metal layers 246 through a plurality of second plugs 248, or making the second metal The layer 246 is electrically connected to the bonding pad 227, and the second metal layer 246 and the second plug 248 learn a second circuit structure 242, and the multilayered second dielectric layer 241 constitutes a second dielectric structure 244. The second circuit structure 242 is intersected in the second dielectric structure 244, and the second circuit structure 242 is electrically connected to the pad 227. The second circuit structure 242 includes a plurality of contacts 247, and the second The dielectric structure 244 has a plurality of openings 249 to expose the contacts 247 of the second circuit structure 242, so that the second circuit structure 242 can be electrically connected to an external circuit through the contacts 247. The second dielectric structure The material of the body 244 may be an organic compound, such as polyimide ( polyimide (PI), phenylcyclobutene (please read the precautions on the back before filling this page) I- 丨! Order --------- line · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 511242 8552twf 1 .doc / 006 A7 B7 V. Description of the invention (fz) benzocyclobutene (BCB), porous dielectric material, polyarylene ether (parylene) or elastomer, etc. Molecular polymer, and the material of the second circuit structure 242 may include copper, aluminum, gold, nickel, titanium tungsten alloy, titanium, or chromium. Since the second laminated layer 240 is formed on the protective layer 230, mobile ions and moisture in the second dielectric structure 2 will not penetrate into the first laminated layer 2 · 20 and the electronic component 214. Therefore, it is feasible to form an organic compound or various transition metals on the protective layer 230. The cross-sectional area of the line path of the second metal layer 246 is larger than the cross-sectional area A1 of the line path of the first metal layer 226 and the cross-sectional area of the first plug 228, and the cross-sectional area a of the second plug 248 is also larger than The cross-sectional area A1 of the circuit path of the first metal layer 226 and the cross-sectional area of the first plug 228. The width d2 of the circuit path of the second metal layer 246 is larger than the width dl of the circuit path of the first metal layer 226; the thickness t2 of the circuit path of the second metal layer 246 is greater than the thickness t1 of the circuit path of the first metal layer 226. The width d2 of the circuit path of the second metal layer 246 is greater than 1 micron, and is preferably between 1 micron and 1 cm. The thickness t2 of the circuit path of the second metal layer 246 is greater than 1 micron, and is preferably between 1 micron and 50 microns. The cross-sectional area of the circuit path of the second metal layer 246 is between 1 square micrometer and 0.5 square millimeter. The thickness L2 of each second dielectric layer 241 is considerably larger than the thickness L1 of each first dielectric layer of the first build-up layer 220. In addition, the cross-sectional area a of the second plug 248 is, for example, bounded between 1 square micrometer and 10,000 square micrometers. In addition, the thickness L2 of each second dielectric layer 241 is, for example, between 1 μm and 100 μm. Due to the accuracy requirements of the manufacturing process of the second circuit structure, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page) · # • 1 —Hi 1 KB ϋ Mmmt ^-^ · Μ · — n mmmmm n 1- Βϋ · 1 I line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511242 85 52twf 1.doc / 006 A7 B7 V. Description of the invention ($ ) High, so you can use lower precision equipment to engage in production to reduce manufacturing costs. The cross-sectional area a of the second plug 248 is larger than the area of the pad 227 exposed outside the protective layer 230. Because the cross-sectional area of the second metal layer 2 of the second circuit structure 242 is very large, the width is wide, and the thickness is thick enough, and the cross-sectional area of the second plug 248 is also very large, and a low-resistance material can be used as the first The main conductive material of the two-line structure 242 is, for example, copper or gold, and the material of the second dielectric structure 244 can be an organic compound, and its dielectric constant is very low, about 1 to 3, and its data depends on The materials used are different, and the thickness of the second dielectric layer 241 is also very thick. Therefore, with the above-mentioned chip structure design, the effect of the time delay of the resistance and capacitance can be reduced, and at the same time, the power of the chip and the temperature generated by the chip can be reduced. Furthermore, the path width of the second circuit structure 242 of the second build-up layer 240 is very wide and the thickness is very thick, and the cross-sectional area of the second plug 248 is also very large. Therefore, in terms of manufacturing process, the accuracy does not need to be too precise. It can be completed by electroplating, electroless plating or sputtering, and the cost of the second circuit structure 242 manufactured by the above method is not high. And when making the second laminate of the present invention, the requirements of the clean room do not need to be too high, it only needs to be between level 10 and level 100 (Class 10 ~ Class 100), which greatly reduces the construction cost of the clean room. . According to the present invention, the configuration of the contacts 247 of the chip structure can be repositioned through the second circuit structure 242 to match the design of the substrate, and only a few contacts for grounding and contacts for power supply are needed. Can greatly simplify the design of the substrate. Furthermore, if a variety of wafers are used through this paper size to comply with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) < please read the precautions on the back before filling this page) * ϋ 1 a— I · 1 mmMm mma§ ^ " J · n 1 i mmmmm «I .1 · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511242 Printed by the Employee Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8552twfl.doc / 006 A7 V. Description of the Invention (/屮) The second circuit structure 242 is reconfigured with its contacts 247, so that different chips can have the same contact layout, so that the contact layout of the substrate can be standardized, and the substrate can be greatly reduced. cost. Please refer to FIG. 3, which is a schematic cross-sectional view of a wafer structure according to another preferred embodiment of the present invention. The second metal layer 346 of the second circuit structure 342 can also be directly formed on the protection layer 330, so that the second metal layer 346 of the second circuit structure 342 can be directly exposed to the protection layer with the first circuit structure 322. The solder pads 327 outside 330 are electrically connected. In addition, in the present invention, the second metal layer 346 of the second circuit structure 342 can be designed as a power bus or a ground bus, which is disposed in the second build-up layer 340 on the protective layer 330. And is electrically connected to the power terminal or the ground terminal of the external circuit through the contact 347, and the power bus or the ground bus can be designed in a flat style. In the foregoing preferred embodiment, the second laminate is composed of a second dielectric structure and a second circuit structure. However, the second build-up layer may be composed of only the second circuit structure, as shown in FIG. 4, which illustrates a schematic cross-sectional view of a wafer structure according to yet another preferred embodiment of the present invention. Wherein, the second metal layer 446 of the second circuit structure is directly formed on the protection layer 430 and is electrically connected directly to the bonding pad 427 of the first circuit structure 422, and the second metal layer of the second circuit structure is 446 was exposed. In addition, in terms of the signal transmission path of the chip structure of the present invention, the second circuit structure can be used as a signal transmission (interconnection) between the electronic components 414, that is, the signal can be transmitted from one of the electronic components 414 through the first A circuit structure 422, and then passed to the second metal layer of the second circuit structure. 16 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----------- -• «II Bn 1 nn mmmmm Order --------- Line · (Please read the precautions on the back before filling out this page) 511242 8552twfl .doc / 006 A7 B7 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 5. The invention description (ff) 446 is printed, and then transmitted to the first circuit structure 422, so that its signal can be transmitted to other electronic components 414. The wafer structure of the present invention can be wired so that the contacts of the second circuit structure can be electrically connected to the substrate or the lead frame; or bumps can be formed on the contacts to be electrically connected to the contacts of the substrate. Next, a method for manufacturing the second laminate of the present invention will be described. Please refer to FIG. 5 to FIG. 11, which are enlarged schematic cross-sectional views illustrating a wafer structure manufacturing process according to a preferred embodiment of the present invention. Please refer to FIG. 5 first, a wafer 502 is first provided, which is composed of a substrate 510, a first build-up layer 520, and a protective layer 530. The substrate 510 has at least one electronic component 514 disposed on a surface 512 of the substrate 510. The first build-up layer 520 is formed on the substrate 510. The first build-up layer 520 includes a first circuit structure 522 and a first dielectric structure 524. The first circuit structure 522 is interlaced in the first dielectric structure 524. . The first dielectric structure 524 is formed by stacking a plurality of first dielectric layers 521, and the first circuit structure 522 includes a plurality of first metal layers 526 and a plurality of first plugs 528. The plug 528 can electrically connect the first metal layer 526 and the electronic component 514, and can also electrically connect the adjacent first metal layer 526, and the first circuit structure 522 further includes at least one solder pad 527, which is located at The surface layer of the first build-up layer 520. The protective layer 530 is formed on the first build-up layer 52. The protective layer 530 has at least one protective layer opening 532 to expose the bonding pad 527. The maximum width of the protective layer opening 532 is, for example, 0.5 μm to 200 μm. Between micrometers. Next, a second dielectric layer 541 is formed by spin-coating. The paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
-n n 1 ·1 n n^-eJ· ·1 I ϋ 1« n i IB I 0 511242 8552twf 1 .doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（%) 護層530上，而第二介電層541比如是感光性的有機材質， 然後透過微影製程，而形成至少一插塞開口 543，以暴露 出焊墊527，其中若是保護層開口 S32的寬度甚小時，比 如是1微米，其插塞開口 543的寬度可以設計成比保護層 開口 532的寬度大，如此在接下來的塡入金屬製程時，導 電金屬較容易塡入到插塞開口 543及保護層開口 532中， 而插塞開口 543的寬度比如是3微米或更大的尺寸。 請參照第6圖，接下來以濺鍍的方式，形成一黏著 層560到第二介電層541上、插塞開口 543的側壁上、插 塞開口 543中的保護層530及焊墊527上。其黏著層560 的材質比如是鈦鎢合金、鈦或鉻等。接著形成一光阻550 到黏著層560上，然後透過曝光、顯影等步驟，使得在欲 製作第二金屬層之處，形成光阻開口 552，其中光阻開口 552貫通光阻550，以暴露出黏著層560，而形成如第7圖 所示的結構。請參照第8圖，然後以電鍍的方式，塡入至 少一導電金屬580到插塞開口 543及光阻開口 552中，而 導電金屬580係位在黏著層560上，其中導電金屬580比 如包括銅、鎳、金或鋁等。接著便將光阻550去除，而形 成如第9圖所示的結構。 接下來，便將暴露於外的黏著層560去除，而僅殘 留位在導電金屬580下的黏著層560，形成如第10圖所示 的結構。請參照第11圖，接著再以旋塗的方式，形成另 一第二介電層570到導電金屬580上及位在底部的第二介 電層541上，而此新形成位在頂部的第二介電層570亦可 (請先閲讀背面之注意事項再填寫本頁) ^^ ··丨丨丨丨丨丨訂丨丨丨丨丨丨丨-線_· 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 511242 85 52twf 1 .doc/006 A7 B7 五、發明說明（/q) 以是感光材質，接著再透過微影的製程，而使位在頂部的 第二介電層570形成一接點開口 572，以暴露出導電金屬 580，暴露出的導電金屬580係定義成接點547，透過接點 547，晶片結構500可以與外界電路電性連接。如此第二 積層540便製作完成，第二積層540包括一第二線路結構 體542及一第二介電結構體544，第二線路結構體542係 交錯於第二介電結構體544中，第二線路結構體542包括 至少一第二金屬層546及至少一第二插塞548，而第二插 塞548係由位在插塞開口 543中的導電金屬580及黏著層 560所構成，第二金屬層546係由位在插塞開口 543外及 位在第二介電層541上的導電金屬580及黏著層560所構 成，並且透過第二插塞548可以使第二金屬層546與焊墊 527電性連接。並且，當保護層開口 532的截面積過小時， 可以將第二插塞548的截面積設計成大於保護層開口 532 的截面積。而第二介電結構體544係由多層第二介電層 541、570疊合而成，其中任一第二介電層541、570的厚 度L2係相當程度地大於任一第一介電層521的厚度L1， 而第二介電層541、570的厚度係介於1微米到100微米 之間。其詳細的第二積層內部結構、材質及尺寸，在前述 之較佳實施例中亦有詳盡的描述，在此便不再贅述。 此外，本發明之晶片結構亦可以是透過其他的製程 所形成，如下所述。請參照第12圖到第18圖，其繪示依 照本發明另一較佳實施例之晶片結構製程的剖面放大示意 圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -·1111111 «ΙΙΙΙΙΙ1 . 經濟部智慧財產局員工消費合作社印製 511242 A7 B7 85 52twf 1.doc/006 五、發明說明（β) 請先參照第12圖，首先提供一晶圓602，其晶圓602 的內部結構如前所述’在此便不再贅述。接下來’以旋塗 的方式形成一第二介電層641到晶圓602之保護層630上’ 而第二介電層641比如是感光性的有機材質，然後透過微 影製程，而形成至少一插塞開口 643，以暴露出焊墊627 ’ 其中若是保護層開口 632的最大寬度甚小時，其插塞開口 643的最大寬度可以設計成比保護層開口 632的最大寬度 大，如此在接下來的塡入金屬製程時’導電金屬才較容易 塡入到插塞開口 643中。 請參照第13圖’接下來以濺鍍的方式’形成一黏 著層660到第二介電層641上、插塞開口 643的側壁上、 插塞開口 643中的保護層630及焊墊627上。其黏著層660 的材質比如是鈦鎢合金、鈦或鉻等。 請參照第14圖，接著以電銨或濺鍍的方式’形成 至少一導電金屬680到插塞開口 643中及黏著層660上， 其中導電金屬680比如包括銅、鎳、金或鋁等。接著形成 一光阻650到導電金屬680上，然後透過曝光、顯影等步 驟，使得光阻650定義出一線路圖案，而光阻650僅殘留 在欲製作第二金屬層之處，而不欲製作成第二金屬層之導 電金屬680會暴露於外，形成如第15圖所示的結構。接 著，透過蝕刻的方式，將暴露於光阻650外的導電金屬680 去除，然後再透過蝕刻的方式，將暴露於導電金屬680外 的黏著層660去除，而形成如第16圖所示的結構。接下 來，將光阻650去除，而形成如第17圖所示的結構。 20 本紙張尺度適用中關家標準（CNS)A4規格（21G X 297公爱） ^ (請先閱讀背面之注意事項再填寫本頁) 丨訂·-丨__丨丨—線一 經濟部智慧財產局員工消費合作社印製 511242 8552twfl .doc/006 A7 B7 &、發明說明（ή) 請參照第18圖，接著再以旋塗的方式，形成另一 第二介電層670到導電金屬680上及位在底部的第二介電 層641上，而此新形成位在頂部的第二介電層670亦可以 是感光材質，接著再透過微影的製程，而使位在頂部的第 二介電層670形成一接點開口 672，以暴露出導電金屬 680，暴露出的導電金屬680係定義成接點647，透過接點 647，晶片結構600可以與外界電路電性連接。其詳細的 第二積層640內部結構、材質及尺寸，在前述之較佳實施 例中亦有詳盡的描述，在此便不再贅述。 而上述之製程，亦可以應用在多層的導電金屬中， 在此便不再贅述。 綜上所述，本發明至少具有下列優點： 1.本發明之晶片結構及其製程，由於第二線路結構 體之第二金屬層的線路路徑截面積甚大、寬度甚寬、厚度 夠厚，且第二插塞的截面積亦甚大，同時可以使用低電阻 的材質作爲第二線路結構體的主要導電材質，比如是銅或 金，並且第二介電結構體之材質可以是有機化合物，厚度 比較厚，而其介電常數甚低，約爲1〜3之間，其數據依採 用的材質之不同而不同。因此藉由上述的晶片結構設計， 可以降低電阻電容時間延遲的效應，同時還可以降低晶片 的功率及晶片所產生的溫度。 2·本發明之晶片結構及其製程，可以透過第二線路 結構體，使得晶片結構的接點配置可以重新定位，以配合 基板的設計，並且透過整合接地點或接電源點，使與基板 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)-nn 1 · 1 nn ^ -eJ · · 1 I ϋ 1 «ni IB I 0 511242 8552twf 1 .doc / 006 A7 B7 Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Cooperatives V. Description of the invention (%) on the protective layer 530 The second dielectric layer 541 is, for example, a photosensitive organic material, and then through the lithography process, at least one plug opening 543 is formed to expose the bonding pad 527. If the width of the protective layer opening S32 is very small, for example, It is 1 micron, and the width of the plug opening 543 can be designed to be larger than the width of the protective layer opening 532. Therefore, in the subsequent metal intrusion process, conductive metal is more likely to penetrate into the plug opening 543 and the protective layer opening 532. The width of the plug opening 543 is, for example, 3 micrometers or more. Please refer to FIG. 6. Next, an adhesive layer 560 is formed on the second dielectric layer 541, the sidewall of the plug opening 543, the protective layer 530 and the pad 527 in the plug opening 543 by sputtering. . The material of the adhesive layer 560 is, for example, titanium tungsten alloy, titanium or chromium. Next, a photoresist 550 is formed on the adhesive layer 560, and then through the steps of exposure and development, a photoresist opening 552 is formed at the place where the second metal layer is to be formed, and the photoresist opening 552 penetrates the photoresist 550 to expose the photoresist. The adhesive layer 560 forms a structure as shown in FIG. 7. Please refer to FIG. 8, and then insert at least one conductive metal 580 into the plug opening 543 and the photoresist opening 552 by electroplating. The conductive metal 580 is located on the adhesive layer 560. The conductive metal 580 includes copper, for example. , Nickel, gold, or aluminum. Then, the photoresist 550 is removed to form a structure as shown in FIG. Next, the adhesive layer 560 exposed to the outside is removed, and only the adhesive layer 560 located under the conductive metal 580 remains, forming a structure as shown in FIG. 10. Please refer to FIG. 11, and then spin-coating to form another second dielectric layer 570 on the conductive metal 580 and the second dielectric layer 541 at the bottom, and this newly formed first The second dielectric layer 570 is also available (please read the precautions on the back before filling this page) ^^ ·· 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 -line_ · This paper size applies to Chinese national standards ( CNS > A4 specification (210 X 297 mm) 511242 85 52twf 1 .doc / 006 A7 B7 V. Description of the invention (/ q) It is a photosensitive material, and then passes through the lithography process to make it the second on the top The dielectric layer 570 forms a contact opening 572 to expose the conductive metal 580. The exposed conductive metal 580 is defined as the contact 547. Through the contact 547, the chip structure 500 can be electrically connected to an external circuit. The laminated layer 540 is completed. The second laminated layer 540 includes a second circuit structure 542 and a second dielectric structure 544. The second circuit structure 542 is interlaced in the second dielectric structure 544. The second circuit structure The body 542 includes at least one second metal layer 546 and at least one second plug 548, and The two plugs 548 are composed of a conductive metal 580 and an adhesive layer 560 located in the plug opening 543, and the second metal layer 546 is formed of conductive materials located outside the plug opening 543 and on the second dielectric layer 541. The second metal layer 546 and the bonding pad 527 can be electrically connected through the second plug 548. When the cross-sectional area of the protective layer opening 532 is too small, the second plug can be connected. The cross-sectional area of 548 is designed to be larger than the cross-sectional area of the protective layer opening 532. The second dielectric structure 544 is formed by stacking a plurality of second dielectric layers 541 and 570, and any of the second dielectric layers 541 and 570 The thickness L2 is substantially larger than the thickness L1 of any of the first dielectric layers 521, and the thickness of the second dielectric layers 541, 570 is between 1 micrometer and 100 micrometers. Its detailed internal structure of the second laminate , Material, and size are also described in detail in the foregoing preferred embodiments, and will not be repeated here. In addition, the wafer structure of the present invention may also be formed through other processes, as described below. FIG. 12 to FIG. 18 show another embodiment according to the present invention. The enlarged schematic diagram of the cross section of the wafer structure manufacturing process of the preferred embodiment. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page)-· 1111111 «ΙΙΙΙΙΙΙ1. Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511242 A7 B7 85 52twf 1.doc / 006 V. Description of the Invention (β) Please refer to Figure 12 first, and first provide a wafer 602 whose internal structure is the same as before The 'will not be repeated here. Next, a second dielectric layer 641 is formed on the protective layer 630 of the wafer 602 by spin coating. The second dielectric layer 641 is, for example, a photosensitive organic material, and is then formed through a lithography process to form at least A plug opening 643 is exposed to expose the solder pad 627 ′. If the maximum width of the protective layer opening 632 is very small, the maximum width of the plug opening 643 can be designed to be larger than the maximum width of the protective layer opening 632. In the process of metal insertion, it is easier for the conductive metal to be inserted into the plug opening 643. Please refer to FIG. 13 'Next, by sputtering', an adhesive layer 660 is formed on the second dielectric layer 641, on the sidewall of the plug opening 643, on the protective layer 630 and the pad 627 in the plug opening 643. . The material of the adhesive layer 660 is, for example, titanium tungsten alloy, titanium or chromium. Please refer to FIG. 14, and then form at least one conductive metal 680 into the plug opening 643 and the adhesive layer 660 by electro-ammonium or sputtering. The conductive metal 680 includes copper, nickel, gold, or aluminum, for example. Next, a photoresist 650 is formed on the conductive metal 680, and then through the steps of exposure and development, the photoresist 650 defines a circuit pattern, and the photoresist 650 only remains at the place where the second metal layer is to be formed, but not to be made The conductive metal 680 forming the second metal layer is exposed to the outside, forming a structure as shown in FIG. 15. Next, the conductive metal 680 exposed to the photoresist 650 is removed by etching, and then the adhesive layer 660 exposed to the conductive metal 680 is removed by etching to form a structure as shown in FIG. 16 . Next, the photoresist 650 is removed to form a structure as shown in FIG. 20 This paper size applies the Zhongguanjia Standard (CNS) A4 specification (21G X 297 public love) ^ (Please read the precautions on the back before filling this page) 丨 Order ·-丨 __ 丨 丨 —Wisdom Ministry of Economy Printed by the Consumer Affairs Cooperative of the Property Bureau 511242 8552twfl.doc / 006 A7 B7 & Description of the invention Please refer to Figure 18, and then spin-coat to form another second dielectric layer 670 to conductive metal 680 Above and on the second dielectric layer 641 on the bottom, the newly formed second dielectric layer 670 on the top can also be a photosensitive material, and then through the lithography process, the second The dielectric layer 670 forms a contact opening 672 to expose the conductive metal 680. The exposed conductive metal 680 is defined as a contact 647. Through the contact 647, the chip structure 600 can be electrically connected to an external circuit. The detailed internal structure, material, and dimensions of the second build-up layer 640 are also described in detail in the foregoing preferred embodiment, and will not be repeated here. The above process can also be applied to multi-layer conductive metals, which will not be repeated here. In summary, the present invention has at least the following advantages: 1. The wafer structure of the present invention and its manufacturing process, because the cross-sectional area of the circuit path of the second metal layer of the second circuit structure is very large, the width is wide, and the thickness is thick enough; and The cross-sectional area of the second plug is also very large. At the same time, a low-resistance material can be used as the main conductive material of the second circuit structure, such as copper or gold, and the material of the second dielectric structure can be an organic compound. Thick, and its dielectric constant is very low, about 1 to 3, and its data varies depending on the material used. Therefore, with the above-mentioned chip structure design, the effect of the time delay of the resistance and capacitance can be reduced, and at the same time, the power of the chip and the temperature generated by the chip can be reduced. 2. The wafer structure and its manufacturing process of the present invention can pass through the second circuit structure, so that the contact configuration of the wafer structure can be repositioned to match the design of the substrate, and by integrating the ground point or the power point, Paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
n mmmmm n i n n n ·.- n n n SI ·1 n I I »· 經濟部智慧財產局員工消費合作社印製 511242 A7 8552twfl .doc/006 五、發明說明（¾ ) 間僅需使用少數用以接地的接點及用以接電源的接點，如 此可以大幅簡化基板的設計。再者，若是將多種晶片透過 第二線路結構體而將其接點重配置，使得不同的晶片可以 具有相同的接點配置，如此可以將基板的接點配置標準 化，而大幅降低基板的成本。 3·本發明之晶片結構及其製程，由於第二線路結構 體之製程的精度要求不高，故可以使用精度等級較低的設 備從事生產，以降低製造成本。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍內’當可作各種之更動與潤飾，因此本發明之隔 離範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 2 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）n mmmmm ninnn · .- nnn SI · 1 n II »· Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511242 A7 8552twfl .doc / 006 V. The invention description (¾) only requires a few contacts for grounding and The contacts used to connect the power supply can greatly simplify the design of the substrate. Furthermore, if multiple contacts are re-arranged through the second circuit structure, different wafers can have the same contact arrangement, which can standardize the contact arrangement of the substrate and greatly reduce the cost of the substrate. 3. The wafer structure of the present invention and its manufacturing process, because the precision of the manufacturing process of the second circuit structure is not high, can use equipment with a lower precision level to engage in production to reduce manufacturing costs. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The isolation scope shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 2 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)