JP4759981B2 - Manufacturing method of electronic component built-in module - Google Patents

Manufacturing method of electronic component built-in module Download PDF

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JP4759981B2
JP4759981B2 JP2004318919A JP2004318919A JP4759981B2 JP 4759981 B2 JP4759981 B2 JP 4759981B2 JP 2004318919 A JP2004318919 A JP 2004318919A JP 2004318919 A JP2004318919 A JP 2004318919A JP 4759981 B2 JP4759981 B2 JP 4759981B2
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electronic component
forming
insulating resin
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JP2006134914A (en
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悟 倉持
義孝 福岡
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Dai Nippon Printing Co Ltd
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Description

本発明は、キャパシタ、レジスタ（抵抗）、インダクタ等の受動部品、もしくは能動部品のような電子部品を内蔵した電子部品内蔵モジュールと、このような電子部品内蔵モジュールを製造するための製造方法に関する。   The present invention relates to an electronic component built-in module including an electronic component such as a passive component such as a capacitor, a resistor (resistor), an inductor, or an active component, and a manufacturing method for manufacturing such an electronic component built-in module.

近年、ＬＳＩチップ等を多層配線基板上に直接実装するベアチップ実装法が提案されている。ベアチップ実装法では、予め多層配線基板上に形成された配線の接続パッド部に、ボンディング・ワイヤ、ハンダや金属球等からなるバンプ、異方性導電膜、導電性接着剤、光収縮性樹脂等の接続手段を用いて半導体チップが実装される。
また、半導体チップ等では、ＩＣ、ＬＳＩ等の集積回路素子の高密度化が進むとともに、動作速度が年々上昇し、半導体チップ内部で発生するスイッチングノイズが集積回路素子を誤動作させる要因になるという問題があった。スイッチングノイズを低減させるためには、電源バスラインと接地バスラインとの間にキャパシタを配置することが有効である。 In recent years, a bare chip mounting method in which an LSI chip or the like is directly mounted on a multilayer wiring board has been proposed. In the bare chip mounting method, bonding wires, bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc., are formed on wiring connection pads formed on a multilayer wiring board in advance. A semiconductor chip is mounted using the connecting means.
In addition, in semiconductor chips and the like, integrated circuit elements such as ICs and LSIs are becoming higher in density, and the operating speed is increasing year by year, and switching noise generated inside the semiconductor chip becomes a factor that causes the integrated circuit elements to malfunction. was there. In order to reduce switching noise, it is effective to arrange a capacitor between the power supply bus line and the ground bus line.

このようなキャパシタやインダクター、レジスタ（抵抗）等の受動部品や能動部品のような電子部品が必要な場合、半導体チップと同様に、多層配線基板に外付けで実装することが行なわれている。しかし、キャパシタを外付け部品として配線基板上に配置すると、キャパシタと半導体チップの間の接続距離が長くなって配線インダクタンスが大きくなるため、キャパシタの効果が不充分となってしまう。また、多層配線基板上に形成された配線の接続パッド部は、半導体チップ等の実装部位とは別の部位に設けられるため、受動部品や能動部品のような電子部品を実装するためには多層配線基板の面方向の広がりが必要であった。このため、多層配線基板の小型化には限界があり、実装される電子部品の数が増えるにしたがって、小型化は更に困難となる傾向にあった。   When electronic components such as passive components and active components such as capacitors, inductors and resistors (resistors) are required, they are externally mounted on a multilayer wiring board as in the case of semiconductor chips. However, if the capacitor is arranged as an external component on the wiring board, the connection distance between the capacitor and the semiconductor chip becomes long and the wiring inductance becomes large, so that the effect of the capacitor becomes insufficient. In addition, since the connection pad portion of the wiring formed on the multilayer wiring board is provided in a part different from the mounting part such as a semiconductor chip, a multilayer part is required for mounting electronic parts such as passive parts and active parts. The expansion of the surface direction of the wiring board was necessary. For this reason, there is a limit to the miniaturization of the multilayer wiring board, and the miniaturization tends to become more difficult as the number of electronic components to be mounted increases.

これらの問題に対応するために、半導体チップを配線基板に実装する場合に用いられる中間基板（インターポーザ、あるいは半導体チップキャリア）に、キャパシタを内蔵させることが提案されている（特許文献１、２）。
特開平８−１４８５９５号公報 特開２００１−３２６２９８号公報 In order to cope with these problems, it has been proposed to incorporate a capacitor in an intermediate substrate (interposer or semiconductor chip carrier) used when a semiconductor chip is mounted on a wiring board (Patent Documents 1 and 2). .
JP-A-8-148595 JP 2001-326298 A

しかしながら、特許文献１に示される半導体装置は、ベース基板上に厚膜キャパシタを有するガラスセラミックスからなるチップキャリアが接続される構造を有し、誘電体層を薄くすることが困難であるため、キャパシタの特性に限界があった。また、特許文献２には、キャパシタをもつセラミックスからなるインターポーザを備えた構成が開示されているが、インターポーザを用いる方法では、キャパシタの誘電体層の材料、厚さ、キャパシタの位置、大きさ等を予め決めておかなければならないという問題があった。   However, the semiconductor device disclosed in Patent Document 1 has a structure in which a chip carrier made of glass ceramics having a thick film capacitor is connected to a base substrate, and it is difficult to make the dielectric layer thin. There was a limit to the characteristics. Patent Document 2 discloses a configuration including an interposer made of ceramics having a capacitor. However, in the method using the interposer, the material, thickness, capacitor position, size, etc. of the capacitor dielectric layer are disclosed. There was a problem that had to be determined in advance.

また、多面付けのウエハ基板に受動部品や能動部品を載置するための凹部を形成し、この凹部に電子部品を内蔵させ、その後、所望の多層配線をウエハ基板上に形成した後、ダイシングすることにより電子部品内蔵モジュールを製造することが考えられる。しかし、電子部品上に多層配線を形成する工程では、電気絶縁層、導通ビア、配線層等を形成する工程が繰り返され、このため工程が複雑で長いものとなり、製造歩留まりの低下を来たすという問題があった。また、このような電子部品内蔵モジュールを複数重ねて使用する場合、重ねられた各電子部品内蔵モジュール間の接続、すなわち、電子部品内蔵モジュールにおける表裏導通が困難であった。   Further, a recess for mounting passive components and active components is formed on a multi-sided wafer substrate, and an electronic component is built in the recess, and then a desired multilayer wiring is formed on the wafer substrate and then diced. It is conceivable to manufacture an electronic component built-in module. However, in the process of forming a multilayer wiring on an electronic component, the process of forming an electrical insulating layer, a conductive via, a wiring layer, etc. is repeated, which makes the process complicated and long, resulting in a decrease in manufacturing yield. was there. Further, when a plurality of such electronic component built-in modules are used in a stacked manner, it is difficult to connect the stacked electronic component built-in modules, that is, to connect the front and back of the electronic component built-in modules.

本発明は、上記のような実情に鑑みてなされたものであり、単体での使用、あるいは複数積み重ねての使用が可能な小型で信頼性が高い電子部品内蔵モジュールを簡便に製造するための製造方法を提供することを目的とする。 The present invention has been made in view of the circumstances as described above, use of a single unit, or multiple stacked easily for the production of small and reliable electronic component built modules that can be used for An object is to provide a manufacturing method.

このような目的を達成するために、本発明の電子部品内蔵モジュールの製造方法は、基材の一方の面に絶縁層を形成し、次いで、該絶縁層を貫通する複数の外部端子を形成する工程と、シリコン基板の一方の面に薄膜素子形成層を有する電子部品チップを、前記シリコン基板が当接するように前記絶縁層上に固着する工程と、前記電子部品チップを被覆するように前記絶縁層上に絶縁樹脂層を形成し、電子部品チップの非配設部位において前記絶縁樹脂層を貫通し所望の前記外部端子が露出するように複数の微細孔を形成するとともに、前記薄膜素子形成層の端子が露出する端子ビア用孔部を前記絶縁樹脂層に形成する工程と、前記微細孔と前記端子ビア用孔部に導電材料を充填して上下導通ビアと端子ビアを形成するとともに、該端子ビアと所望の前記上下導通ビアとを接続するための配線を形成する工程と、前記端子ビアと配線を被覆し、前記上下導通ビアを露出するように被覆層としての絶縁樹脂層を形成する工程と、前記基材を除去する工程と、を有するような構成とした。 In order to achieve such an object, the method for manufacturing an electronic component built-in module according to the present invention forms an insulating layer on one surface of a substrate, and then forms a plurality of external terminals penetrating the insulating layer. A step of fixing an electronic component chip having a thin film element forming layer on one surface of a silicon substrate on the insulating layer so that the silicon substrate is in contact; and the insulation so as to cover the electronic component chip Forming an insulating resin layer on the layer, forming a plurality of fine holes so as to penetrate the insulating resin layer and expose the desired external terminals at the non-arranged portion of the electronic component chip, and the thin film element forming layer Forming a terminal via hole in which the terminal is exposed in the insulating resin layer, filling the fine hole and the terminal via hole with a conductive material to form a vertical conductive via and a terminal via, Terminal via Forming a wiring for connecting the desired vertical conduction via, covering the terminal via and wiring, and forming an insulating resin layer as a coating layer so as to expose the vertical conduction via; And a step of removing the substrate.

本発明の他の態様として、前記外部端子を形成する工程にて、所望の前記外部端子を接続するための配線層を前記絶縁層に形成し、前記微細孔を形成する工程では、所望の外部端子または配線層が露出するように前記微細孔を形成するような構成とした。
本発明の他の態様として、被覆層としての絶縁樹脂層に露出している上下導通ビアに、絶縁樹脂層と同一面をなすように導電材料を充填する工程、あるいは、はんだボール、金めっきバンプ、金スタッドバンプのいずれかを形成する工程を有するような構成とした。
本発明の他の態様として、前記基材が金属またはシリコンであるような構成とした。 As another aspect of the present invention, in the step of forming the external terminal, a wiring layer for connecting the desired external terminal is formed on the insulating layer, and in the step of forming the microhole, a desired external The fine hole is formed so that the terminal or the wiring layer is exposed.
As another aspect of the present invention, a step of filling a conductive material so that a vertical conductive via exposed in an insulating resin layer as a coating layer is flush with the insulating resin layer, or a solder ball, a gold plating bump The structure is such that it has a step of forming any one of the gold stud bumps.
As another aspect of the present invention, the base material is a metal or silicon.

このような本発明の電子部品内蔵モジュールは、基板を備えておらず、絶縁樹脂層内に電子部品チップが内蔵されているので小型、薄型化が可能であり、また、上下導通ビアを絶縁樹脂層中に備えているので、本発明の電子部品内蔵モジュールどうしの積層、あるいは、他の電子部品内蔵モジュール等との積層時に容易に各モジュール間の導通をとることができる。
また、本発明の電子部品内蔵モジュールの製造方法は、電子部品上に多層配線を形成する煩雑な工程が不要であるため、製造歩留まりが向上し、信頼性の高い電子部品内蔵モジュールを製造することができる。 Such an electronic component built-in module of the present invention does not include a substrate, and an electronic component chip is built in an insulating resin layer, so that it can be reduced in size and thickness. Since it is provided in the layer, it is possible to easily establish conduction between the modules when the electronic component built-in modules of the present invention are stacked or stacked with other electronic component built-in modules.
In addition, since the method for manufacturing an electronic component built-in module according to the present invention does not require a complicated process of forming multilayer wiring on the electronic component, the manufacturing yield is improved and a highly reliable electronic component built-in module is manufactured. Can do.

以下、本発明の実施の形態について図面を参照して説明する。
［電子部品内蔵モジュール］
図１は、本発明の電子部品内蔵モジュールの一実施形態を示す平面図であり、図２は図１に示される電子部品内蔵モジュールのＡ−Ａ線矢視縦断面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Electronic component built-in module]
FIG. 1 is a plan view showing an embodiment of the electronic component built-in module of the present invention, and FIG. 2 is a vertical cross-sectional view of the electronic component built-in module shown in FIG.

図１及び図２において、本発明の電子部品内蔵モジュール１１は、所望の部位に複数の外部端子１３、配線層１４を有する絶縁層１２と、この絶縁層１２の一方の面に配設された電子部品チップ２１と、この電子部品チップ２１を被覆するように絶縁層１２上に配設された絶縁樹脂層１６と、備えている。尚、図１は、電子部品内蔵モジュール１１を絶縁層１２側から見た平面図である。
外部端子１３は、絶縁層１２を貫通するように配設されており、所望の外部端子１３間を接続するように配線層１４が絶縁層１２に配設されている。
また、絶縁樹脂層１６には、この絶縁樹脂層１６を貫通し所望の外部端子１３または配線層１４と接続（図示例では外部端子１３と接続）する上下導通ビア１８が配設されている。 1 and 2, an electronic component built-in module 11 according to the present invention is disposed on an insulating layer 12 having a plurality of external terminals 13 and a wiring layer 14 at a desired site, and on one surface of the insulating layer 12. An electronic component chip 21 and an insulating resin layer 16 disposed on the insulating layer 12 so as to cover the electronic component chip 21 are provided. FIG. 1 is a plan view of the electronic component built-in module 11 as viewed from the insulating layer 12 side.
The external terminal 13 is disposed so as to penetrate the insulating layer 12, and the wiring layer 14 is disposed on the insulating layer 12 so as to connect the desired external terminals 13.
The insulating resin layer 16 is provided with vertical conductive vias 18 that penetrate the insulating resin layer 16 and are connected to a desired external terminal 13 or wiring layer 14 (connected to the external terminal 13 in the illustrated example).

上記の電子部品チップ２１は、シリコン基板２２と、このシリコン基板２２の一方の面に形成された薄膜素子形成層２３を有し、薄膜素子形成層２３の端子２４が外部端子１３または配線層１４に接続（図示例では外部端子１３と接続）している。このような電子部品チップ２１は、シリコン基板２２の厚みが２０〜５００μｍ、薄膜素子形成層２３の厚みが５〜５０μｍ、全体の厚みが２５〜５５０μｍの範囲となるように設定することが好ましい。また、１個の電子部品チップ２１の外形寸法は、一辺の長さが０．５〜２０ｍｍの範囲となるように設定することが好ましい。
尚、薄膜素子形成層２３が備える電子部品としては、キャパシタ、レジスタ（抵抗）、インダクタ、トランス、ＬＣＲ回路等の受動部品、オペアンプ等のアクティブフィルタ素子、ロジック、メモリ素子等の能動部品である。 The electronic component chip 21 has a silicon substrate 22 and a thin film element forming layer 23 formed on one surface of the silicon substrate 22, and the terminals 24 of the thin film element forming layer 23 are external terminals 13 or wiring layers 14. (In the illustrated example, connected to the external terminal 13). Such an electronic component chip 21 is preferably set so that the silicon substrate 22 has a thickness of 20 to 500 μm, the thin film element forming layer 23 has a thickness of 5 to 50 μm, and the total thickness of 25 to 550 μm. Moreover, it is preferable to set the external dimension of one electronic component chip 21 so that the length of one side is in the range of 0.5 to 20 mm.
The electronic parts included in the thin film element forming layer 23 are passive parts such as capacitors, resistors (resistors), inductors, transformers, and LCR circuits, active parts such as operational amplifiers, logic, and memory elements.

本発明の電子部品内蔵モジュール１１を構成する絶縁層１２は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機材料、あるいは、これらの有機材料とガラス繊維等を組み合せたもの等からなるものとすることができ、厚みは３０〜５５０μｍの範囲で設定することができる。
本発明の電子部品内蔵モジュール１１を構成する外部端子１３、配線層１４は、銅、銀、金、クロム、アルミニウム、ニッケル等の導電材料からなるものとすることができ、また、金／ニッケル／金の３層構造、ニッケル／金の２層構造等としてもよい。このような外部端子１３は、絶縁層１２と同じ厚みを有し、絶縁層１２を貫通するものである。また、配線層１４は、所望の外部端子１３を接続するように絶縁層１２内に配設されており、絶縁層１２内に完全に埋設されたものであってもよく、また、絶縁層１２のいずれか一方の面、あるいは両面に露出するものであってもよい。 The insulating layer 12 constituting the electronic component built-in module 11 of the present invention is made of an organic material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, or a polyimide resin, or a combination of these organic materials and glass fibers. The thickness can be set in the range of 30 to 550 μm.
The external terminal 13 and the wiring layer 14 constituting the electronic component built-in module 11 of the present invention can be made of a conductive material such as copper, silver, gold, chromium, aluminum, nickel, etc., and gold / nickel / A three-layer structure of gold or a two-layer structure of nickel / gold may be used. Such external terminals 13 have the same thickness as the insulating layer 12 and penetrate the insulating layer 12. The wiring layer 14 is disposed in the insulating layer 12 so as to connect a desired external terminal 13, and may be completely embedded in the insulating layer 12. It may be exposed on either one or both surfaces.

本発明の電子部品内蔵モジュール１１を構成する絶縁樹脂層１６は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機材料等とすることができる。絶縁樹脂層１６の厚みは、電子部品チップ２１を完全に被覆するように設定することができ、例えば、電子部品チップ２１の厚みよりも１〜２０μｍ程度厚くなるように設定することができる。
また、本発明の電子部品内蔵モジュール１１を構成する上下導通ビア１８は、銅、銀、金、クロム、アルミニウム等の導電材料からなるものとすることができ、太さは、例えば、２５〜５７０μｍの範囲で設定することができる。尚、本発明の電子部品内蔵モジュール１１は、この上下導通ビア１８の露出面に、はんだボール、金めっきバンプ、金スタッドバンプのいずれかを備えるものであってもよい。 The insulating resin layer 16 constituting the electronic component built-in module 11 of the present invention can be made of an organic material such as epoxy resin, benzocyclobutene resin, cardo resin, or polyimide resin. The thickness of the insulating resin layer 16 can be set so as to completely cover the electronic component chip 21, for example, can be set to be about 1 to 20 μm thicker than the thickness of the electronic component chip 21.
Further, the vertical conduction via 18 constituting the electronic component built-in module 11 of the present invention can be made of a conductive material such as copper, silver, gold, chromium, aluminum, and the thickness is, for example, 25 to 570 μm. Can be set within the range. The electronic component built-in module 11 of the present invention may be provided with any one of a solder ball, a gold plating bump, and a gold stud bump on the exposed surface of the vertical conduction via 18.

図３は、本発明の電子部品内蔵モジュールの他の実施形態を示す平面図であり、図４は図３に示される電子部品内蔵モジュールのＢ−Ｂ線矢視縦断面図である。
図３及び図４において、本発明の電子部品内蔵モジュール３１は、所望の部位に複数の外部端子３３を有する絶縁層３２と、この絶縁層３２の一方の面に配設された電子部品チップ４１と、この電子部品チップ４１を被覆するように絶縁層３２上に配設された絶縁樹脂層３６と、備えている。尚、図３は、電子部品内蔵モジュール３１を絶縁樹脂層３６側から見た平面図である。 FIG. 3 is a plan view showing another embodiment of the electronic component built-in module of the present invention, and FIG. 4 is a vertical cross-sectional view of the electronic component built-in module shown in FIG.
3 and 4, an electronic component built-in module 31 according to the present invention includes an insulating layer 32 having a plurality of external terminals 33 at a desired site, and an electronic component chip 41 disposed on one surface of the insulating layer 32. And an insulating resin layer 36 disposed on the insulating layer 32 so as to cover the electronic component chip 41. FIG. 3 is a plan view of the electronic component built-in module 31 as viewed from the insulating resin layer 36 side.

上記の外部端子３３は、絶縁層３２を貫通するように配設されている。尚、上述の電子部品内蔵モジュール１１と同様に、所望の外部端子３３を接続する配線層を絶縁層３２内に備えるものであってもよい。
また、絶縁樹脂層３６は、電子部品チップ４１を被覆するように絶縁層３２上に配設された絶縁樹脂層３６ａと、この絶縁樹脂層３６ａに配設された端子ビア３４と配線３５を被覆するように絶縁樹脂層３６ａに積層された絶縁樹脂層３６ｂからなっている。そして、この絶縁樹脂層３６には、この絶縁樹脂層３６を貫通し所望の外部端子３３と接続する上下導通ビア３８が配設されている。 The external terminal 33 is disposed so as to penetrate the insulating layer 32. Similar to the electronic component built-in module 11 described above, a wiring layer for connecting a desired external terminal 33 may be provided in the insulating layer 32.
The insulating resin layer 36 covers the insulating resin layer 36a disposed on the insulating layer 32 so as to cover the electronic component chip 41, and the terminal via 34 and the wiring 35 disposed on the insulating resin layer 36a. Thus, the insulating resin layer 36b is laminated on the insulating resin layer 36a. The insulating resin layer 36 is provided with a vertical conduction via 38 that penetrates the insulating resin layer 36 and connects to a desired external terminal 33.

上記の電子部品チップ４１は、シリコン基板４２と、このシリコン基板４２の一方の面に形成された薄膜素子形成層４３を有し、シリコン基板４２が絶縁層３２に固着されている。そして、薄膜素子形成層４３の端子４４は、上記の絶縁樹脂層３６ａに配設された端子ビア３４と配線３５を介して所望の上下導通ビア３８に接続している。
このような電子部品チップ４１は、上述の電子部品チップ２１と同様のものとすることができ、ここでの説明は省略する。
また、本発明の電子部品内蔵モジュール３１を構成する絶縁層３２、外部端子３３は、上述の電子部品内蔵モジュール１１を構成する絶縁層１２、外部端子１３と同様のものとすることができる。 The electronic component chip 41 includes a silicon substrate 42 and a thin film element forming layer 43 formed on one surface of the silicon substrate 42, and the silicon substrate 42 is fixed to the insulating layer 32. The terminal 44 of the thin film element formation layer 43 is connected to a desired vertical conduction via 38 via a terminal via 34 and a wiring 35 disposed in the insulating resin layer 36a.
Such an electronic component chip 41 can be the same as the electronic component chip 21 described above, and a description thereof is omitted here.
Further, the insulating layer 32 and the external terminal 33 constituting the electronic component built-in module 31 of the present invention can be the same as the insulating layer 12 and the external terminal 13 constituting the electronic component built-in module 11 described above.

本発明の電子部品内蔵モジュール３１を構成する絶縁樹脂層３６（３６ａ、３６ｂ）の材質は、上述の絶縁樹脂層１６と同様のものとすることができる。また、絶縁樹脂層３６ａの厚みは、電子部品チップ４１を完全に被覆するように設定することができ、例えば、電子部品チップ４１の厚みよりも１〜２０μｍ程度厚くなるように設定することができる。さらに、絶縁樹脂層３６ｂの厚みは、絶縁樹脂層３６ａに配設された端子ビア３４と配線３５を完全に被覆するように設定することができ、例えば、３〜２０μｍ程度の範囲で設定することができる。   The material of the insulating resin layer 36 (36a, 36b) constituting the electronic component built-in module 31 of the present invention can be the same as that of the insulating resin layer 16 described above. Further, the thickness of the insulating resin layer 36a can be set so as to completely cover the electronic component chip 41, and can be set to be, for example, about 1 to 20 μm thicker than the thickness of the electronic component chip 41. . Furthermore, the thickness of the insulating resin layer 36b can be set so as to completely cover the terminal via 34 and the wiring 35 disposed in the insulating resin layer 36a, and for example, set in the range of about 3 to 20 μm. Can do.

また、本発明の電子部品内蔵モジュール３１を構成する端子ビア３４、配線３５、上下導通ビア３８は、銅、銀、金、クロム、アルミニウム等の導電材料からなるものとすることができる。また、端子ビア３４の太さは、例えば、１０〜１００μｍの範囲で設定することができ、上下導通ビア３８の太さは、例えば、１０〜５００μｍの範囲で設定することができる。尚、本発明の電子部品内蔵モジュール３１は、上下導通ビア３８の露出面にはんだボール、金めっきバンプ、金スタッドバンプのいずれかを備えるものであってもよい。   Further, the terminal via 34, the wiring 35, and the vertical conduction via 38 constituting the electronic component built-in module 31 of the present invention can be made of a conductive material such as copper, silver, gold, chromium, and aluminum. Further, the thickness of the terminal via 34 can be set in a range of 10 to 100 μm, for example, and the thickness of the vertical conduction via 38 can be set in a range of 10 to 500 μm, for example. The electronic component built-in module 31 of the present invention may be provided with any one of a solder ball, a gold plating bump, and a gold stud bump on the exposed surface of the vertical conduction via 38.

このような本発明の電子部品内蔵モジュールは、基板を備えておらず、絶縁樹脂層内に電子部品チップが内蔵されているので小型、薄型化が可能である。また、上下導通ビアが絶縁樹脂層中に配設されているので、例えば、本発明の電子部品内蔵モジュールを複数重ねて積層構造とした場合、あるいは、他の電子部品内蔵モジュール等と重ねて積層構造とした場合に、各モジュール間の導通を容易にとることができる。
尚、上述の実施形態では、電子部品内蔵モジュールは２個の電子部品チップを内蔵するものであるが、本発明の電子部品内蔵モジュールでは、内蔵する電子部品チップの個数に限定はなく、また、配設位置、配設間隔等も任意に設定することができる。
上述の実施形態では、上下導通ビアが電子部品チップの各辺に対応して２個づつ配設され、各電子部品チップが有する端子の数が４個であるが、これは本発明を説明するために便宜的に設定した個数であり、これらに限定されるものではない。 Such an electronic component built-in module of the present invention does not include a substrate, and an electronic component chip is built in the insulating resin layer, so that it can be reduced in size and thickness. In addition, since the vertical conductive vias are arranged in the insulating resin layer, for example, when a plurality of electronic component built-in modules of the present invention are stacked to form a laminated structure, or stacked with other electronic component built-in modules, etc. In the case of the structure, conduction between the modules can be easily obtained.
In the above-described embodiment, the electronic component built-in module contains two electronic component chips. However, in the electronic component built-in module of the present invention, the number of built-in electronic component chips is not limited. Arrangement positions, arrangement intervals and the like can be arbitrarily set.
In the above-described embodiment, two vertical conductive vias are provided corresponding to each side of the electronic component chip, and each electronic component chip has four terminals. This explains the present invention. Therefore, the number is set for convenience, and is not limited thereto.

［電子部品内蔵モジュールの製造方法］
図５は、本発明の電子部品内蔵モジュールの製造方法の一実施形態を説明するための工程図である。
本発明の電子部品内蔵モジュールの製造方法では、まず、基材１の一方の面に絶縁層１２を形成し、この絶縁層１２の所望の部位に外部端子１３と配線層１４を形成する（図５（Ａ））。基材１としては、銅、銅合金等の金属材料、シリコン等を使用することができ、厚みは、例えば、０．０５〜１ｍｍ程度とすることができる。 [Method of manufacturing electronic component built-in module]
FIG. 5 is a process diagram for explaining an embodiment of a method for producing an electronic component built-in module according to the present invention.
In the method for manufacturing an electronic component built-in module according to the present invention, first, the insulating layer 12 is formed on one surface of the substrate 1, and the external terminals 13 and the wiring layer 14 are formed at desired portions of the insulating layer 12 (see FIG. 5 (A)). As the base material 1, metal materials, such as copper and a copper alloy, silicon | silicone, etc. can be used, and thickness can be about 0.05-1 mm, for example.

絶縁層１２の形成は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の電気絶縁性樹脂材料を含有する塗布液、あるいは、これらの電気絶縁性樹脂材料とガラス繊維とを組み合わせたものを含有する塗布液を公知の塗布方法で塗布し、その後、加熱、紫外線照射、電子線照射等の所定の硬化処理を施すことにより行うことができる。   The insulating layer 12 is formed by applying a coating solution containing an electrically insulating resin material such as epoxy resin, benzocyclobutene resin, cardo resin, polyimide resin, or a combination of these electrically insulating resin materials and glass fibers. Can be performed by applying a predetermined curing treatment such as heating, ultraviolet irradiation, electron beam irradiation, and the like.

上記の外部端子１３と配線層１４の形成は、例えば、以下のように行うことができる。まず、感光性の絶縁樹脂材料を用いて絶縁層１２となる感光性絶縁樹脂層を形成し、この感光性絶縁樹脂層を所定のマスクを介して露光し、現像することにより、外部端子１３用の孔部と、配線層１４用の溝部を絶縁層１２に形成する。そして、洗浄後、上記の孔部、溝部と、絶縁層１２上に真空成膜法により導電層を形成し、絶縁層１２上の導電層にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。次に、このレジストパターンをマスクとして、上記の孔部と溝部の内部に電解めっきにより導電材料を析出させて外部端子１３、配線層１４を形成し、その後、レジストパターンと導電層を除去する。また、基材１の材質が導電体（金属）の場合は、絶縁層１２の周縁部を露出し、あるいは基材１の側面や裏面に電極を立て、上記の孔部、溝部に電解めっきにて導電材料を直接析出させて外部端子１３、配線層１４を形成してもよい。   The external terminal 13 and the wiring layer 14 can be formed as follows, for example. First, a photosensitive insulating resin layer to be the insulating layer 12 is formed using a photosensitive insulating resin material, and the photosensitive insulating resin layer is exposed through a predetermined mask and developed, whereby the external terminals 13 are used. And a groove for the wiring layer 14 are formed in the insulating layer 12. Then, after cleaning, a conductive layer is formed on the hole, groove, and insulating layer 12 by a vacuum film forming method, a resist layer is formed on the conductive layer on the insulating layer 12, and desired pattern exposure and development are performed. By doing so, a resist pattern is formed. Next, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating inside the hole and groove to form the external terminal 13 and the wiring layer 14, and then the resist pattern and the conductive layer are removed. Further, when the material of the base material 1 is a conductor (metal), the peripheral edge of the insulating layer 12 is exposed, or an electrode is placed on the side surface or the back surface of the base material 1, and the above hole and groove are subjected to electrolytic plating. Alternatively, the external terminal 13 and the wiring layer 14 may be formed by directly depositing a conductive material.

また、外部端子１３と配線層１４の形成は、以下のように行うこともできる。すなわち、炭酸ガスレーザー、ＵＶ−ＹＡＧレーザー等を用いて絶縁層１２に外部端子１３用の孔部、配線層１４用の溝部を形成する。そして、洗浄後、上記の孔部、溝部の内部、および絶縁層１２に無電解めっきにより導電層を形成し、この導電層上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことによりレジストパターンを形成する。次いで、このレジストパターンをマスクとして、上記の孔部と溝部の内部に電解めっきにより導電材料を析出させて外部端子１３、配線層１４を形成し、その後、レジストパターンと導電層を除去する。   Further, the formation of the external terminals 13 and the wiring layer 14 can also be performed as follows. That is, a hole for the external terminal 13 and a groove for the wiring layer 14 are formed in the insulating layer 12 using a carbon dioxide laser, a UV-YAG laser, or the like. Then, after cleaning, a conductive layer is formed by electroless plating on the hole, groove, and insulating layer 12, and a dry film resist is laminated on the conductive layer to perform desired pattern exposure and development. Thus, a resist pattern is formed. Next, using the resist pattern as a mask, a conductive material is deposited by electrolytic plating inside the hole and groove to form the external terminal 13 and the wiring layer 14, and then the resist pattern and the conductive layer are removed.

上記の導電材料としては、例えば、銅、銀、金、クロム、アルミニウム、ニッケル等を挙げることができ、外部端子１３、配線層１４を多層構造、例えば、ニッケル／銅／ニッケルの３層構造、ニッケル／金／ニッケルの３層構造、ニッケル／銀／ニッケルの３層構造、これらの３層構造のニッケルの代わりに、クロム、チタン等を用いた３層構造、あるいは、ニッケル／金、チタン／銅等の２層構造とすることができる。
次に、シリコン基板２２の一方の面に薄膜素子形成層２３を有する電子部品チップ２１を、薄膜素子形成層２３の端子２４が外部端子１３または配線層１４に接続するように、絶縁層１２上にフリップチップ実装する（図５（Ｂ））。電子部品チップ２１を構成する薄膜素子形成層２３は、キャパシタ、レジスタ（抵抗）、インダクタ、トランス、ＬＣＲ回路等の所望の薄膜受動素子、オペアンプ等のアクティブフィルタ素子、ロジック、メモリ素子等の所望の薄膜能動素子が形成されたものである。この薄膜素子形成層２３の厚みは３〜３０μｍ程度、電子部品チップ２１の厚みは１０〜５０μｍ程度とすることができる。 Examples of the conductive material include copper, silver, gold, chromium, aluminum, nickel, and the like. The external terminal 13 and the wiring layer 14 have a multilayer structure, for example, a three-layer structure of nickel / copper / nickel, Three-layer structure of nickel / gold / nickel, three-layer structure of nickel / silver / nickel, three-layer structure using chromium, titanium, etc. instead of nickel of these three-layer structures, or nickel / gold, titanium / A two-layer structure such as copper can be used.
Next, the electronic component chip 21 having the thin film element forming layer 23 on one surface of the silicon substrate 22 is placed on the insulating layer 12 so that the terminal 24 of the thin film element forming layer 23 is connected to the external terminal 13 or the wiring layer 14. Flip chip mounting is performed (FIG. 5B). The thin film element forming layer 23 constituting the electronic component chip 21 includes desired thin film passive elements such as capacitors, resistors (resistors), inductors, transformers, and LCR circuits, active filter elements such as operational amplifiers, logic, and memory elements. A thin film active element is formed. The thin film element forming layer 23 can have a thickness of about 3 to 30 μm, and the electronic component chip 21 can have a thickness of about 10 to 50 μm.

次いで、実装した電子部品チップ２１を被覆するように、絶縁層１２上に絶縁樹脂層１６を形成し、電子部品チップ２１の非配設部位において絶縁樹脂層１６を貫通し所望の外部端子１３または配線層１４（図示例では外部端子１３）が露出するように複数の微細孔１７を形成する（図５（Ｃ））。
絶縁樹脂層１６は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の絶縁樹脂材料を用いて形成することができる。 Next, an insulating resin layer 16 is formed on the insulating layer 12 so as to cover the mounted electronic component chip 21, and penetrates the insulating resin layer 16 at a non-arranged portion of the electronic component chip 21, so that a desired external terminal 13 or A plurality of fine holes 17 are formed so that the wiring layer 14 (external terminal 13 in the illustrated example) is exposed (FIG. 5C).
The insulating resin layer 16 can be formed using an insulating resin material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, or a polyimide resin.

微細孔１７の形成は、例えば、絶縁樹脂層１６上にマスクパターンを形成し、露出している絶縁樹脂層１６に対して、プラズマを利用したドライエッチング法であるＩＣＰ−ＲＩＥ（Inductively Coupled Plasma − Reactive Ion Etching：誘導結合プラズマ−反応性イオンエッチング）法で穿孔することにより形成することができる。この微細孔１７の開口寸法は、次工程で形成する上下導通ビアの寸法に応じて適宜設定することができる。また、微細孔１７は、炭酸ガスレーザー、ＵＶ−ＹＡＧレーザー等を用いて形成することができる。さらに、感光性の絶縁樹脂材料を用いて絶縁樹脂層１６となる感光性絶縁樹脂層を形成し、この感光性絶縁樹脂層を所定のマスクを介して露光、現像することにより微細孔１７を形成することもできる。   The fine holes 17 are formed by, for example, forming a mask pattern on the insulating resin layer 16 and applying ICP-RIE (Inductively Coupled Plasma −), which is a dry etching method using plasma to the exposed insulating resin layer 16. It can be formed by perforating by the Reactive Ion Etching method. The opening size of the fine hole 17 can be appropriately set according to the size of the vertical conduction via formed in the next process. The fine holes 17 can be formed using a carbon dioxide laser, a UV-YAG laser, or the like. Further, a photosensitive insulating resin layer to be the insulating resin layer 16 is formed using a photosensitive insulating resin material, and the fine holes 17 are formed by exposing and developing the photosensitive insulating resin layer through a predetermined mask. You can also

次に、微細孔１７内に導電材料を充填して上下導通ビア１８を形成する（図５（Ｄ））。微細孔１７内への導電材料の充填は、例えば、微細孔１７内と絶縁樹脂層１６上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。次いで、このレジストパターンをマスクとして、微細孔１７内に電解めっきにより導電材料を析出させ、その後、レジストパターンと導電層を除去する。
尚、本発明では、電子部品チップ２１の実装前に、予め、めっきビアポストを外部端子１３上に設けておき、電子部品チップ２１の実装後に、絶縁樹脂層１６で電子部品２１を被覆し、次いで、ＣＭＰ（化学的機械研磨）等により表面平坦化を行うと同時に、めっきビアポストを露出させて上下導通ビア１８としてもよい。 Next, a conductive material is filled in the micro holes 17 to form the vertical conduction vias 18 (FIG. 5D). The conductive material is filled into the micro holes 17 by, for example, forming a conductive layer in the micro holes 17 and the insulating resin layer 16 by a vacuum film forming method, forming a resist layer on the conductive layer, and then forming a desired pattern. A resist pattern is formed by performing exposure and development. Next, using this resist pattern as a mask, a conductive material is deposited in the fine holes 17 by electrolytic plating, and then the resist pattern and the conductive layer are removed.
In the present invention, a plating via post is provided on the external terminal 13 in advance before mounting the electronic component chip 21, and after mounting the electronic component chip 21, the electronic component 21 is covered with the insulating resin layer 16, and then The surface via planarization may be performed by CMP (Chemical Mechanical Polishing) or the like, and at the same time, the plated via post may be exposed to form the vertical conductive via 18.

上下導通ビア１８を構成する導電材料としては、例えば、銅、銀、金、クロム、アルミニウム等を挙げることができる。
次いで、基材１を除去することにより、本発明の電子部品内蔵モジュール１１を得ることができる（図５（Ｅ））。基材１の除去は、例えば、選択エッチング、基材１の裏面側からの研磨等により行うことができる。 Examples of the conductive material constituting the vertical conduction via 18 include copper, silver, gold, chromium, and aluminum.
Next, by removing the substrate 1, the electronic component built-in module 11 of the present invention can be obtained (FIG. 5E). The removal of the base material 1 can be performed by, for example, selective etching, polishing from the back surface side of the base material 1 or the like.

図６及び図７は、本発明の電子部品内蔵モジュールの製造方法の他の実施形態を説明するための工程図である。
本発明の電子部品内蔵モジュールの製造方法では、まず、基材１０の一方の面に絶縁層３２を形成し、この絶縁層３２の所望の部位に外部端子３３を形成する（図６（Ａ））。基材１０としては、上述の基材１と同様のものを使用することができる。また、絶縁層３２、外部端子３３の形成は、上述の絶縁層１２、外部端子１３の形成と同様に行うことができる。尚、所望の外部端子３３を接続する配線層を絶縁層３２内に形成する場合には、上述の配線層１４の形成と同様に行うことができる。 6 and 7 are process diagrams for explaining another embodiment of the method for manufacturing the electronic component built-in module of the present invention.
In the method for manufacturing an electronic component built-in module according to the present invention, first, the insulating layer 32 is formed on one surface of the substrate 10, and the external terminal 33 is formed at a desired portion of the insulating layer 32 (FIG. 6A). ). As the base material 10, the same material as the base material 1 described above can be used. The insulating layer 32 and the external terminal 33 can be formed in the same manner as the insulating layer 12 and the external terminal 13 described above. In addition, when forming the wiring layer which connects the desired external terminal 33 in the insulating layer 32, it can carry out similarly to formation of the above-mentioned wiring layer 14. FIG.

次に、シリコン基板４２の一方の面に薄膜素子形成層４３を有する電子部品チップ４１を、シリコン基板４２側において絶縁層３２上に固着する（図６（Ｂ））。電子部品チップ４１を構成する薄膜素子形成層４３は、キャパシタ、レジスタ（抵抗）、インダクタ、トランス、ＬＣＲ回路等の受動部品、オペアンプ等のアクティブフィルタ素子、ロジック、メモリ素子等の能動部品のような所望の薄膜素子が形成されたものである。この薄膜素子形成層４３の厚みは１〜３０μｍ程度、電子部品チップ４１の厚みは２０〜１００μｍ程度とすることができる。   Next, the electronic component chip 41 having the thin film element formation layer 43 on one surface of the silicon substrate 42 is fixed on the insulating layer 32 on the silicon substrate 42 side (FIG. 6B). The thin film element forming layer 43 constituting the electronic component chip 41 is a passive component such as a capacitor, a resistor (resistance), an inductor, a transformer, or an LCR circuit, an active filter element such as an operational amplifier, an active component such as a logic or a memory element. A desired thin film element is formed. The thin film element formation layer 43 can have a thickness of about 1 to 30 μm, and the electronic component chip 41 can have a thickness of about 20 to 100 μm.

次いで、実装した電子部品チップ４１を被覆するように、絶縁層３２上に絶縁樹脂層３６ａを形成する。そして、電子部品チップ４１の非配設部位において絶縁樹脂層３６ａを貫通し所望の外部端子３３が露出するように複数の微細孔３７を形成するとともに、薄膜素子形成層４３の端子４４が露出するように端子ビア用孔部３９を形成する（図６（Ｃ））。   Next, an insulating resin layer 36 a is formed on the insulating layer 32 so as to cover the mounted electronic component chip 41. Then, a plurality of fine holes 37 are formed so as to penetrate the insulating resin layer 36a and expose the desired external terminals 33 at the non-arranged portion of the electronic component chip 41, and the terminals 44 of the thin film element forming layer 43 are exposed. Thus, a terminal via hole 39 is formed (FIG. 6C).

絶縁樹脂層３６ａは、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の絶縁樹脂材料を用いて形成することができる。
微細孔３７、端子ビア用孔部３９は、例えば、感光性の絶縁樹脂材料を用いて絶縁樹脂層３６ａとなる感光性絶縁樹脂層を形成し、この感光性絶縁樹脂層を所定のマスクを介して露光、現像することにより形成することができる。また、炭酸ガスレーザー、ＵＶ−ＹＡＧレーザー等を用いて微細孔３７、端子ビア用孔部３９を形成することもできる。微細孔３７の開口寸法は、次工程で形成する上下導通ビアの寸法に応じて適宜設定することができる。また、端子ビア用孔部３９の開口寸法は、例えば、５〜１００μｍの範囲で設定することができる。 The insulating resin layer 36a can be formed using an insulating resin material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, or a polyimide resin.
The fine holes 37 and the terminal via holes 39 are formed, for example, by forming a photosensitive insulating resin layer to be the insulating resin layer 36a using a photosensitive insulating resin material, and passing the photosensitive insulating resin layer through a predetermined mask. It can be formed by exposing and developing. Further, the fine holes 37 and the terminal via holes 39 can be formed using a carbon dioxide laser, a UV-YAG laser, or the like. The opening size of the fine hole 37 can be appropriately set according to the size of the vertical conduction via formed in the next step. Moreover, the opening dimension of the hole part 39 for terminal vias can be set in the range of 5-100 micrometers, for example.

次に、微細孔３７、端子ビア用孔部３９内に導電材料を充填して上下導通ビア３８と端子ビア３４を形成するとともに、端子ビア３４と所望の上下導通ビア３８とを接続するための配線３５を形成する（図６（Ｄ））。微細孔３７、端子ビア用孔部３９内への導電材料の充填と、配線３５の形成は、例えば、以下のように行うことができる。すなわち、微細孔３７、端子ビア用孔部３９内と絶縁樹脂層３６ａ上に真空成膜法により導電層を形成し、この導電層上に感光性レジスト層を形成し、所望のパターン露光、現像を行うことにより配線３５を形成するためのレジストパターンを形成する。次いで、このレジストパターンをマスクとして、微細孔３７、端子ビア用孔部３９内と、露出している導電層上に電解めっきにより導電材料を析出させ、その後、レジストパターンと導電層を除去する。
上下導通ビア３８、端子ビア３４、および配線３５を構成する導電材料としては、例えば、銅、銀、金、クロム、アルミニウム等を挙げることができる。 Next, the fine hole 37 and the terminal via hole 39 are filled with a conductive material to form the vertical conduction via 38 and the terminal via 34, and for connecting the terminal via 34 and the desired vertical conduction via 38. A wiring 35 is formed (FIG. 6D). The filling of the conductive material into the fine hole 37 and the terminal via hole 39 and the formation of the wiring 35 can be performed, for example, as follows. That is, a conductive layer is formed in the fine hole 37, the terminal via hole 39 and on the insulating resin layer 36a by a vacuum film forming method, a photosensitive resist layer is formed on the conductive layer, and desired pattern exposure and development are performed. To form a resist pattern for forming the wiring 35. Next, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the fine holes 37 and the terminal via holes 39 and on the exposed conductive layer, and then the resist pattern and the conductive layer are removed.
Examples of the conductive material constituting the vertical conduction via 38, the terminal via 34, and the wiring 35 include copper, silver, gold, chromium, and aluminum.

次に、端子ビア３４と配線３５を被覆し、上下導通ビア３８を露出するように被覆層としての絶縁樹脂層３６ｂを形成する（図７（Ａ））。絶縁樹脂層３６ｂの形成は、例えば、以下のように行うことができる。まず、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の感光性の絶縁樹脂材料を用いて感光性絶縁樹脂層を形成する。次いで、この感光性絶縁樹脂層を所定のマスクを介して露光、現像することにより、上下導通ビア３８を露出させるための開口部３６ｂ′を備えた絶縁樹脂層３６ｂを形成する。   Next, the terminal via 34 and the wiring 35 are covered, and an insulating resin layer 36b as a covering layer is formed so as to expose the vertical conduction via 38 (FIG. 7A). The insulating resin layer 36b can be formed as follows, for example. First, a photosensitive insulating resin layer is formed using a photosensitive insulating resin material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, or a polyimide resin. Next, this photosensitive insulating resin layer is exposed and developed through a predetermined mask to form an insulating resin layer 36b having an opening 36b 'for exposing the vertical conductive via 38.

次に、開口部３６ｂ′に露出している上下導通ビア３８上に、絶縁樹脂層３６ｂと同一面となるように（例えば、上記の上下導通ビア３８の形成と同様の手法により）導電材料を充填して上下導通ビア３８′を形成する（図７（Ｂ））。
次いで、基材１０を除去することにより、本発明の電子部品内蔵モジュール３１を得ることができる（図７（Ｃ））。基材１０の除去は、例えば、選択エッチング、基材１０の裏面側からの研磨等により行うことができる。
上述の電子部品内蔵モジュールの製造方法は例示であり、これに限定されるものではない。 Next, a conductive material is formed on the vertical conduction via 38 exposed in the opening 36b 'so as to be flush with the insulating resin layer 36b (for example, by the same method as the formation of the vertical conduction via 38). The upper and lower conductive vias 38 'are formed by filling (FIG. 7B).
Next, by removing the substrate 10, the electronic component built-in module 31 of the present invention can be obtained (FIG. 7C). The removal of the base material 10 can be performed by, for example, selective etching, polishing from the back surface side of the base material 10, or the like.
The method for manufacturing the electronic component built-in module described above is an example, and the present invention is not limited to this.

次に、具体的実施例を挙げて本発明を更に詳細に説明する。
厚み３０μｍのシリコン基板の一方の面に、受動部品として薄膜キャパシタを具備する薄膜素子形成層（厚み１０μｍ）を設けた。その後、シリコン基板と薄膜素子形成層からなる積層体をダイシングして、５ｍｍ×５ｍｍの大きさの電子部品チップを作製した。
一方、厚み１００μｍのシリコン基板を基材として準備し、この基材の片面に、ベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して、感光性絶縁層（厚み８μｍ）を形成した。
次に、外部端子形成用のマスクを介して上記の感光性絶縁層を露光し、現像を行った。これにより、絶縁層を形成するとともに、外部端子形成用の孔部（内径３０μｍ）と、配線層形成用の溝部（幅１０μｍ）を絶縁層の所定位置に形成した。 Next, the present invention will be described in more detail with specific examples.
A thin film element forming layer (thickness 10 μm) having a thin film capacitor as a passive component was provided on one surface of a 30 μm thick silicon substrate. Thereafter, the laminate composed of the silicon substrate and the thin film element formation layer was diced to produce an electronic component chip having a size of 5 mm × 5 mm .
On the other hand, a silicon substrate having a thickness of 100 μm was prepared as a base material, and a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied to one side of the base material with a spin coater and dried. A layer (thickness 8 μm) was formed.
Next, the photosensitive insulating layer was exposed through a mask for forming external terminals and developed. Thus, an insulating layer was formed, and a hole for forming an external terminal (inner diameter: 30 μm) and a groove for forming a wiring layer (width: 10 μm) were formed at predetermined positions of the insulating layer.

次いで、洗浄した後、外部端子形成用の孔部内、配線層形成用の溝部内、および絶縁層上に、スパッタリング法によりチタン／銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、フォトマスクを介し露光、現像して、外部端子と配線層とを形成するためのレジストパターン（外部端子形成用の孔部、配線層形成用の溝部が露出する）を形成した。このレジストパターンをマスクとし、上記の導電層を給電層として、チタン、銅、チタンの順に電解めっきで析出した。これにより、チタン／銅／チタンの積層構造からなる外部端子と配線層を形成し、その後、レジストパターンと導電層を除去した。   Next, after cleaning, a conductive layer made of titanium / copper is formed by sputtering in the hole for forming the external terminal, the groove for forming the wiring layer, and the insulating layer, and a liquid resist ( Tokyo Ohka Kogyo Co., Ltd. LA900) was applied. Next, exposure and development were performed through a photomask to form a resist pattern (external terminal forming hole portions and wiring layer forming groove portions were exposed) for forming external terminals and wiring layers. Using this resist pattern as a mask and the above conductive layer as a power feeding layer, titanium, copper and titanium were deposited in this order by electrolytic plating. Thus, external terminals and wiring layers having a laminated structure of titanium / copper / titanium were formed, and then the resist pattern and the conductive layer were removed.

次に、電子部品チップのシリコン基板側を絶縁層上に固着して複数の電子部品チップを配設した。このように配設された各電子部品チップの間隔は１ｍｍであった。
次に、電子部品チップを被覆するようにベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布し、乾燥して感光性絶縁樹脂層を形成した。次いで、この感光性絶縁樹脂層をマスクを介して露光し、現像を行った。これにより、絶縁樹脂層（電子部品チップの非配設部位での厚み５０μｍ）を形成し、また、電子部品チップの非配設部位に、各電子部品チップを囲むように開口径５０μｍの微細孔を０．３ｍｍピッチで複数形成するとともに、電子部品チップの薄膜素子形成層の端子が露出するように端子ビア用孔部を複数形成した。尚、上記の微細孔は、奥部に外部端子が露出したものであった。 Next, a plurality of electronic component chips were disposed by fixing the silicon substrate side of the electronic component chips on the insulating layer. The interval between the electronic component chips thus arranged was 1 mm.
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied by a spin coater so as to cover the electronic component chip, and dried to form a photosensitive insulating resin layer. Next, this photosensitive insulating resin layer was exposed through a mask and developed. As a result, an insulating resin layer (thickness of 50 μm at the non-arranged part of the electronic component chip) is formed, and fine holes with an opening diameter of 50 μm are encircled in the non-arranged part of the electronic component chip. Are formed at a pitch of 0.3 mm, and a plurality of terminal via holes are formed so that the terminals of the thin film element forming layer of the electronic component chip are exposed. In addition, said fine hole was an external terminal exposed in the inner part.

次いで、洗浄した後、微細孔の内部、端子ビア用孔部の内部、および絶縁樹脂層上に、スパッタリング法によりチタンと銅からなる導電層を形成し、この導電層上に感光性のフィルムレジスト（東京応化工業（株）製 ＢＦ４０５）をラミネートした。その後、フォトマスクを介して露光、現像して、上下導通ビアと端子ビアと配線を形成するためのレジストパターンを形成した。次に、上記のレジストパターンをマスクとして電解銅めっきにより微細孔の内部、端子ビア用孔部の内部を銅で充填するとともに、配線を形成した。その後、レジストパターンと導電層を除去した。これにより、絶縁樹脂層を貫通し、外部端子に接続された上下導通ビアを形成し、この上下導通ビアは配線、端子ビアを介して薄膜素子形成層の端子に接続されるものであった。   Next, after washing, a conductive layer made of titanium and copper is formed by sputtering on the inside of the fine hole, the inside of the terminal via hole, and the insulating resin layer, and a photosensitive film resist is formed on this conductive layer. (BF405 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was laminated. Thereafter, exposure and development were performed through a photomask to form a resist pattern for forming vertical conductive vias, terminal vias, and wiring. Next, the inside of the fine hole and the inside of the terminal via hole were filled with copper by electrolytic copper plating using the resist pattern as a mask, and wiring was formed. Thereafter, the resist pattern and the conductive layer were removed. Thus, a vertical conduction via that penetrates the insulating resin layer and is connected to the external terminal is formed, and this vertical conduction via is connected to the terminal of the thin film element formation layer via the wiring and the terminal via.

次に、端子ビアと配線３５を被覆するようにベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布し、乾燥して感光性絶縁樹脂層を形成した。次いで、この感光性絶縁樹脂層をマスクを介して露光し、現像を行った。これにより、上下導通ビアを露出させるための開口部を備えた絶縁樹脂層（厚み６５μｍ）を形成した。次いで、開口部に露出している上下導通ビア上に、絶縁樹脂層３６ｂと同一面となるように、上記の上下導通ビアの形成と同様の手法により、導電材料を充填して上下導通ビアを形成した。
次に、基材であるシリコン基板を水酸化カリウム水溶液を用いてエッチングした。その後、ダイシングして、電子部品チップ２個を内蔵した本発明の電子部品内蔵モジュール（１５ｍｍ×１５ｍｍ、厚み６０μｍ）を得た。 Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied by a spin coater so as to cover the terminal via and the wiring 35, and dried to form a photosensitive insulating resin layer. Next, this photosensitive insulating resin layer was exposed through a mask and developed. As a result, an insulating resin layer (thickness: 65 μm) having an opening for exposing the vertical conduction via was formed. Next, a conductive material is filled into the vertical conductive via so as to be flush with the insulating resin layer 36b on the vertical conductive via exposed at the opening by the same method as the formation of the vertical conductive via. Formed.
Next, the silicon substrate as a base material was etched using a potassium hydroxide aqueous solution. Thereafter, dicing was performed to obtain an electronic component built-in module (15 mm × 15 mm, thickness 60 μm) of the present invention incorporating two electronic component chips.

小型で高信頼性が要求される半導体装置や各種電子機器への用途にも適用できる。   The present invention can also be applied to small semiconductor devices and various electronic devices that require high reliability.

本発明の電子部品内蔵モジュールの一実施形態を示す平面図である。It is a top view which shows one Embodiment of the electronic component built-in module of this invention. 図１に示される電子部品内蔵モジュールのＡ−Ａ線矢視縦断面図である。It is an AA arrow longitudinal cross-sectional view of the electronic component built-in module shown by FIG. 本発明の電子部品内蔵モジュールの他の実施形態を示す平面図である。It is a top view which shows other embodiment of the electronic component built-in module of this invention. 図３に示される電子部品内蔵モジュールのＢ−Ｂ線矢視縦断面図である。FIG. 4 is a longitudinal sectional view of the electronic component built-in module shown in FIG. 本発明の電子部品内蔵モジュールの製造方法の一実施形態を説明する工程図である。It is process drawing explaining one Embodiment of the manufacturing method of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの製造方法の他の実施形態を説明する工程図である。It is process drawing explaining other embodiment of the manufacturing method of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの製造方法の他の実施形態を説明する工程図である。It is process drawing explaining other embodiment of the manufacturing method of the electronic component built-in module of this invention.

符号の説明Explanation of symbols

１，１０…基材
１１，３１…電子部品内蔵モジュール
１２，３２…絶縁層
１３，３３…外部端子
１４…配線層
１６，３６（３６ａ，３６ｂ）…絶縁樹脂層
１７，３７…微細孔
１８，３８…上下導通ビア
３４…端子ビア
３５…配線
２１，４１…電子部品チップ
２２，４２…シリコン基板
２３，４３…薄膜素子形成層
２４，４４…端子 DESCRIPTION OF SYMBOLS 1,10 ... Base material 11, 31 ... Electronic component built-in module 12, 32 ... Insulating layer 13, 33 ... External terminal 14 ... Wiring layer 16, 36 (36a, 36b) ... Insulating resin layer 17, 37 ... Fine hole 18, 38 ... Vertical conduction via 34 ... Terminal via 35 ... Wiring 21, 41 ... Electronic component chip 22, 42 ... Silicon substrate 23, 43 ... Thin film element formation layer 24, 44 ... Terminal

Claims (4)

基材の一方の面に絶縁層を形成し、次いで、該絶縁層を貫通する複数の外部端子を形成する工程と、
シリコン基板の一方の面に薄膜素子形成層を有する電子部品チップを、前記シリコン基板が当接するように前記絶縁層上に固着する工程と、
前記電子部品チップを被覆するように前記絶縁層上に絶縁樹脂層を形成し、電子部品チップの非配設部位において前記絶縁樹脂層を貫通し所望の前記外部端子が露出するように複数の微細孔を形成するとともに、前記薄膜素子形成層の端子が露出する端子ビア用孔部を前記絶縁樹脂層に形成する工程と、
前記微細孔と前記端子ビア用孔部に導電材料を充填して上下導通ビアと端子ビアを形成するとともに、該端子ビアと所望の前記上下導通ビアとを接続するための配線を形成する工程と、
前記端子ビアと配線を被覆し、前記上下導通ビアを露出するように被覆層としての絶縁樹脂層を形成する工程と、
前記基材を除去する工程と、を有することを特徴とする電子部品内蔵モジュールの製造方法。 Forming an insulating layer on one surface of the substrate, and then forming a plurality of external terminals penetrating the insulating layer;
Fixing an electronic component chip having a thin film element forming layer on one surface of a silicon substrate on the insulating layer so that the silicon substrate contacts;
An insulating resin layer is formed on the insulating layer so as to cover the electronic component chip, and a plurality of fine patterns are formed so that a desired external terminal is exposed through the insulating resin layer at a non-arranged portion of the electronic component chip. Forming a hole in the insulating resin layer while forming a hole and exposing a terminal via hole through which a terminal of the thin film element forming layer is exposed;
Filling the fine hole and the terminal via hole with a conductive material to form a vertical conduction via and a terminal via, and forming a wiring for connecting the terminal via and a desired vertical conduction via; ,
Covering the terminal via and wiring, and forming an insulating resin layer as a covering layer so as to expose the vertical conduction via; and
And a step of removing the base material. 前記外部端子を形成する工程にて、所望の前記外部端子を接続するための配線層を前記絶縁層に形成し、前記微細孔を形成する工程では、所望の外部端子または配線層が露出するように前記微細孔を形成することを特徴とする請求項１に記載の電子部品内蔵モジュールの製造方法。 In the step of forming the external terminal, a wiring layer for connecting the desired external terminal is formed on the insulating layer, and in the step of forming the fine hole, the desired external terminal or the wiring layer is exposed. The method for manufacturing an electronic component built-in module according to claim 1 , wherein the fine hole is formed in the electronic component. 被覆層としての絶縁樹脂層に露出している上下導通ビアに、絶縁樹脂層と同一面をなすように導電材料を充填する工程、あるいは、はんだボール、金めっきバンプ、金スタッドバンプのいずれかを形成する工程を有することを特徴とする請求項１または請求項２に記載の電子部品内蔵モジュールの製造方法。 Filling the vertical conductive via exposed in the insulating resin layer as a coating layer with a conductive material so that it is flush with the insulating resin layer, or any of solder balls, gold plating bumps, and gold stud bumps method of manufacturing an electronic component built-in module according to claim 1 or claim 2 characterized by having a step of forming. 前記基材は、金属またはシリコンであることを特徴とする請求項１乃至請求項３のいずれかに記載の電子部品内蔵モジュールの製造方法。 The substrate is a method of manufacturing an electronic component built-in module according to any one of claims 1 to 3, characterized in that a metal or silicon.
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