TW469569B - Method for manufacturing low-resistance polysilicon/metal gate structure - Google Patents
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Λ69 56 9 發明說明 1 ·發明的領域： 本發明係有關於半導體元件之製造方法，且特別是有 關於應用在金氧半導體上之低阻值複晶矽/金屬閘極結構 之製造方法。 2 ·習知技術： 由於金氧半導體元件尺寸全面性縮小化的發展，因而 使得接觸阻值與片（sheet)阻值增加。傳統上，閉極電極 使用複晶碎/矽化物閘極結構’如複晶石夕/矽化鶴，而此種 閘極結構會增加阻值而造成閘極RC延遲的增大，從而降低 效能。此情況是特別不利於高速記憶體晶片及邏輯元件的 應用。Λ69 56 9 Description of the invention 1. Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a low-resistance composite silicon / metal gate structure applied to a metal-oxide semiconductor. 2 · Known technology: Due to the overall reduction in size of metal oxide semiconductor devices, the contact resistance and sheet resistance have increased. Traditionally, the closed-electrode uses a polycrystalline shredded / silicided gate structure such as a polycrystalline stone / silicone crane. Such a gate structure will increase the resistance value and increase the gate RC delay, thereby reducing the efficiency. This situation is particularly detrimental to the application of high-speed memory chips and logic elements.
Si taram等人於美國專利No,5, 384, 285揭露一種克服 複晶妙/矽化物閘極電極之高閘極阻值的方法，複晶妙/石夕 化物閘極電極之高阻值可藉由防止製程中過渡金屬的反應 而降低’特別是與氧反應。Sitaram所提出的方法是在過 渡金屬層之上形成一氮化鈦或氮氧化鈦上蓋層來防止過渡 金屬層的反應，上蓋層是在矽化物形成之後移除。儘管此 方法可降低；e夕化物層的片（sheet)阻值’然而其無法達成 本發明所能達到的降低接觸阻值或複晶矽/鎢整體閘極電 極之阻值。此方法亦無法達成本發明所能達到的熱穩定 性。 〜 同樣地’ Apte等人於美國專利No. 5, 593, 924揭露一種 利用可移除的金屬上蓋層，如氮化欽以減輕石夕化物層内的Si taram et al., In U.S. Patent No. 5,384,285, disclose a method to overcome the high gate resistance of a polycrystalline / silicide gate electrode. It reduces' especially with oxygen by preventing the reaction of transition metals during the process. The method proposed by Sitaram is to form a titanium nitride or titanium oxynitride cap layer on the transition metal layer to prevent the reaction of the transition metal layer. The cap layer is removed after the silicide is formed. Although this method can reduce the sheet resistance of the oxide layer ', it cannot achieve the reduction in contact resistance or the resistance of the polycrystalline silicon / tungsten integrated gate electrode that can be achieved by the present invention. This method also fails to achieve the thermal stability that can be achieved by the invention. ~ Similarly, Apte et al., U.S. Patent No. 5,593, 924, disclose a method of using a removable metal cap layer, such as nitride, to reduce the
469 56 9 五、發明說明（2) 污染從而降低片（sheet)阻值。此發明並未陳述前述之複 晶矽/矽化物間極電極之其他相關問題。 在很多的相關專利及技術文獻，都有說明解決上述問 題之不同缺失的方法，最接近且相關的技術發展專利文獻 可考慮則述之美國專利No. 5，384，285(Sitaram等人）及美 國專利No.5, 593, 924 (Apte等人），以及下面之美國專 利° 美國專利No. 5，103，272 (Nish iyama)揭露一種於複晶 石夕閘極及源/沒極區之上形成矽化鈦層之製程，此方法係 利用氮化鈦障壁層來防止矽化鈦層的結塊。 美國專利No_5, 550, 079 (Lin)揭露一種具有氮化鎢障 壁層之矽化物分流器。 美國專利No. 5, 668, 065 (Lin)揭露一種複晶矽/矽化 鎢/氮化矽之閘極結構。 發明概述： 本發明之目的為提供一種應用在金氧半導體上之閘極 結構之製造方法’此方法所製作之閘極結構可降低閘極之 片（sheet)阻值與接觸阻值，從而使RC延遲減至最低。 本發明之另—目的為製造一複合的複晶矽/金屬閘極 -構，此結構在大的溫度範圍内具有良好的熱穩定性。 —本發明尚有另一目的為提供一種於複晶矽層之上形成 擴散P早壁層之方法’此方法所形成之擴散障壁層不易剝469 56 9 V. Description of the invention (2) Contamination reduces sheet resistance. This invention does not state other related issues of the aforementioned polycrystalline silicon / silicide interelectrode. In many related patents and technical documents, there are different methods to solve the above problems. The closest and related technical development patent documents can be considered in US Patent No. 5,384,285 (Sitaram et al.) And U.S. Patent No. 5,593,924 (Apte et al.), And the following U.S. Patent ° U.S. Patent No. 5,103,272 (Nish iyama) discloses a method for the gate and source / inverter regions of polycrystalline stone This method uses a titanium nitride barrier layer to prevent the agglomeration of the titanium silicide layer. U.S. Patent No. 5,550,079 (Lin) discloses a silicide shunt having a tungsten nitride barrier layer. US Patent No. 5, 668, 065 (Lin) discloses a gate structure of polycrystalline silicon / silicided tungsten / silicon nitride. Summary of the Invention: The purpose of the present invention is to provide a method for manufacturing a gate structure applied to a metal-oxide semiconductor. The gate structure produced by this method can reduce the sheet resistance and contact resistance of the gate, so that RC delay is minimized. Another object of the present invention is to produce a composite polycrystalline silicon / metal gate structure, which has good thermal stability in a wide temperature range. — Another object of the present invention is to provide a method for forming a diffusion P early wall layer on a polycrystalline silicon layer. The diffusion barrier layer formed by this method is not easy to peel.
469 56 9 五、發明說明（3) 本發明還有另一目的為提供一種經濟及穩定的製程以 製造一應用在金氧半導體元件上之低阻值複晶矽/金屬閘 極。 為了達成上述目的，本發明提供一種製造—複合的複 晶矽/金屬閘極之方法，其具有：（丨）在形成一擴散障壁層 之前先施行一新穎的退火步驟及（2)此新穎的擴散障壁層 是由氮化钦層沉積在矽化鈦層之上所組成，或是為直接沉 積在複晶矽層之上之氮化鈦層。製程首先是於一矽基底之 上形成一第一絕緣層，再於第一絕緣層之上形成—複晶矽 層，在一關鍵步驟中，複晶矽層施以退火處理以防止後續 _ 之形成擴散障壁層的剝落。再於退火複晶矽層上形成一擴 散障壁層，此擴散障壁層是由氮化鈦層沉積在矽化鈦層之 上所組成’或疋為直接沉積在複晶梦層之上之氮化欽廣。 於障壁層之上形成一鎢層。於鎢層之上可形成一上蓋 層’上蓋層包括一氧化層及一氮化麥層。上蓋層、鎢層、 擴散障壁層及複晶矽層藉由圖案化而定義成一閘極結構。 本發明之基本製程步驟如表1所示。 表1469 56 9 V. Description of the invention (3) Another object of the present invention is to provide an economical and stable process for manufacturing a low-resistance polycrystalline silicon / metal gate for metal-oxide semiconductor devices. In order to achieve the above object, the present invention provides a method for manufacturing a composite polycrystalline silicon / metal gate, which has: (丨) performing a novel annealing step before forming a diffusion barrier layer and (2) this novel The diffusion barrier layer is composed of a nitride layer deposited on a titanium silicide layer, or a titanium nitride layer deposited directly on a polycrystalline silicon layer. The process first forms a first insulating layer on a silicon substrate, and then forms a polycrystalline silicon layer on the first insulating layer. In a key step, the polycrystalline silicon layer is annealed to prevent subsequent _ Exfoliation of the diffusion barrier layer is formed. A diffusion barrier layer is formed on the annealed polycrystalline silicon layer. The diffusion barrier layer is composed of a titanium nitride layer deposited on the titanium silicide layer, or a nitride nitride layer deposited directly on the polycrystalline dream layer. wide. A tungsten layer is formed on the barrier layer. An overcap layer may be formed on the tungsten layer. The overcap layer includes an oxide layer and a wheat nitride layer. The cap layer, the tungsten layer, the diffusion barrier layer, and the polycrystalline silicon layer are defined as a gate structure by patterning. The basic process steps of the present invention are shown in Table 1. Table 1
4 69 56 9 、^____ 五'發明說明（4) 第一實施例 第二實施例 — 沉豬氣化層 沉積氡化層 沉賴複晶矽層 沉禎複晶矽層 退火(防止刻落） 退火(防止剝落） _ 沉積鈦 沉積氮化鈦層 ~ __ 退火以形成矽化鈦層 沉稍鎢層 — 沉稍釓化鈦層 圖案化以定義閘極 — _ 沉稍鎢層 _ ®案化以定義閘極 ---- 本發明提供之閘極結構可大幅改善習知技術之間極片 阻值與接觸阻值，從而使!^延遲減至最低，進而增進元件 之效能。傳統閘極具有之片（sheet)阻值約2.5 Ohm/口， 接觸阻值約IE-3 Ohm · c#。而本發明所提供之閘極具 之片（sheet)阻值約i.6 〇hm/□，接觸阻值約2£_7价、 cm2 ° υπιη 齡不Ϊ ί 據本發明1造方法所製作 < 閘極經證明具有 定性。 ^•比傳、统閘極具有較佳之熱穩 為了讓本發明之上 明顯易懂’下文特舉 眚：的特徵、及優點能更 詳細說明如下： 實施例並配合所附圖式，作 圖式之簡單說明 為了讓本發明之 明顯易懂’所附圖± 遮和其他目的、特徵、 α附圖表說明如下： 和優點能更4 69 56 9, ^ ____ Five 'Description of the Invention (4) First embodiment Second embodiment—sinking pig gasification layer deposition tritium layer Shen lai polycrystalline silicon layer immersed polycrystalline silicon layer annealing (prevents pitting) annealing ( Preventing spalling) _ Deposition of titanium Deposition of titanium nitride layer __ Annealing to form titanium silicide layer Shen slightly tungsten layer — Shen slightly hafnium titanium patterned to define the gate — _ Shen slightly tungsten layer _ ® case to define the gate ---- The gate structure provided by the present invention can greatly improve the pole piece resistance value and contact resistance value of the conventional technology, thereby minimizing the delay, and thereby improving the performance of the device. The traditional gate has a sheet resistance of about 2.5 Ohm / port and a contact resistance of about IE-3 Ohm · c #. The sheet provided by the present invention has a sheet resistance value of about i.6 0hm / □, a contact resistance value of about 2 £ _7 valence, cm2 ° υπιη Ϊ 不 Ϊ ί produced according to the manufacturing method of the present invention & lt The gate has proven to be qualitative. ^ • Bichuan and the gate have better thermal stability. In order to make the present invention clearly understandable, the following special mentions: Features and advantages can be explained in more detail as follows: Examples and drawings In order to make the present invention obvious and easy to understand, the attached drawings and other objects, features, and α drawings are described as follows:
469569 五、發明說明（5) 第1、2A、2B、3及4圖係顯示依據本發明之實施例的 製程順序以製造應用在互補式金氧半導值 複晶矽/金屬閘極之剖面示意圖。 菔疋件上之低 [符號說明] 1〇〜矽基底；12〜第一絕緣層；14〜複晶矽層；14A〜退 火複晶矽層；16A〜矽化鈦層；16B〜氮化鈦層；16〜障壁 層’18〜鎢層；22A〜四乙氧基矽甲烷（TE〇s )層；22β氮 化矽層；22〜上蓋層；23〜閘極結構；26〜淡摻雜源/汲極 區；28〜閘極絕緣間隔層；30〜源/汲極區。 較佳實施例 本發明將配合所附圖式作詳細說明，本發明提供一種 製造方法以形成一應用在互補式金氧半導體元件上之低阻 值複晶梦/金屬閘極。 現在請參照第1圖，首先，於一矽基底（1〇)之上形成 一第一絕緣層（12)，第一絕緣層（12)較佳是為一厚度5〇至 150 Α之二氧化矽層而達到其目標厚度1〇〇Α。第―絕緣層 (12)可使用化學氣相沉積來形成亦可較佳的以習知技術之 熱氧化製程來形成。 亦請參照第1圖，於第一絕緣層（丨2)之上形成一複晶 矽層（14)，複晶矽層（14)較佳是藉由低壓化學氣相沉積 於600至800 C溫度範圍’形成厚度約5〇〇至15〇〇入。 在一關鍵步驟中，複晶矽層（14)是在氮氣氣氛中退 火’溫度是設定在800至950 °C之間，退火2〇至120分鐘，469569 V. Description of the invention (5) Figures 1, 2A, 2B, 3, and 4 show the process sequence according to the embodiment of the present invention to manufacture a cross-section of a complementary metal-oxide-semiconductor silicon / metal gate schematic diagram. Low on components [Symbol description] 10 ~ silicon substrate; 12 ~ first insulating layer; 14 ~ polycrystalline silicon layer; 14A ~ annealed polycrystalline silicon layer; 16A ~ titanium silicide layer; 16B ~ titanium nitride layer 16 ~ barrier layer '18 ~ tungsten layer; 22A ~ tetraethoxysilylmethane (TE0s) layer; 22β silicon nitride layer; 22 ~ cap layer; 23 ~ gate structure; 26 ~ lightly doped source / Drain region; 28 ~ gate insulation spacer; 30 ~ source / drain region. Preferred Embodiments The present invention will be described in detail with reference to the accompanying drawings. The present invention provides a manufacturing method for forming a low-resistance complex crystal dream / metal gate applied to a complementary metal-oxide semiconductor device. Now referring to FIG. 1, first, a first insulating layer (12) is formed on a silicon substrate (10), and the first insulating layer (12) is preferably a thickness of 50 to 150 Å in oxidization. Silicon layer to reach its target thickness of 100A. The first-insulating layer (12) can be formed using chemical vapor deposition, and can also be preferably formed by a thermal oxidation process using conventional techniques. Please also refer to Fig. 1. A polycrystalline silicon layer (14) is formed on the first insulating layer (丨 2). The polycrystalline silicon layer (14) is preferably 600 to 800 C by low-pressure chemical vapor deposition. The temperature range 'forms to a thickness of about 500 to 15,000 in. In a key step, the polycrystalline silicon layer (14) is annealed in a nitrogen atmosphere. The temperature is set between 800 and 950 ° C, and annealing is performed for 20 to 120 minutes.
$ 9頁 4，6 9 5 6 9 五、發明說明（6) 退火後複晶矽層（14)形成一退火複晶矽層（14A)。經由實 驗證實，在形成一擴散障壁層之前先施行退火複晶矽之步 驟，可減少後績之形成擴散障壁層的剝落。 第一實施例 在第一實施例中，於退火複晶石夕層之上形成一石夕化钦 層’之後，形成一氮化欽層而組合成一障壁層。請參照第 2A圖，一矽化鈦層（16A)是利用金屬矽化物製程形成於退 火複晶矽層（1 4 A)之上。表面是以氫氟酸來清潔。鈦層是 以濺鍍或化學氣相沉積形成厚度約30至60 A。濺鍍鈦層是 與暴露的複晶矽層進行金屬矽化物製程，如快速熱退火製 程（RTP)，溫度約介於550 °C至700 °C之間，進行30至120 秒。以化學氣相沉積鈦層是藉由氯化鈦（TiCi 4)及（h2)於 5 5 0 °C至7 0 0 °C之間反應而在原處形成矽化鈦。其次，實施 第二熱退火製程’在氮氣氣氛中，溫度約介於7〇〇艺至800 °C之間。經由此熱退火步驟，可使矽化鈦層（1 6 A)穩定。 然後’於矽化鈦層（1 6 A)之上以濺鍍或化學氣相沉積 形成一厚度約200至400 A之氮化鈦層（16B)。依據本發明 之第一實施例’障壁層（16)是由矽化鈦層（16A)及氮化鈦 層（1 6 B)所組成。 請參照第3圖，於障壁層（1 6)之上形成一厚度約5〇〇至 1 5 0 0 A之鎢層（18) ’鎢層（18)之形成較佳是使用化學氣相 沉積製程。於鎢層（18)之上較佳是形成一上蓋層（22)，上 蓋層（22)可包括一厚度約200至300 A之四乙氧基石夕子烧 CTEOS)層（22A)及一厚度約ι〇00至2500A之氮化石夕層$ 9 pages 4, 6 9 5 6 9 V. Description of the invention (6) The annealed polycrystalline silicon layer (14) forms an annealed polycrystalline silicon layer (14A) after annealing. It has been verified through experiments that the step of annealing the polycrystalline silicon before forming a diffusion barrier layer can reduce the spalling of the diffusion barrier layer formed later. First Embodiment In the first embodiment, after forming a silicon oxide layer on the annealed polycrystalline stone layer, a nitride layer is formed to form a barrier layer. Referring to FIG. 2A, a titanium silicide layer (16A) is formed on the annealed polycrystalline silicon layer (1 4 A) by a metal silicide process. The surface is cleaned with hydrofluoric acid. The titanium layer is formed by sputtering or chemical vapor deposition to a thickness of about 30 to 60 A. The sputtered titanium layer is a metal silicide process, such as a rapid thermal annealing process (RTP), with the exposed polycrystalline silicon layer at a temperature of about 550 ° C to 700 ° C for 30 to 120 seconds. The chemical vapor deposition of the titanium layer is carried out by reacting titanium chloride (TiCi 4) and (h2) between 5500 ° C and 700 ° C to form titanium silicide in situ. Secondly, a second thermal annealing process is performed 'in a nitrogen atmosphere at a temperature between about 700 ° C and 800 ° C. After this thermal annealing step, the titanium silicide layer (16 A) can be stabilized. Then, a titanium nitride layer (16B) having a thickness of about 200 to 400 A is formed on the titanium silicide layer (16 A) by sputtering or chemical vapor deposition. According to the first embodiment of the present invention, the barrier layer (16) is composed of a titanium silicide layer (16A) and a titanium nitride layer (16B). Referring to FIG. 3, a tungsten layer (18) is formed on the barrier layer (16) with a thickness of about 500 to 15 0 A. The formation of the tungsten layer (18) is preferably chemical vapor deposition. Process. An upper cap layer (22) is preferably formed on the tungsten layer (18). The upper cap layer (22) may include a tetraethoxy stone yakko (CTEOS) layer (22A) and a thickness of about ι0000 to 2500A nitride nitride layer
第10頁 1 69 56 9 五、發明說明（7) (Πι:、上益蓋層(22)、鎢層(18)、擴散障壁層(16)及複晶 二由圖案化而定義成-具有侧壁之間極結構 (23)二圖？化較佳是利用傳統的微影及反應離子蝕刻製程 U水化ί體如氣氣’或氟化氣體，如四氟化碳作為蝕 ' 進行。然後，藉由反應電漿蝕刻使用CHF3或0?4 + 112 作為蝕刻劑來去除鄰近聞極結構之第一絕緣層。 •亦請參照第3圖，利用淡摻雜源/汲極離子植入法 (LuhUj Doped Drain implantati〇n)，於複晶矽閘極兩 側之" '體基底位置形成淡摻雜源/汲極區（2 6 ),所植入 之離子較佳為鱗離子、钟離子或蝴離子，植入之能量的範 圍在20至50 KeV之間，植入劑量的範圍在5£12至5]£13 a toms/cm2 之間 〇 請參照第4圖，於閘極結構（23)之側壁形成閘極絕緣 間隔層（28):㈣絕緣間隔層（28)較佳是為一厚度約5〇〇 至10 0 0 A之氧化矽層，閘極絕緣間隔層可利用低壓化學氣 ^ /儿積或較佳為電漿促進化學氣相沉積於溫度3〇〇乞至8〇〇 C之間形成’之後’再以非等向性反應離子蝕刻使用CHF3 或cpv 〇2作為银刻劑來蝕刻出閘極絕緣間隔層（2 8)。 源/汲極區（30)是利用離子植入法於閘極絕緣間隔層 (28)兩侧之半導體基底位置形成，所植入之離子較佳為磷 離子或砷離子，更佳為磷離子，植入之能量的範圍在3〇至 60 KeV之間’植入劑量的範圍在1E15至1E16 at〇ms/cm2之 間。Page 10 1 69 56 9 V. Description of the invention (7) (Πι :, Shangyi cap layer (22), tungsten layer (18), diffusion barrier layer (16), and polycrystal II are defined by patterning to have- The second picture of the pole structure (23) between the sidewalls is preferably performed by using a conventional lithography and reactive ion etching process to hydrate a body such as a gas or a fluorinated gas such as carbon tetrafluoride as the etching. Then, use the reactive plasma etching to remove the first insulating layer adjacent to the odor structure using CHF3 or 0? 4 + 112 as an etchant. • Please also refer to Figure 3, using a lightly doped source / drain ion implantation (LuhUj Doped Drain implantatiOn), a lightly doped source / drain region (2 6) is formed on both sides of the polycrystalline silicon gate. The implanted ions are preferably scale ions, Bell ion or butterfly ion, the implanted energy range is between 20 and 50 KeV, and the implanted dose range is between 5 £ 12 and 5] £ 13 a toms / cm2. Please refer to Figure 4 for the gate A gate insulating spacer layer (28) is formed on the sidewall of the structure (23): the ㈣ insulating spacer layer (28) is preferably a silicon oxide layer having a thickness of about 500 to 100 A. The gate insulating spacer layer may be Use low-pressure chemical gas ^ /, or preferably plasma, to promote chemical vapor deposition to form 'after' at temperatures between 300 and 800 ° C and then use CHF3 or cpv with anisotropic reactive ion etching. 2 is used as a silver etchant to etch out the gate insulating spacer (28). The source / drain region (30) is formed on the semiconductor substrates on both sides of the gate insulating spacer (28) by ion implantation. The implanted ions are preferably phosphorus ions or arsenic ions, more preferably phosphorus ions. The implanted energy ranges from 30 to 60 KeV. The implanted dose ranges from 1E15 to 1E16 at 0 ms / cm2. .
IMH 469 56 9 五、發明說明（8) 第二實施例 請參照第2B圖’氮化鈦層（1 6B)可藉由另—方式形成 於退火複晶矽層（14A)之上而無須沉積鈦。如同第一實施 例，製程首先於一半導體基底（丨〇)之上形成一第一絕緣層 (12)，接著’於第一絕緣層（丨2)之上形成一複晶矽層 (14)，複晶矽層（14)是在氮氣氣氛中退火，溫度是設定在 800至950 °C之間’退火20至120分鐘，退火後複晶石夕層 (14)形成一退火複晶石夕層（14A)，以減少後續之形成擴散 障壁層（1 6)的剝落。 在第二實施例中’氮化鈦層（1 6B)是以濺鍍或化學氣 相沉積形成於退火複晶梦層（14A)之上，形成之厚度约2〇〇 至400A。依據本發明之第二實施例，障壁層（16)僅由氣化 鈦層（16B)所組成。 第二實施例之後續製程是同第一實施例，於障壁層 (16)之上形成一鎢層（18)，於鎢層（18)之上形成一上蓋層 (2 2 )，及形成一閘極結構- θ 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。譬如，本發 明實施例所舉例者為N —t；ype元件，然而熟習此技藝者， 可摻雜不同種類之離子而形成p_type元件。雖然本發明實 施=所舉例者為閘極結構，然其亦可為其他的導線結 如字元線。 、IMH 469 56 9 V. Description of the invention (8) Please refer to Figure 2B for the second embodiment. 'The titanium nitride layer (16B) can be formed on the annealed polycrystalline silicon layer (14A) by another method without deposition. titanium. As in the first embodiment, the process first forms a first insulating layer (12) on a semiconductor substrate (丨 0), and then 'forms a polycrystalline silicon layer (14) on the first insulating layer (丨 2). The polycrystalline silicon layer (14) is annealed in a nitrogen atmosphere, and the temperature is set between 800 and 950 ° C. Annealed for 20 to 120 minutes. The annealed polycrystalline silicon layer (14) forms an annealed polycrystalline silicon after annealing. Layer (14A) to reduce subsequent spalling of the diffusion barrier layer (16). In the second embodiment, the 'titanium nitride layer (16B) is formed on the annealed polycrystalline dream layer (14A) by sputtering or chemical vapor deposition to a thickness of about 200 to 400A. According to a second embodiment of the present invention, the barrier layer (16) is composed of only a vaporized titanium layer (16B). The subsequent process of the second embodiment is the same as the first embodiment. A tungsten layer (18) is formed on the barrier layer (16), a cap layer (2 2) is formed on the tungsten layer (18), and a Gate structure-θ Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. For example, the N-t; ype element is exemplified in the embodiment of the present invention. However, those skilled in the art can dope different types of ions to form a p_type element. Although the present invention is implemented as a gate structure as an example, it can also be other wire junctions such as word lines. ,
IIHI IIM 第12頁IIHI IIM Page 12
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