46 6 5 9 3 五、發明說明（l) 本發明係有關於一種半導體積體電路（integrated cifcui ts ; ICs)製程技術’特別是有關於一種自我對準金 属石夕化物（self-aligned metal silicide ’ 簡稱metal s a 1 i c i d e)的製造方法’能夠有效地降低阻值，並且可改 善不當的橋接（bridge)現象。 以下利用第1A〜第1C圖所示在金氧半電晶體（metal oxide semiconductor transistor ;i!OS transistor)形 成自我對準金屬矽化物的製程剖面圖，以說明習知技術。 首先’請參照第1A圖與第1B圖，第1A圖之符號10表示 梦基底’而石夕基底10表面形成有閘極（gate)i3與源極/汲 極（source/drain)12。另外，符號11表示閘極氧化層 (gate oxide) ’而符號14表示間隙壁（spacer)。符號15表 示形成於閘極13與源極/汲極12表面的原始氧化層（native oxide)。習知技術利用稀釋的（1:100)氫氟酸（HF)去除上 述原始氧化層1 5，以露出上述閘極1 3與源極/汲極1 2表 面’而形成第1B圖所示的剖面。以下反應式可代表上述反 rtfc ‘ 應·46 6 5 9 3 V. Description of the invention (l) The present invention relates to a semiconductor integrated circuit (integrated cifcui ts; ICs) process technology 'especially to a self-aligned metal silicide 'Abbreviation for manufacturing method of metal sa 1 pesticide' can effectively reduce the resistance value and improve the improper bridge phenomenon. In the following, cross-sectional views of a process for forming a self-aligned metal silicide in a metal oxide semiconductor transistor (i! OS transistor) shown in FIGS. 1A to 1C are used to illustrate the conventional technique. First, please refer to FIG. 1A and FIG. 1B. The symbol 10 in FIG. 1A indicates a dream substrate. The gate surface of the stone evening substrate 10 is formed with a gate i3 and a source / drain 12. In addition, reference numeral 11 indicates a gate oxide 'and reference numeral 14 indicates a spacer. Symbol 15 indicates a native oxide layer formed on the surfaces of the gate electrode 13 and the source / drain electrode 12. The conventional technique uses dilute (1: 100) hydrofluoric acid (HF) to remove the original oxide layer 15 to expose the surface of the gate 13 and source / drain 12 ′ to form the surface shown in FIG. 1B. section. The following reaction formula can represent the above reverse rtfc ‘should
Si02 + 6HF — H2 + SiF6 + 2H20 接著，請參照第1C圖，在上述露出的閘極13與源極/ 汲極12表面形成自我對準金屬（例如鈷）矽化物層16，以達 到降低阻值的目的。 然而，隨著電路積集度的增加，閘極與源極/汲極的 尺寸日益縮小，在形成自我對準金屬石夕化物之前，以氫氟 酸清除原始氧化層的方式，對於阻值的降低效果已漸漸無Si02 + 6HF — H2 + SiF6 + 2H20 Next, referring to Figure 1C, a self-aligned metal (eg, cobalt) silicide layer 16 is formed on the exposed gate 13 and source / drain 12 surfaces to reduce resistance. The purpose of the value. However, with the increase of the circuit accumulation, the size of the gate and source / drain is getting smaller and smaller. Before the formation of self-aligned metal fossil compounds, the original oxide layer is removed by hydrofluoric acid. The reduction effect has gradually disappeared
466693 五、發明說明（2) 法符合需求。 . 有鑑於此，本發明的目的在於提供一種自我對 =化：的製造方法’利用含氫氣體在高溫下去除原始氧化 層，再形成金屬矽化物，能夠進一步地降低閘極盥源極/ 汲極的阻值，而且可改善不當的橋接現象。’，、 電量（junction leakage)不會上昇。 芩接面漏 =述目的’本發明提供-種自我對準金屬石夕化物 ^製、方法’包括下列步驟：提供一矽基底，該矽基底表 極I : Ϊ :閘極與—源極"及極’並且該閘極與該源極/没 始氧化層；利用含氫⑷氧體去除上述原 η以露出該閘極與該極/汲極表® ;在該閘極與 该源極/汲極表面形成一自我對準金屬矽化物。 再者，上述自我對準金屬矽化物的製造 ϊϋ?摻有雜質之複晶錢成。該源極以極^以是 該矽基底表面的N型或P型離子摻雜區域構成。 並且，上述自我對準金屬矽化物 始氧化層可以在介糊侧。c的溫度下=去 而處理時間最好介於5秒〜1 20秒之間。 體俜準金屬石夕化物的製造方法，其中該含氫氣 合^ ^ 2)之混合氣體或是氫氣與氬氣（Ar)之混 成誃mif自我對準金屬矽化物的製造方法，其中形 於二会屬屉.、f矽化物的步驟最好更包括下列步驟··濺 x ,進行熱處理使該金屬層與該閘極及該源極/ 466693 五、發明說明（3) 汲極表面的矽反應而形成金屬矽化物；以 應的該金屬層。 古除未參予反 並且，上述自我對準金屬矽化物的製造方法， 金屬層係鈷金屬層、鈦金屬層、或鈕金屬層。 ^中該 為了讓本發明之上述㈣、特徵、和優點能 懂，下文特舉一較佳實施例，並配合所 1易 明如下： 幽v作咩細說 圖式之簡單說明： 第1A〜第1C圖係習知技術之自我對準金屬矽化 程剖面圖。 教 第2A〜第2C圖係根據本發明較佳實施例之自我對 屬石夕化物的製程剖面圖。 … 符號之說明 1 0、1 0 0〜單晶矽基底； 11、110〜閘極氧化層； 1 2、1 2 0〜源極/ ί及極； 13、 130~ 閑極； 14、 140〜間隙壁（spacer); 15、 150〜原始氧化層； 16、 160〜自我對準金屬矽化物。 實施例 以下利用第2A〜第2C圖所示在金氧半電晶體“的 transistor)形成自我對準金屬矽化物的製程剖面圖，以 說明本發明較佳實施例。466693 V. Description of Invention (2) The method meets the requirements. In view of this, the object of the present invention is to provide a manufacturing method of self-alignment: using hydrogen-containing gas to remove the original oxide layer at high temperature, and then forming a metal silicide, which can further reduce the gate electrode source / drain. Extreme resistance, and can improve improper bridging. ’, The electricity leakage will not rise.芩 Interface leakage = stated purpose 'The present invention provides a self-aligned metal lithium oxide method and method' including the following steps: Provide a silicon substrate, the silicon substrate epipolar I: Ϊ: gate and -source & quot And the pole 'and the gate and the source / non-starting oxide layer; removing the original n with a hydrogen-containing oxide to expose the gate and the pole / drain table®; at the gate and the source A self-aligned metal silicide is formed on the drain surface. Furthermore, the above-mentioned self-aligned metal silicide is fabricated by a compound crystal doped with impurities. The source electrode is composed of an N-type or P-type ion doped region that is a surface of the silicon substrate. In addition, the self-aligned metal silicide starting oxide layer may be on the paste side. At the temperature of c = to go, and the processing time is preferably between 5 seconds to 120 seconds. Manufacturing method of bulk metal quasi-metallic oxide, wherein the mixed gas containing hydrogen or ^ 2) or a mixture of hydrogen and argon (Ar), a mif self-aligned metal silicide manufacturing method, wherein The step of f silicide preferably includes the following steps: sputtering x, performing heat treatment to make the metal layer react with the gate and the source / 466693 V. Description of the invention (3) Silicon reaction on the surface of the drain electrode A metal silicide is formed; the corresponding metal layer is formed. In addition, the ancient method has not participated. In addition, in the above-mentioned self-aligned metal silicide manufacturing method, the metal layer is a cobalt metal layer, a titanium metal layer, or a button metal layer. ^ In order to make the above-mentioned features, characteristics, and advantages of the present invention understandable, a preferred embodiment is given below, and it is easy to understand as follows: v v 作 咩 Detailed description of the diagram: Section 1A ~ Figure 1C is a cross-sectional view of the self-aligned metal silicidation process of the conventional technology. Figures 2A to 2C are cross-sectional views of the process of self-parallel lithophyllite according to a preferred embodiment of the present invention. … Explanation of symbols 1 0, 1 0 0 ~ single crystal silicon substrate; 11, 110 ~ gate oxide layer; 1 2, 1 2 0 ~ source / til and electrode; 13, 130 ~ idle electrode; 14, 140 ~ Spacer (spacer); 15, 150 ~ original oxide layer; 16, 160 ~ self-aligned metal silicide. EXAMPLES The following is a cross-sectional view of a process for forming a self-aligned metal silicide in a "transistor" of a metal-oxide semiconductor transistor as shown in Figs. 2A to 2C to illustrate a preferred embodiment of the present invention.
第7頁 4 6 6 693 五、發明說明（4) 首先’請參照第2A圖與第2B圖，第2A圖之符號1〇〇表 示單晶矽基底，而矽基底表面形成有摻入離子的複晶矽構 成之閉極130、與p型或n型離子摻雜區域構成的源極/汲極 120。另外’符號110表示閘極氧化層，而符號14〇表示例 如二氧化矽或氮化矽材料構成的間隙壁（spacer)。符號 150表示形成於閘極130與源極/汲極12〇表面，而且由二氧 化石夕（Si02)構成的原始氧化層（natjve (^丨心）^為了在後 續步驟有效地形成能夠降低阻值的金屬矽化物（metal silicide) ’必須徹底地清除上述原始氧化層〗。因此， 本發明實施例在850 t的高溫環境下利用含氫氣體’例如 氫氣與氮氣之混合氣體或是氫氣與氬氣之混合氣體，以去 除上述二氧化矽構成的原始氧化層〗5 〇大約6 〇秒，以得到 如第2B圖所示露出閘極130與源極/汲極120之矽表面之剖 面圖。以下反應式可代表上述反應： 2H2+Si02 —2H2〇 + Si 接著，請參照第2C圖，在上述露出的閘極丨3〇與源極/ 汲極120表面形成自我對準金屬矽化物層16〇 ’以達到降低 阻值的目的。上述自我對準金屬矽化物層16〇的形成步驟_ 。為，全面性地濺鍍一例如鈷金屬層，然後，在8〇〇〜1〇〇〇 ec的溫度下施以第1次回火步驟（annealing) ’以促進鈷與 矽反應而形成CoS ι2 ,然後去除未參予反應的鈷金屬或其 他副反應物，再施以第2次回火步驟。本實施例是以鈷金 屬為例，然而本發明不限於此，任何具有降低阻值效果的 金屬，例如鈦金屬、钽金屬或鎢金屬等皆可取代鈷金屬。Page 7 4 6 6 693 V. Description of the invention (4) First, please refer to FIG. 2A and FIG. 2B. The symbol 100 in FIG. 2A indicates a single crystal silicon substrate, and the surface of the silicon substrate is doped with ions doped with ions. A closed electrode 130 composed of polycrystalline silicon and a source / drain 120 composed of a p-type or n-type ion doped region. In addition, the reference numeral 110 indicates a gate oxide layer, and the reference numeral 140 indicates a spacer made of a material such as silicon dioxide or silicon nitride. The symbol 150 indicates the original oxide layer (natjve (^ 丨 心)) formed on the surface of the gate electrode 130 and the source / drain electrode 12 and composed of SiO2 (Si02) ^ In order to effectively form the electrode in the subsequent steps, resistance can be reduced Value of metal silicide (metal silicide) must completely remove the above-mentioned original oxide layer. Therefore, the embodiment of the present invention uses a hydrogen-containing gas under a high temperature environment of 850 t, such as a mixed gas of hydrogen and nitrogen or hydrogen and argon Gas to remove the original oxide layer composed of the above-mentioned silicon dioxide, for about 50 to 60 seconds, to obtain a cross-sectional view of the silicon surface exposing the gate 130 and the source / drain 120 as shown in FIG. 2B. The following reaction formula can represent the above reaction: 2H2 + Si02 —2H2〇 + Si Next, referring to FIG. 2C, a self-aligned metal silicide layer 16 is formed on the exposed gate 丨 30 and the surface of the source / drain 120 above. 〇 'in order to achieve the purpose of reducing the resistance. The above-mentioned self-aligned metal silicide layer 160 formation step is to comprehensively sputtering a metal layer such as cobalt, and then, in the 800-1000ec At the temperature of 1 Tempering step (annealing) to promote the reaction between cobalt and silicon to form CoS2, and then remove the unreacted cobalt metal or other side-reactants, and then perform the second tempering step. This embodiment uses cobalt metal as an example. For example, the present invention is not limited to this. Any metal having a resistance reducing effect, such as titanium metal, tantalum metal, or tungsten metal, can replace cobalt metal.
466693 五、發明說明（5) 發明特徵與效果 本發明的特徵在於，進行自我對準金屬矽化物製程 (silicide process)之前’利用含氫氣體去除原始氧化層 以取代傳統的稀釋氫氟酸。 根據本發明的製造方法，能夠進一步地降低閘極與源 極/汲極的阻值，例如在2. 0 // m的N型複晶矽閘極之片電阻 (sheet resistance)由傳統的 13.9 〜14.4 ohm/sq 降低為 12.9〜13.6 ohm/sq，再者，在2.0//m的P型複晶矽閘極之 片電阻由傳統的13.914.4 ohm/sq降低為12.9〜13. 6 ohm/sq， 而且根據本發明的製造方法，可改善不當的橋接現 象。再者’接面漏電量（juncti〇I1 leakage)不會上昇。 —雖然本發明已以較佳實施例揭露如上，然其並非兩以 限定^發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍Θ，當可作更動與潤 因此本發 』 當視後附之巾請專利範圍所界定者為p $範圍466693 V. Description of the invention (5) Features and effects of the present invention The feature of the present invention is that prior to the self-aligned metal silicide process, a hydrogen-containing gas is used to remove the original oxide layer to replace the traditional dilute hydrofluoric acid. According to the manufacturing method of the present invention, the resistance values of the gate and the source / drain can be further reduced, for example, the sheet resistance of the N-type complex silicon gate at 2. 0 // m is 13.9 ～ 14.4 ohm / sq is reduced to 12.9 ~ 13.6 ohm / sq, in addition, the P-type polycrystalline silicon gate electrode resistance at 2.0 // m is reduced from the traditional 13.914.4 ohm / sq to 12.9 ~ 13. 6 ohm / sq, and according to the manufacturing method of the present invention, improper bridging can be improved. Furthermore, the junction leakage (juncti0I1 leakage) will not increase. -Although the present invention has been disclosed as above with the preferred embodiment, it is not limited to two inventions. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. When viewing the attached towel, please define the scope of the patent as p $