TW377481B - Wafer burn-in test circuit of a semiconductor memory device - Google Patents

Wafer burn-in test circuit of a semiconductor memory device

Info

Publication number
TW377481B
TW377481B TW086116329A TW86116329A TW377481B TW 377481 B TW377481 B TW 377481B TW 086116329 A TW086116329 A TW 086116329A TW 86116329 A TW86116329 A TW 86116329A TW 377481 B TW377481 B TW 377481B
Authority
TW
Taiwan
Prior art keywords
word line
signal
wafer burn
circuit
row address
Prior art date
Application number
TW086116329A
Other languages
English (en)
Inventor
Dong-Sik Jeong
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW377481B publication Critical patent/TW377481B/zh

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
TW086116329A 1996-11-06 1997-11-04 Wafer burn-in test circuit of a semiconductor memory device TW377481B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960052254A KR100220950B1 (ko) 1996-11-06 1996-11-06 웨이퍼 번인회로

Publications (1)

Publication Number Publication Date
TW377481B true TW377481B (en) 1999-12-21

Family

ID=19480927

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086116329A TW377481B (en) 1996-11-06 1997-11-04 Wafer burn-in test circuit of a semiconductor memory device

Country Status (4)

Country Link
US (1) US5936899A (zh)
KR (1) KR100220950B1 (zh)
GB (1) GB2319623B (zh)
TW (1) TW377481B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023434A (en) * 1998-09-02 2000-02-08 Micron Technology, Inc. Method and apparatus for multiple row activation in memory devices
US6327682B1 (en) * 1999-03-22 2001-12-04 Taiwan Semiconductor Manufacturing Company Wafer burn-in design for DRAM and FeRAM devices
KR100287189B1 (ko) * 1999-04-07 2001-04-16 윤종용 활성화된 다수개의 워드라인들이 순차적으로 디세이블되는 반도체 메모리장치
KR100827444B1 (ko) 2006-12-22 2008-05-06 삼성전자주식회사 반도체 메모리 장치 및 이의 번인 테스트 방법
KR100845810B1 (ko) * 2007-08-14 2008-07-14 주식회사 하이닉스반도체 웨이퍼 번인 테스트 회로
KR20160131792A (ko) * 2015-05-08 2016-11-16 에스케이하이닉스 주식회사 반도체 메모리 장치
KR102543184B1 (ko) * 2018-03-29 2023-06-14 삼성전자주식회사 테스트 소자 그룹 및 이를 포함하는 반도체 웨이퍼

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770620B2 (ja) * 1990-12-26 1995-07-31 株式会社東芝 半導体記憶装置
JP2829135B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
JP2829134B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
KR950014099B1 (ko) * 1992-06-12 1995-11-21 가부시기가이샤 도시바 반도체 기억장치
JP3015652B2 (ja) * 1994-03-03 2000-03-06 株式会社東芝 半導体メモリ装置
KR0119887B1 (ko) * 1994-06-08 1997-10-30 김광호 반도체 메모리장치의 웨이퍼 번-인 테스트 회로

Also Published As

Publication number Publication date
GB9723495D0 (en) 1998-01-07
GB2319623B (en) 2001-03-28
KR19980034258A (ko) 1998-08-05
US5936899A (en) 1999-08-10
KR100220950B1 (ko) 1999-09-15
GB2319623A (en) 1998-05-27

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees