TW371791B - A non-volatile semiconductor memory device having mono bit and multiple bit mode - Google Patents

A non-volatile semiconductor memory device having mono bit and multiple bit mode

Info

Publication number: TW371791B
Authority: TW; Taiwan
Prior art keywords: bit; mono; volatile semiconductor; memory device; mode
Prior art date: 1996-10-04

Application number

TW086114343A

Other languages

English (en)

Chinese (zh)

Inventor

Jong-Wook Park

Original Assignee

Samsung Electronics Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1996-10-04

Filing date

1997-10-02

Publication date

1999-10-11

1997-10-02 Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd

1999-10-11 Application granted granted Critical

1999-10-11 Publication of TW371791B publication Critical patent/TW371791B/zh

Links

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Read Only Memory (AREA)

TW086114343A 1996-10-04 1997-10-02 A non-volatile semiconductor memory device having mono bit and multiple bit mode TW371791B (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
KR1019960043936A KR100204803B1 (ko)	1996-10-04	1996-10-04	단일 비트셀 및 다중비트셀 동작의 동시적인 수행이 가능한 불휘발성 반도체 메모리 장치

Publications (1)

Publication Number	Publication Date
TW371791B true TW371791B (en)	1999-10-11

Family

ID=19476218

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
TW086114343A TW371791B (en)	1996-10-04	1997-10-02	A non-volatile semiconductor memory device having mono bit and multiple bit mode

Country Status (3)

Country	Link
JP (1)	JP3662725B2 (ja)
KR (1)	KR100204803B1 (ja)
TW (1)	TW371791B (ja)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
KR100301932B1 (ko) *	1999-04-27	2001-10-29	윤종용	불 휘발성 반도체 메모리 장치
KR20010004990A (ko)	1999-06-30	2001-01-15	김영환	플래쉬 이이피롬 셀 및 그 제조 방법
KR100447969B1 (ko) *	2001-09-13	2004-09-10	주식회사 하이닉스반도체	멀티레벨 및 싱글레벨 프로그램/리드 겸용 플래쉬 메모리장치
KR100512181B1 (ko)	2003-07-11	2005-09-05	삼성전자주식회사	멀티 레벨 셀을 갖는 플래시 메모리 장치와 그것의 독출방법 및 프로그램 방법
KR100567912B1 (ko) *	2004-05-28	2006-04-05	주식회사 하이닉스반도체	플래시 메모리 장치의 페이지 버퍼 및 이를 이용한 데이터프로그램 방법
KR100609568B1 (ko) *	2004-07-15	2006-08-08	에스티마이크로일렉트로닉스 엔.브이.	비휘발성 메모리 장치의 페이지 버퍼 및 이를 이용한프로그램 방법과 독출 방법
KR100642911B1 (ko) *	2004-11-30	2006-11-08	주식회사 하이닉스반도체	페이지 버퍼 및 이를 이용한 플래쉬 메모리 소자의 검증방법
KR100672122B1 (ko) *	2005-03-10	2007-01-19	주식회사 하이닉스반도체	소비 전력이 감소된 플래시 메모리 장치의 페이지 버퍼 회로
KR100680484B1 (ko) *	2005-03-30	2007-02-08	주식회사 하이닉스반도체	개선된 독출 동작 기능을 가지는 플래시 메모리 장치의페이지 버퍼 회로 및 그 독출 동작 제어 방법
KR100697285B1 (ko)	2005-05-11	2007-03-20	삼성전자주식회사	워드라인과 선택라인 사이에 보호라인을 가지는 낸드플래시 메모리 장치
KR100634457B1 (ko)	2005-07-04	2006-10-16	삼성전자주식회사	단일의 페이지 버퍼 구조로 멀티-비트 및 단일-비트프로그램 동작을 수행하는 플래시 메모리 장치
KR100721012B1 (ko)	2005-07-12	2007-05-22	삼성전자주식회사	낸드 플래시 메모리 장치 및 그것의 프로그램 방법
KR100666183B1 (ko) *	2006-02-01	2007-01-09	삼성전자주식회사	3-레벨 불휘발성 반도체 메모리 장치 및 이에 대한구동방법
KR100666186B1 (ko)	2006-02-17	2007-01-09	삼성전자주식회사	3-레벨 불휘발성 반도체 메모리 장치 및 이에 적용되는페이지 버퍼
JP2009146467A (ja) *	2007-12-11	2009-07-02	Toshiba Corp	半導体集積回路装置
KR100898664B1 (ko) *	2007-12-24	2009-05-22	주식회사 하이닉스반도체	페이지 버퍼 및 불휘발성 메모리 장치의 프로그램 방법
KR100923821B1 (ko) *	2007-12-24	2009-10-27	주식회사 하이닉스반도체	불휘발성 메모리 장치의 페이지 버퍼 및 그 프로그램 방법
CN102789807B (zh) *	2011-05-20	2015-01-28	旺宏电子股份有限公司	具有二极管在存储串列中的三维阵列存储器架构
KR102290448B1 (ko)	2014-09-04	2021-08-19	삼성전자주식회사	불휘발성 메모리 및 불휘발성 메모리의 동작 방법

1996
- 1996-10-04 KR KR1019960043936A patent/KR100204803B1/ko not_active IP Right Cessation
1997
- 1997-10-02 TW TW086114343A patent/TW371791B/zh active
- 1997-10-03 JP JP27095797A patent/JP3662725B2/ja not_active Expired - Fee Related

Also Published As

Publication number	Publication date
JPH10125083A (ja)	1998-05-15
JP3662725B2 (ja)	2005-06-22
KR19980025698A (ko)	1998-07-15
KR100204803B1 (ko)	1999-06-15

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