TW371791B - A non-volatile semiconductor memory device having mono bit and multiple bit mode - Google Patents

A non-volatile semiconductor memory device having mono bit and multiple bit mode

Info

Publication number
TW371791B
TW371791B TW086114343A TW86114343A TW371791B TW 371791 B TW371791 B TW 371791B TW 086114343 A TW086114343 A TW 086114343A TW 86114343 A TW86114343 A TW 86114343A TW 371791 B TW371791 B TW 371791B
Authority
TW
Taiwan
Prior art keywords
bit
mono
volatile semiconductor
memory device
mode
Prior art date
Application number
TW086114343A
Other languages
Chinese (zh)
Inventor
Jong-Wook Park
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW371791B publication Critical patent/TW371791B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a non-volatile semiconductor device having mono bit and multiple bit, including a plurality of latch sense amplifiers, coupled to these bit line and controlled a control signal for detecting the condition of memory cells of the non-volatile semiconductor device, a control means for isolation circuit for dominating an internal connection among these bit lines, the internal circuit is selectively activated by a mono bit mode or a multiple bit mode; a current route control means controlling the current route in the memory cells of the said memory device and under the mono bit mode and the multiple bit mode to complete reading programming, erasing and confirming operations. This memory device provides mono bit or multiple bit date with great flexibility in operation.
TW086114343A 1996-10-04 1997-10-02 A non-volatile semiconductor memory device having mono bit and multiple bit mode TW371791B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960043936A KR100204803B1 (en) 1996-10-04 1996-10-04 Nonvolatile semiconductor device capable of single bit cell and multi bit cell

Publications (1)

Publication Number Publication Date
TW371791B true TW371791B (en) 1999-10-11

Family

ID=19476218

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086114343A TW371791B (en) 1996-10-04 1997-10-02 A non-volatile semiconductor memory device having mono bit and multiple bit mode

Country Status (3)

Country Link
JP (1) JP3662725B2 (en)
KR (1) KR100204803B1 (en)
TW (1) TW371791B (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100301932B1 (en) * 1999-04-27 2001-10-29 윤종용 A non-volatile semiconductor memory device
KR20010004990A (en) 1999-06-30 2001-01-15 김영환 Flash EEPROM cell and method of manufacturing the same
KR100447969B1 (en) * 2001-09-13 2004-09-10 주식회사 하이닉스반도체 Flash memory apparatus for multilevel and singlelevel program/read
KR100512181B1 (en) 2003-07-11 2005-09-05 삼성전자주식회사 Flash memory device having multi-level cell and method for its reading operation and program operation
KR100567912B1 (en) * 2004-05-28 2006-04-05 주식회사 하이닉스반도체 Page buffer in a flash memory device and method of programing data using the same
KR100609568B1 (en) * 2004-07-15 2006-08-08 에스티마이크로일렉트로닉스 엔.브이. Page buffer of nonvolatile memory device and programming and reading method using the same
KR100642911B1 (en) * 2004-11-30 2006-11-08 주식회사 하이닉스반도체 Page buffer and verify method of flash memory device using thereof
KR100672122B1 (en) * 2005-03-10 2007-01-19 주식회사 하이닉스반도체 Page buffer circuit of flash memory device with reduced consumption power
KR100680484B1 (en) * 2005-03-30 2007-02-08 주식회사 하이닉스반도체 Page buffer circuit of flash memory device with improved read operation function and methods for controlling read operation of the same
KR100697285B1 (en) 2005-05-11 2007-03-20 삼성전자주식회사 Nand flash memory device having shield line between word line and selection line
KR100634457B1 (en) 2005-07-04 2006-10-16 삼성전자주식회사 Flash memory device capable of performing multi-bit and single-bit program operations with a single page buffer structure
KR100721012B1 (en) 2005-07-12 2007-05-22 삼성전자주식회사 Nand flash memory device and program method thereof
KR100666183B1 (en) * 2006-02-01 2007-01-09 삼성전자주식회사 Nonvolatile semiconductor memory device having three-level memory cells and operating method therefor
KR100666186B1 (en) 2006-02-17 2007-01-09 삼성전자주식회사 Nonvolatile semiconductor memory device having three-level memory cells and page buffer used therefor
JP2009146467A (en) * 2007-12-11 2009-07-02 Toshiba Corp Semiconductor integrated circuit device
KR100898664B1 (en) * 2007-12-24 2009-05-22 주식회사 하이닉스반도체 Page buffer and programming method of non volatile memory device
KR100923821B1 (en) * 2007-12-24 2009-10-27 주식회사 하이닉스반도체 Page buffer of non volatile memory device and programming method of non volatile memory device
CN102789807B (en) * 2011-05-20 2015-01-28 旺宏电子股份有限公司 Three-dimensional array memory architecture having diode in storage serial
KR102290448B1 (en) 2014-09-04 2021-08-19 삼성전자주식회사 Nonvolatile memory and operating method of nonvolatile memory

Also Published As

Publication number Publication date
JPH10125083A (en) 1998-05-15
JP3662725B2 (en) 2005-06-22
KR19980025698A (en) 1998-07-15
KR100204803B1 (en) 1999-06-15

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