TW351787B - Memory subsystem capable of high speed data transfer - Google Patents

Memory subsystem capable of high speed data transfer

Info

Publication number
TW351787B
TW351787B TW086116931A TW86116931A TW351787B TW 351787 B TW351787 B TW 351787B TW 086116931 A TW086116931 A TW 086116931A TW 86116931 A TW86116931 A TW 86116931A TW 351787 B TW351787 B TW 351787B
Authority
TW
Taiwan
Prior art keywords
data
clock
memory
circuit
signal circuit
Prior art date
Application number
TW086116931A
Other languages
English (en)
Inventor
Masao Nakano
Hiroyoshi Tomita
Mitsunori Sato
Toshihiro Takemae
Masao Taguchi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW351787B publication Critical patent/TW351787B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
TW086116931A 1997-07-04 1997-11-13 Memory subsystem capable of high speed data transfer TW351787B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17996997A JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム

Publications (1)

Publication Number Publication Date
TW351787B true TW351787B (en) 1999-02-01

Family

ID=16075154

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086116931A TW351787B (en) 1997-07-04 1997-11-13 Memory subsystem capable of high speed data transfer

Country Status (4)

Country Link
US (1) US6397312B1 (zh)
JP (1) JP3929116B2 (zh)
KR (1) KR100271724B1 (zh)
TW (1) TW351787B (zh)

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CN107977328A (zh) * 2017-12-20 2018-05-01 天津瑞发科半导体技术有限公司 一种onfi接口双时钟沿采样装置

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107977328A (zh) * 2017-12-20 2018-05-01 天津瑞发科半导体技术有限公司 一种onfi接口双时钟沿采样装置
CN107977328B (zh) * 2017-12-20 2019-12-10 天津瑞发科半导体技术有限公司 一种onfi接口双时钟沿采样装置

Also Published As

Publication number Publication date
KR100271724B1 (ko) 2000-11-15
JPH1125029A (ja) 1999-01-29
JP3929116B2 (ja) 2007-06-13
KR19990013250A (ko) 1999-02-25
US6397312B1 (en) 2002-05-28

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