TW305068B - The semiconductor device - Google Patents
The semiconductor device Download PDFInfo
- Publication number
- TW305068B TW305068B TW085101630A TW85101630A TW305068B TW 305068 B TW305068 B TW 305068B TW 085101630 A TW085101630 A TW 085101630A TW 85101630 A TW85101630 A TW 85101630A TW 305068 B TW305068 B TW 305068B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal wiring
- dummy electrode
- semiconductor
- insulating film
- wafer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 83
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 description 44
- 238000009792 diffusion process Methods 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 239000000463 material Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910008599 TiW Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910016570 AlCu Inorganic materials 0.000 description 2
- 229910017150 AlTi Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
305068 A7 B7 五、發明説明(丨) 經濟部中央標準局員工消費合作社印製 發明所屬之技術範圍 本發明係關於半導體裝置。更細言之,係關於可防止半導 體封裝之一種’即TCP(Tape Carrier Package,捲帶載體 封裝)中之内導線(inner lead)與半導髏晶片端部接觸之晶 片設計所形成之半導體裝置。 先前之技術 先前技術中,有一種半導體封裝爲TCP。如圖5所示,此 種半導體封裝中,在形成有各種元件及迴路之半導禮晶片 la之表面上形成有端點(pad,未圖示),該端點透過凸塊9 與外部連接用配線(内導線)11接合。 爲了形成上述封裝構造,首先將具有凸塊9的半導體晶片 la裝置於接合台16上。其次,使凸塊9與爲搭載捲帶載體15 之晶片而設之裝置孔(device hole)中延伸而出之内導線η 之位置對齊。其後,用加熱後之接合工具14在凸塊9上對内 導線11進行加熱及加整,使凸塊9及内導線π上之鍍層形成 共融合金而連接。通常凸塊9上係鍍金,而内導線n上係鍍 錫,因此係形成金與錫之共融合金而連接。 本發明欲解決之問題 一般而言,半導體之接點係形成於其周邊區域,但由於電 路布局上的限制,有時在接點與晶片端部之間,會被配置例 如電源線等金屬配線。此時,如圖6及圖7所示,金屬配線 17被配置於半導體基板1上之活性區域以外所形成之場氧化 膜2上’同時被配置於元件形成區域上之絕緣膜$積層處之 上方’而且内導線11會橫跨於金屬配線17之上方。又,半 -4- 本紙張尺度適用中國國家槺準(CNS ) A4规格(210 X297公釐) VI-------------- I 訂 ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(2 ) 導體晶片la的端部12是爲了從由複數個晶片所構成的晶圓 中切出各個晶片而形成的刻痕,故露出半導體基板1。 在這種半導體晶片la上接合内導線11之時,接合工具14 的熱會傳到内導線11,有時熱膨脹會使内導線落下。又, 由於接合工具之熱之作用,由凸塊9與内導線11所形成之共 融合金或内導線上產生金屬鍍層垂流,壓迫半導體晶片,且 如果接合工具14之位置偏離,則上述問題更爲顯著,有時 在形成於金屬配線17上之絕緣膜(鈍化膜,例如SiN、PSG 膜等)10上會產生裂縫。該上述情形下,會產生金屬配線17 與内導線11短路、水分等侵入裂缝使金屬配線17腐蝕、或 是内導線11與半導體晶片1之端部12短路等問題。 再者’爲了防止橫方向應力造成金屬配線之滑動,有人提 出以假電極(dummy electrode)等在半導禮晶片表面上形 成凸部,再於其間配置金屬配線之方法,但並沒有考慮到内 導線接合時之上述問題’致使内導線因熱而下沉,或與半導 想晶片端部短路,此時假電極並不會發揮任何效果。又,由 於假電極係與金屬配線平行配置,故若有複數個内電極與假 電極短路’則會有其他的信號通過假電極被傳送到接點,造 成錯誤動作。 解決問題的古法 本發明提供一種半導體裝置,其半導髏晶片至少包含半導 體基板、絕緣膜、場氧化膜及配置於表面上之接點,該半導 趙晶片隔著凸塊與内導線接合,其中: 金屬配線形成於一凹部中,該凹部位於上述半導體晶片中 ) ( 2J0X297^ ) I---7------f ,衣-- (請先閲讀背面之注意事項再填寫本頁) 訂〆 i 305068五、發明説明(3 ) 經濟部中央標準局員工消費合作社印製 之接點與晶片端部之間,且其形成於半導體晶片内之絕緣膜 及/或場氧化膜之一部分被除去,該金屬配線與接點之間以 及金屬配線與晶片之端部之間各與上述金屬配線有一定的間 隔,且在比上述金屬配線高之位置上形成分離於各個内導線 上之假電極,而内導線被配置於假電極之上3 本發明之實施態樣 本發明中之半導體晶片包括在具有場氧化膜之半導體基板 上配置電晶體、電容、電阻等種種元件或電路,用配線層等 連接之,再用NSG、PSG、BPSG等絕緣膜等保護者。又, 其中較佳者爲接點露出於配置有此等元件等之晶片表面上, 且在該接點上形成凸塊者。構成接點之材料並不特別受限, 可爲一般當做電極使用的Al、TiW、八11、1^、(:11等導電層 。又,凸塊所使用之材料可爲與接點相同之材料或是銲錫、 金等。這種半導體晶片的接點係透過凸塊與内導線接合,而 構成半導體裝置。 又,在本發明之半導體裝置中,電源配線等金屬配線配置 於上述半導體晶片上之接點與晶片端部之間。該金屬配線係 ①形成於一凹部内,該凹部位於半導體表面上,該半導體表 面爲未形成場氧化膜之區域,且其形成於半導體晶片内絕緣 膜之一部分被除去,或②形成於一凹部内,該凹部位於半導 體表面上,該半導體表面爲於一場氧化膜上再形成絕緣膜之 區域,且絕緣膜及/或場氧化膜之一部分被除去,或形成於 除去氧化膜之後在半導體基板表面上形成的凹部内,③形成 於蝕刻半導體基板表面之一部分所形成之凹部内,其位於凹 -6- 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐) ----------{衣-----r丨訂·------{ » _ (請先閲讀背面之注意事項再填寫本頁) Α7 Β7 經濟部中央標準局員工消費合作社印製 五、發明説明(4 ) 部内’且形成於接近半導嫌基板的正上方。金屬配線之材料 並不特別受限,可爲一般做爲導電材料使用的Al、AlSi、 AlCu、AlSi/TiW、AlTi、TiN等。其膜厚及寬度等因所製 得之半導體裝置之大小而異,例如膜厚爲5〇〇nm〜1200nm 、較佳爲700〜900nm,寬度較佳爲〇.2μιη〜20μπι。 再者’接點與金屬配線之間以及金屬配線與半導體晶片端 部之間,各形成1層或2層以上的假電極。此等假電極較佳 對應各内導線互相分離而形成(參考圖一),其只要位於與内 導線的交差部分附近且與金屬配線保持一定之間隔即可,其 形狀並不特別受限,較佳形成與金屬配線略呈平行之長方形 。假電極之材料可爲例如Al、AlSi、AlCu、AlSi/TiW、 AlTi、TiN、多矽、欢與共融點金屬之碎化物、該矽化物與 矽之多矽化物等,可形成膜厚200nm〜1200nm左右,寬度 〇.2μιη 〜ΙΟμιη 左右。 假電極係形成1層之時,該假電可形成於場氧化膜等之上 形形成於比上述金屬配線高之位置上,或是即使不形成於場 氧化膜上,假電極的上面也必須配置於較金屬配線的上面高 的位置。該假電極可例如在於半導體基板上形成電晶體之閘 極時,用相同的材料及相同的步驟,形成與閘極電氣分離的 形狀。又,亦可用與閘極以外的配線層 '接點等相同的材料 及相同的步驟形成。 又,在上述第1層假電極上,可再隔著絕緣膜形成第2層 假電極,而形成二層假電極。此時,第2層假電極可配置於 以上述金屬配線高之位置(即將第2層的假電極的上面配置於 本紙張尺度適用中國國家揉準(CNS )八4规格(210X297公釐) I---^-------f .衣-----Γ—訂、------f (諳先閲讀背面之注意事項再填寫本頁) ^05068 A7 B7五、發明説明(5 ) 經濟部中央標準局員工消費合作社印製 比金屬配線的上面高的位置)。絕緣膜可爲層間絕緣膜,用 於被覆形成於半導體基板上之元件,例如可用Si〇2、SiN、 BPSG、BSG等或其積層膜。形成於該層間絕緣膜上之假電 極可例如在形成上述元件間之金屬配線之時,用相同之材料 及相同之步驟,形成與此等金屬配線電氣分離之形狀。 如此,使假電極配置於比金屬配線高的位置後,即使在内 導線落下或是下沉之時,亦會與被電氣分離的假電極接觸, 因而可防止内導體直接與半導端部或金屬配線接觸。又,即 使内導線與假電極短路,由於假電極各自分離,故只會與短 路的内導線成等電位,並不會有其他影響。再者,藉著在第 1層假電極上再形成第2層假電極,可再加大第2層假極之表 面與金屬配線之表面之高低差,故可完全防止内導線與半導 體端部或金屬配線接觸。 又,内導線的下沉量可根據接合時之溫度、内導線材料之 線膨脹率等予先推測,必須形成大於沉降量之凹部,但可視 所欲形成之凹部之深度,形成1層或2層假電極,若是適當 地組合金屬配線下有或沒有氧化膜等條件。 又,金屬配線直接形成於半導體基板上時,若在金屬配線 上施加與半導體基板不同之電位,則擴散層較佳爲與半導基 板相異之導電型雜質擴散層而分離。若在金屬配線上施加與 半導體基板相同之電位,則亦可形成與基板爲同一導電型之 雜質擴散層。該擴散層可例如與半導體基板上所形成之電晶 體擴散層同時形成。此時之擴散層不論其爲P型或N型之雜 質,其濃度均較佳爲1015離子/cm3〜102Q離子/cm3左右。 -8- 本紙張尺度適用中國國家梯準(CNS ) A4规格(210 X 297公釐) ^^^^1 ·ϋ1 n^— n^i ^flu -*tm ^m— m ml J^i ! (請先閱讀背面之注意事項再填寫本頁) 五、發明説明(6 ) A7 B7 經濟部中央梯準局員工消費合作杜印製 又,以上雖以捲帶載體包裝(TCP)説明了本發明之半導體 裝置’但即使是導線接合(wire bonding)之半導嫌裝置, 亦實質上同樣地適用本發明。 以上茲以圖式説明本發明之半導體裝置之具體實例,但本 發明並不限定於此P 實施例1 在本發明之半導體裝置中,如圖1及2所示,於矽基板1上 形成厚度至少Ι.Ομπι左右之埸氧化膜2及擴散層3,其上再 形成厚度0.5μιη左右的第1假電極4及厚0.9μιη左右的絕緣 膜5。再者,第2假電極8隔著絕緣膜5再形成於第1假電極4 上。凹部6形成於第1假電極4(第2假電極8)間矽基板1之擴 散層3之正上方,金屬配線7形成於凹部6内。又,凸塊9隔 著接點13形成於矽基板1上,内導線11橫跨第2假電極8及 金屬配線7而接合於凸塊9上。又,在矽基板1與金屬配線7 之電位相同之時,擴散層3之導電型較佳爲與矽基板1相同 者,若電位不同,則擴散層3之導電型較佳爲與矽基板1相 異者。 在上述半導體裝置中,由於金屬配線7係形成於珍基板1 上,故其與場氧化膜2上之第2假電極8之間之高度差爲場氧 化膜2之膜厚之一半左右(例如〇.5μιη)、閘極4之膜厚 (0.5μιη)及絕緣膜5之膜厚(0.9μιη)之合計値(1·9μπι),遠 較金屬配線7之厚度大。因此,在接合之時,即使内導線i j 下沉而破壞絕緣膜10,仍會被場氧化膜2上之第2假電極8所 支持,因此可防止内導線11與金屬配線7及晶片端部〗2間之 -9- 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐) (請先閲讀背面之注意Ϋ項再填寫本頁) 訂- i A7 ___B7 五、發明説明(7 ) 電氣短路。 以下茲説明圖2所示之半導體裝置之製造方法。 首先,在矽基板1以LOCOS法形成厚Ι.Ομιη左右的場氧化 膜2。此時,未在形成金屬配線7之區域上形成場氧化膜2。 其次,在矽基板1之全面上隔著閘極絕緣膜堆積厚約 0.5 μιη之多矽層,形成所要形狀之圖樣之後,形成閘極電極 (未圖示),同時形成第1假電極4,配置於下一步驟中形成之 金屬配線7之兩側。 其次,爲了形成源極/汲極擴散層(未囷示),進行離予注 入。此時,同時在未形成場氧化膜2之區域上形成擴散層3 。在此等閘極、第1假電極4上形成層間絕緣膜5。在層間絕 緣膜5上形成接觸洞,同時在第1假電極4間形成擴散層3之 區域上之碎基板1上形成凹部6。 其次’在含有接觸洞及凹部6之珍基板上形成導電層,再 形成所要形狀之圖樣之後,形成接點13、金屬配線7及第2 假電極8。又,在接點13、金屬配線7及第2假電極8上,形 成保遵半導禮晶片表面之絕緣膜1〇。 經濟部中央標準局員工消費合作社印製 -----------^ .衣-- (請先閲讀背面之注意事項再填寫本頁) 訂- 其後,在絕緣膜10上開窗,使接點露出,以習知之方法 形成凸塊9以與半導||晶片之接勘接觸’使用接合工具等接 合凸塊9與内導線11等,而完成半導體裝置。 實施例2 其次,説明本發明之另一半導體裝置。如圈3所示,在秒 基板1上’形成厚度至少1〇μιη&右的場氧化膜2,其上再 形成厚〇,9μπι左右的絕緣膜5 ^除去該絕緣膜之一部分以形
經濟部中央標準局員工消費合作社印製 ^05068 A7 ______B7 五、發明説明(8 ) 成凹部6。凹部内形成金屬配線7,且在絕緣膜5上與金扁配 線7同時形成與金屬配線7略平行之厚〇.5μιη左右的假電極8 ,絕緣膜10則再形成於假電極8上。又,凸塊9隔著接點13 形成於矽基板1上,内導線11橫跨假電極8及金屬配線7而接 合於凸塊9上。 在上述半導體裝置中,由於金屬配線7係形成於場氧化膜 2上,故其與假電極8之間之高度差爲絕緣膜5之膜厚 (〇-9μιη),使金屬配線7的位置較假電極8爲低。因此,在接 合之時,即使内導線11下沉而破壞絕緣膜1 〇,仍會被絕緣 膜5上之假電極8所支持,因此可防止内導線11與金屬配線7 及晶片端部12間之電氣短路。 又,此時之半導體裝置實質上可用與上述相同之方法形成 〇 實施例3 其次,説明本發明之另一半導體裝置。 如圖1及圖4所示,在妙基板1上,形成至少厚1. 〇 μιη左右 的場氧化膜2及擴散層3,其上再形成厚〇.5μιη左右的第1假 電極4及厚0·9μιη左右的絕緣膜5。再者,第2假電極8隔著 絕緣膜5再形成於第1假電極4上。凹部6形成於第1假電極4( 第2假電極8)間碎基板1之擴散屠3之正上方,金屬配線7形 成於凹部6内。又,凸塊9隔著接點13形成於矽基板1上,内 導線11橫跨第2假電極8及金屬配線7而接合於凸塊9上。又 ,在碎基板1與金屬配線7之電位相同之時,擴散層3之導電 型較佳爲與矽基板1相同者,若電位不同,則擴散廣3之導 -11 - 本紙張尺度適用中國國家標率(CNS ) A4*L格(210X297公釐) ----------人.私-----"丨訂-------f (請先閱讀背面之注意事項再填寫本貰) 經濟部中央襟準局員工消費合作社印製 A7 ___B7 五、發明説明(9 ) 電型較佳爲與矽基板1相異者。 在上述之本發明之半導體裝置中,由於金屬配線7係形成 於矽基板1上,故其與場氧化膜2上之第2假電極8之間之高 度差爲場氧化膜2之膜厚之一半左右(例如〇.5μηι)、閘極4之 膜厚(0·5μπι)之合計値(Ι.Ομχη),遠較金屬配線7之厚度大 。因此,在接合之時,即使内導線11下沉而破壞絕緣膜1〇 ,仍會被場氧化膜2上之第2假電極8所支持,因此可防止内 導線1 1與金屬配線7及晶片端部12間之電氣短路。 以下茲説明囷4所示之半導體裝置之製造方法。 首先,在矽基板1以LOCOS法形成厚Ι.Ομιη左右的場氧化 膜2。此時,未在形成金屬配線7之區域上形成場氧化膜2。 其次,在矽基板1之全面上隔著閘極絕緣膜堆積厚約 0·5μιη之多矽層,形成所要形狀之圖樣之後,形成閘極電極 (未圖示),同時形成第1假電極4,配置於下一步驟中形成之 金屬配線7之兩側。 其次,爲了形成源極/汲極擴散層(未圖示),進行離子注 入。此時’同時在未形成場氧化膜2之區域上形成擴散層3 。在此等閘極、第1假電極4上形成層間絕緣膜5。在層間絕 緣膜5上形成接觸洞,同時在第i假電極4間形成擴散層3之 區域上形成凹部6。 其次’在含有接觸洞及凹部6之矽基板上形成導電層,再 形成所要形狀之圖樣之後,形成接點13、金屬配線7及第2 假電極8。又’在接點13、金屬配線7及第2假電極8上,形 成保護半導禮晶片表面之絕緣膜1〇。 ___- 12- 本紙張尺度適用中國國家棣準(CNS ) A4規格(210X297公羡) —---— nnn——^ ^-----r I ^ -* (请先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 B7 五、發明説明(10 ) 其後,在絕緣膜10上開窗,使接點露出,以習知之方法 形成凸塊9以與半導體晶片之接點接觸,使用接合工具等接 合凸塊9與内導線11等,而完成半導體装置。 發明之功效 本發明之半導體裝置係在金屬配線兩侧比金屬配線高之位 置上形成假電極,故即使是内導線落下或下沉時,假電極亦 可成爲金屬配線及/或半導體晶片之端部等之堤,可防止内 導線與金屬配線及/或半導體晶片之端部之短路或金屬配線 上之絕緣膜之裂縫發生。而且,即使在形成1層或2層假電 極之時,亦不必特別增加步驟,而可在形成其他配線層時同 時形成之。 又,假電極由於係電位獨立的配線,故即使假電極上的保 護膜被破壞而與内導線短路,亦只會與施加在接點上之電位 成爲等電位,不會造成不良。 再者,金屬配線形成於凹部内之半導體基板之正上方時, 可確實地防止與配置於金屬導線正上方之内導線短路。而且 ,在如此將金屬導線形成於凹部内之時,亦只要變更形成場 氧化膜時之光罩之形狀即可實現。 因此,本發明不但可輕易地設定條件,使内導線接合步骤 中之内導線與半導體晶片間沒有短路、接觸之危險,而且可 提高内導線接合步驟中良率與信賴度。 圖式之簡要説明 圖1爲顯示本發明之半導體晶片與内導線之連接狀態之示 意圖。 -13 - 本紙張尺度逋用中國國家樣準(CNS ) A4规格(210X297公釐) ^^^1 tn t^m —flu ϋ nn Aml·· ^11^1 一 V n^i . -J^i l (請先閱讀背面之注意事項再填寫本頁) 五、發明説明(n ) A7 B7 經濟部中央標準局員工消費合作社印袋 圖2爲圖1之A-A·線示意剖面囷(其半導體晶片具有2層假 電極構造時)。 圖3爲圖1之A-A’線示意剖面圖(其半導體晶片具有1層假 電極構造時)。 圖4爲圖1之A-A·線示意剖面圖(其半導體晶片具有另外2 層假電極構造時)。 圖5爲説明内導線接合步驟之圖。 圖6爲先前之半導體晶片與内導線之連接狀態之示意平面 围。 圖7爲圖6之B-B’線之示意平面囷。 符號之説明 1 矽基板(半導體基板) 1 a半導體晶片 2 場氧化膜 3 擴散層 4 第1假電極 5 絕緣膜 6 凹部 7 金屬配線 8 第2假電極 9 凸塊 10 絕緣膜 11内導線 12半導體晶片端部 本紙張尺纽·(210去t (請先閲讀背面之注意事項再填寫本頁) 訂· A7 B7 五、發明説明(12 ) 13 接點 14接合工具 15 捲帶載體 16接合台 I丨~Γ-----1」II (請先閱讀背面之注意事項再填寫本頁) 訂· 經濟部中央標準局員工消費合作社印製 -15- 本紙張尺度適用中國國家橾率(CNS ) A4規格(210X297公釐)
Claims (1)
- 申請專利範圍 2. A8 B8 C8 D8 一種半導趙裝置,其半導髏晶片至少包含半導體基板、 絕緣膜、場氧化膜及配置於表面上之接點,該半導體晶 片隔著凸塊與内導線接合,其中: 金屬配線形成於一凹部中,該凹部位於上述半導體晶片 中之接點與晶片端部之間,且其形成於半導體晶片内之 絕緣膜及/或場氧化膜之一部分被除去,該金屬配線與接 點之間以及金屬配線與晶片之端部之間各與上述金屬配 線有一定的間隔,且在比上述金屬配線高之位置上形成 分離於各個内導線上之假電極’而内導線被配置於假電 極之上。 根據申請專利範团第1項之半導體裝置,其中金屬配線係 形成於凹部内之半導體基板之正上方。 (請先閲讀背面之注意事項再填寫本頁) ,今 訂.·* 1 經濟部中央標準局員工消費合作社印製 -16 本紙張尺度適用中國國家梂率(CNS > A4规格(210X297公釐)
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JP01212196A JP3207347B2 (ja) | 1996-01-26 | 1996-01-26 | 半導体装置 |
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TW085101630A TW305068B (en) | 1996-01-26 | 1996-02-09 | The semiconductor device |
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US (1) | US5659202A (zh) |
JP (1) | JP3207347B2 (zh) |
KR (1) | KR100211604B1 (zh) |
CN (1) | CN1065663C (zh) |
TW (1) | TW305068B (zh) |
Cited By (1)
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TWI502666B (zh) * | 2010-12-01 | 2015-10-01 | Panasonic Corp | Electronic parts mounting body, electronic parts, substrate |
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TW388912B (en) * | 1996-04-22 | 2000-05-01 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
KR0183898B1 (ko) * | 1996-06-28 | 1999-04-15 | 김광호 | 반도체장치 및 이를 이용한 콘택홀 형성방법 |
KR100272166B1 (ko) * | 1998-06-30 | 2000-11-15 | 윤종용 | 소자분리영역에 형성된 더미 도전층을 갖춘반도체소자 및 그제조방법 |
DE19834234C2 (de) * | 1998-07-29 | 2000-11-30 | Siemens Ag | Integrierter Halbleiterchip mit Füllstrukturen |
US6146984A (en) * | 1999-10-08 | 2000-11-14 | Agilent Technologies Inc. | Method and structure for uniform height solder bumps on a semiconductor wafer |
US6096649A (en) * | 1999-10-25 | 2000-08-01 | Taiwan Semiconductor Manufacturing Company | Top metal and passivation procedures for copper damascene structures |
KR100408414B1 (ko) | 2001-06-20 | 2003-12-06 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
KR100390044B1 (ko) * | 2001-06-27 | 2003-07-04 | 주식회사 하이닉스반도체 | 패드 패턴 형성 방법 |
JP4944402B2 (ja) * | 2005-07-13 | 2012-05-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8476629B2 (en) * | 2011-09-27 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced wafer test line structure |
CN109935548B (zh) * | 2017-12-19 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
KR20200116577A (ko) * | 2019-04-01 | 2020-10-13 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
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JPS6079744A (ja) * | 1983-10-05 | 1985-05-07 | Nec Corp | 半導体装置 |
JPH01152644A (ja) * | 1987-12-09 | 1989-06-15 | Sharp Corp | 半導体装置 |
JPH01303742A (ja) * | 1988-05-31 | 1989-12-07 | Nec Corp | 半導体装置 |
JPH02260425A (ja) * | 1989-03-30 | 1990-10-23 | Toppan Printing Co Ltd | 電気素子及び電気素子の製造方法 |
JPH03169073A (ja) * | 1989-11-29 | 1991-07-22 | Hitachi Ltd | 半導体集積回路装置 |
JPH03190236A (ja) * | 1989-12-20 | 1991-08-20 | Mitsubishi Electric Corp | Mos集積回路 |
JPH03263325A (ja) * | 1990-03-13 | 1991-11-22 | Mitsubishi Electric Corp | 半導体装置 |
JPH03274764A (ja) * | 1990-03-26 | 1991-12-05 | Hitachi Ltd | 半導体集積回路装置 |
JP3186084B2 (ja) * | 1991-05-24 | 2001-07-11 | 日本電気株式会社 | 半導体メモリー装置 |
JPH0677223A (ja) * | 1991-09-30 | 1994-03-18 | Nec Corp | 樹脂封止型半導体装置 |
JP2762844B2 (ja) * | 1992-06-10 | 1998-06-04 | 日本電気株式会社 | 半導体装置 |
JPH0616329A (ja) * | 1992-07-01 | 1994-01-25 | Mita Ind Co Ltd | 画像形成装置の記録紙収納装置 |
JPH0697300A (ja) * | 1992-09-10 | 1994-04-08 | Mitsubishi Electric Corp | 半導体集積回路の配線間構造 |
-
1996
- 1996-01-26 JP JP01212196A patent/JP3207347B2/ja not_active Expired - Fee Related
- 1996-02-09 TW TW085101630A patent/TW305068B/zh not_active IP Right Cessation
- 1996-04-10 US US08/630,624 patent/US5659202A/en not_active Expired - Lifetime
- 1996-04-23 KR KR1019960012309A patent/KR100211604B1/ko not_active IP Right Cessation
- 1996-06-07 CN CN96107654A patent/CN1065663C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI502666B (zh) * | 2010-12-01 | 2015-10-01 | Panasonic Corp | Electronic parts mounting body, electronic parts, substrate |
Also Published As
Publication number | Publication date |
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US5659202A (en) | 1997-08-19 |
JPH09205114A (ja) | 1997-08-05 |
CN1065663C (zh) | 2001-05-09 |
JP3207347B2 (ja) | 2001-09-10 |
KR970060467A (ko) | 1997-08-12 |
CN1156335A (zh) | 1997-08-06 |
KR100211604B1 (ko) | 1999-08-02 |
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