TW202349520A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TW202349520A
TW202349520A TW112101310A TW112101310A TW202349520A TW 202349520 A TW202349520 A TW 202349520A TW 112101310 A TW112101310 A TW 112101310A TW 112101310 A TW112101310 A TW 112101310A TW 202349520 A TW202349520 A TW 202349520A
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Taiwan
Prior art keywords
conductive
pads
conductive pads
semiconductor device
layer
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TW112101310A
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English (en)
Inventor
陳俊仁
白偉均
何承蔚
邱勝煥
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台灣積體電路製造股份有限公司
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Publication of TW202349520A publication Critical patent/TW202349520A/zh

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Abstract

一種方法包括在複數個金屬墊之上形成第一聚合物層，且圖案化第一聚合物層以在第一聚合物層中形成複數個開口。複數個金屬墊通過複數個開口暴露。複數個導電通孔形成在複數個開口中。複數個導電墊形成在複數個導電通孔之上且接觸複數個導電通孔。複數個導電墊中的一導電墊從在導電墊正下方的一導電通孔橫向偏移且物理接觸導電墊。形成第二聚合物層以覆蓋複數個導電墊且物理接觸複數個導電墊。

Description

半導體裝置及其形成方法
本發明是關於一種半導體裝置及其形成方法，特別是關於一種形成導電通孔以及導電墊的方法。
在積體電路的形成中，積體電路裝置(例如，電晶體)形成在晶圓中的半導體基材的表面。然後在積體電路裝置之上形成互連結構。金屬墊形成在互連結構之上，且電性耦接到互連結構。在金屬墊之上形成鈍化層以及聚合物層，其中金屬墊通過鈍化層以及聚合物層中的開口暴露。電性連接器形成在晶圓的表面上。然後可將晶圓切割成裸晶。
根據一些實施例，一種方法包括在複數個金屬墊之上形成第一聚合物層；圖案化第一聚合物層以在第一聚合物層中形成複數個開口，其中複數個金屬墊通過複數個開口暴露；形成複數個導電通孔以及複數個導電墊，複數個導電通孔形成在複數個開口中，複數個導電墊形成在複數個導電通孔之上且接觸複數個導電通孔，其中複數個導電墊中的一導電墊從在導電墊正下方的一導電通孔橫向偏移且物理接觸導電墊；以及形成第二聚合物層，覆蓋複數個導電墊且物理接觸複數個導電墊。
根據一些實施例，一種裝置包括複數個金屬墊、第一聚合物層、複數個導電通孔、複數個導電墊以及第二聚合物層，第一聚合物層在複數個金屬墊之上，複數個導電通孔延伸至第一聚合物層中以接觸複數個金屬墊，複數個導電墊在複數個導電通孔之上且接觸複數個導電通孔，其中複數個導電墊從複數個導電通孔中的相應下方者橫向偏移，第二聚合物層在複數個導電墊之上且接觸複數個導電墊。
根據一些實施例，一種半導體裝置包括複數個金屬墊、第一介電層、複數個導電通孔、複數個導電墊以及電性連接器，第一介電層在複數個金屬墊之上，複數個導電通孔延伸至第一介電層中以接觸複數個金屬墊，複數個導電墊在複數個導電通孔之上且接觸複數個導電通孔，其中複數個導電墊形成陣列，且其中複數個導電墊的第一中心從複數個導電通孔中的相應下方者的第二中心橫向偏移，電性連接器在複數個導電墊之上且接觸複數個導電墊。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
此外，其與空間相關用詞。例如“在…下方”、“之下”、“較低的”、“上覆於”、“較高的” 及類似的用詞，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
根據一些實施例提供了一種封裝部件及其形成方法。封裝部件包括通孔以及在通孔之上且接觸通孔的導電墊。通孔以及導電墊可在聚合物層中。導電墊從通孔橫向偏移(未縱向對齊)，以使導電墊在通孔的一側比導電墊在通孔的相對側大。隨著導電墊從通孔橫向偏移，施加在導電墊以及通孔上以及附近的介電層上的應力可被釋放。此處討論的實施例旨在提供示例以實現或使用本揭露的標的，且本領域具有一般知識者將容易理解在保持在不同實施例的預期範圍內可進行的修改。綜觀各種視圖以及說明性實施例中，相同的參考符號用於表示相同的元件。儘管方法實施例可被描述為以特定順序執行，但是其他方法實施例可以任何邏輯順序執行。
第1圖到第10圖示出本揭露根據一些實施例的形成封裝體的中間階段的剖面圖。對應的製程也示意性地反映在如第16圖中所顯示的製程流程200中。可理解的是，雖然以裝置晶圓以及其中的裝置裸晶作為示例進行討論，但是本揭露的實施例也可應用於形成其他裝置(封裝部件)中的導電墊以及通孔，包括但不限於封裝基材、中介層、封裝體等等。
第1圖示出積體電路裝置20的剖面圖。根據一些實施例，裝置20是裝置晶圓或包括裝置晶圓，其包括主動裝置以及可能的被動裝置，其被表示為積體電路裝置26。裝置20可包括複數個晶片22在其中，其中一個晶片22被示出。根據本揭露的替代實施例，裝置20是中介層晶圓，其沒有主動裝置，且可包括也可不包括被動裝置。根據本揭露的又一替代實施例，裝置20是封裝基材條或包括封裝基材條，其包括無芯(core-less)封裝基材或其中具有芯的有芯(cored)封裝基材。在隨後的敘述中，裝置晶圓被用作裝置20的示例，且裝置20因此被稱為晶圓20。
根據一些實施例，晶圓20包括半導體基材24以及形成在半導體基材24的頂部表面的特徵。半導體基材24可由結晶矽、結晶鍺、矽鍺、碳摻雜矽或III-V族化合物半導體(例如，GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等等)形成，或包括結晶矽、結晶鍺、矽鍺、碳摻雜矽或III-V族化合物半導體。半導體基材24也可為體(bulk)半導體基材或絕緣體上半導體(Semiconductor-On-Insulator, SOI)基材。可在半導體基材24中形成淺溝槽隔離(Shallow Trench Isolation, STI)區域(未顯示)，以隔離半導體基材24中的主動區域。雖然未顯示，但是貫穿通孔可(或可不)形成以延伸至半導體基材24中，其中貫穿通孔用來電性互耦接半導體基材24相對側上的特徵。
根據一些實施例，晶圓20包括積體電路裝置26，形成在半導體基材24的頂部表面上。根據一些實施例，積體電路裝置26可包括電晶體、電阻器、電容器、二極體等等。積體電路裝置26的細節未在此說明。根據替代實施例，晶圓20用來形成中介層(其沒有主動裝置)，且基材24可為半導體基材或介電基材。
層間介電(Inter-Layer Dielectric, ILD)28形成在半導體基材24之上，且填充積體電路裝置26中電晶體(未顯示)的閘極堆疊之間的空間。根據一些實施例，層間介電28由磷矽玻璃(Phospho Silicate Glass, PSG)、硼矽玻璃(Boro Silicate Glass, BSG)、摻雜硼磷矽玻璃(Boron-doped Phospho Silicate Glass, BPSG)、摻雜氟矽玻璃(Fluorine-doped Silicate Glass, FSG)、氧化矽、氮氧化矽、氮化矽、低介電常數的介電材料等等形成。層間介電28可使用旋轉塗布、流動式化學氣相沉積(Flowable Chemical Vapor Deposition, FCVD)等等形成。根據一些實施例，層間介電28使用沉積方法(例如，電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition, PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition, LPCVD)等等)形成。
接觸栓塞30形成在層間介電28中，且用來將積體電路裝置26電性連接到上覆的(overlying)金屬線以及通孔。根據一些實施例，接觸栓塞30由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金以及/或其多層的導電材料形成，或包括選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金以及/或其多層的導電材料。形成接觸栓塞30可包括在層間介電28中形成接觸開口，將導電材料填充到接觸開口中，以及執行平坦化製程(例如，化學機械拋光(Chemical Mechanical Polish, CMP)製程或機械研磨製程)，以使接觸栓塞30的頂部表面與層間介電28的頂部表面齊平。
互連結構32形成在層間介電28以及接觸栓塞30之上。互連結構32包括金屬線34以及通孔36，其形成在介電層38(也稱為金屬間介電(Inter-metal Dielectrics, IMDs))中。以下將同一層(same level)的金屬線統稱為金屬層。根據一些實施例，互連結構32包括複數個金屬層，複數個金屬層包括通過通孔36互連的金屬線34。金屬線34以及通孔36可由銅或銅合金形成，且金屬線34以及通孔36也可由其他金屬形成。根據一些實施例，介電層38由低介電常數的介電材料形成。例如，低介電常數的介電材料的介電常數(k值)可低於大約3.0。介電層38可包括含碳的低介電常數的介電材料、氫矽酸鹽(Hydrogen SilsesQuioxane, HSQ)、甲基矽氧烷(MethylSilsesQuioxane, MSQ)等等。根據一些實施例，形成介電層38包括在介電層38中沉積含致孔劑(porogen-containing)的介電材料，然後執行固化製程以驅除致孔劑，因此剩餘的介電層38是多孔(porous)的。
形成金屬線34以及通孔36可包括單鑲嵌(single damascene)製程以及/或雙鑲嵌(dual damascene)製程。鑲嵌結構的每一個可包括擴散阻障層以及擴散阻障層之上的含銅金屬材料。擴散阻障層可包括鈦、氮化鈦、鉭、氮化鉭等等。
金屬線34包括頂部導電(金屬)特徵(表示為頂部導電特徵34A)，例如金屬線、金屬墊或通孔。頂部導電特徵34A在頂部介電層(表示為介電層38A)中，頂部介電層為介電層38的頂層。根據一些實施例，頂部介電層38A由非低介電常數的介電材料形成，其可包括氮化矽、未摻雜矽玻璃(Undoped Silicate Glass, USG)、氧化矽等等。根據替代實施例，介電層38A由相似於介電層38的下部的材料的低介電常數的介電材料形成。介電層38A也可具有多層結構，包括例如兩個未摻雜矽玻璃層以及中間的氮化矽層。頂部金屬特徵34A也可由銅或銅合金形成，且可具有雙鑲嵌結構或單鑲嵌結構。
鈍化層40(有時稱為鈍化-1(passivation-1或pass-1)) 形成在互連結構32之上。相應的製程被示為如第16圖中所顯示的製程流程200中的製程202。根據一些實施例，鈍化層40由具有大於或等於氧化矽的介電常數的介電常數的非低介電常數的介電材料形成。鈍化層40可由無機介電材料形成或包括無機介電材料，無機介電材料可選自但不限於氮化矽(SiN x)、氧化矽(SiO 2)、氮氧化矽(SiON x)、矽碳氧化物(SiOC x)、碳化矽(SiC)、未摻雜矽玻璃(USG)等等、其組合以及其多層。值“x”表示相對原子比(atomic ratio)。
在蝕刻製程中圖案化鈍化層40，且在鈍化層40中形成通孔42，以接觸頂部導電特徵(金屬線)34A。根據一些實施例，可通過單鑲嵌製程形成通孔42。
金屬墊44形成在通孔42之上，且接觸通孔42。相應的製程被示為如第16圖中所顯示的製程流程200中的製程204。金屬墊44可通過導電特徵(例如，金屬線34以及通孔36)電性耦接到積體電路裝置26。根據一些實施例，金屬墊44是鋁墊或鋁-銅墊，而也可使用其他金屬材料。根據一些實施例，金屬墊44具有大約大於百分之95的鋁百分比。
參照第2圖，鈍化層46形成在金屬墊44上。鈍化層46可為單層或複合層，且可由無孔材料形成。根據一些實施例，鈍化層46是複合層，包括氧化矽層以及在氧化矽層之上的氮化矽層。然後，通過蝕刻製程圖案化鈍化層46，以形成開口47，以使鈍化層46可覆蓋金屬墊44的邊緣部分，且金屬墊44的頂部表面的一些部分通過開口47暴露。
第3圖示出施加介電層48。根據一些實施例，介電層48包括聚合物，聚合物可包括聚醯亞胺(polyimide)、聚苯噁唑(polybenzoxazole, PBO)、苯並環丁烯(benzocyclobutene, BCB)等等。因此，介電層48可替代地稱為聚合物層48，而介電層48也可由其他介電材料(例如，無機介電材料)形成或包括其他介電材料。相應的製程被示為如第16圖中所顯示的製程流程200中的製程206。形成聚合物層48可包括旋轉塗布，然後固化聚合物層48。開口50形成在聚合物層48中。
第4圖到第6圖示出通孔以及上覆的導電墊的形成。參照第4圖，金屬晶種層54沉積在聚合物層之上。相應的製程被示為如第16圖中所顯示的製程流程200中的製程208。金屬晶種層54是導電晶種層，且可為金屬晶種層。根據一些實施例，金屬晶種層54是包括兩層或更多層的複合層。例如，金屬晶種層54可包括下層以及上層，其中下層可包括鈦層、氮化鈦層、鉭層、氮化鉭層等等。上層的材料可包括銅或銅合金。根據替代實施例，金屬晶種層54為單層，例如可為銅層。可使用物理氣相沉積(Physical Vapor Deposition, PVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(atomic layer deposition, ALD)等等形成金屬晶種層54，而也可使用其他適用的方法。金屬晶種層54是延伸至開口50中的共形層。
第4圖還示出圖案化的電鍍光罩56的形成。相應的製程被示為如第16圖中所顯示的製程流程200中的製程210。根據一些實施例，電鍍光罩56由光阻形成或包括光阻。電鍍光罩56被圖案化以形成開口58，金屬晶種層54的一些部分通過開口58暴露。電鍍光罩56的圖案化可包括曝光製程以及顯影製程。
第5圖示出將導電材料(特徵)60電鍍到開口58中以及金屬晶種層54上。相應的製程被示為如第16圖中所顯示的製程流程200中的製程212。根據一些實施例，形成導電特徵60包括電鍍製程，電鍍製程可包括電化學電鍍製程、無電極電鍍製程等等。電鍍可在電鍍化學溶液中執行。導電特徵60可包括銅、鋁、鎳、鎢等等、其合金以及/或其多層。根據一些實施例，導電特徵60包括銅且沒有鋁。
接著，去除如第5圖中所顯示的電鍍光罩56，且暴露在金屬晶種層54下方的部分。在隨後的製程中，執行蝕刻製程以去除金屬晶種層54的暴露部分。相應的製程被示為如第16圖中所顯示的製程流程200中的製程214。第6圖中顯示所得結構。在通篇描述中，導電材料60以及在對應的下方的部分的金屬晶種層54統稱為重分佈線(Redistribution Lines, RDLs)62。重分佈線62的每一個可包括通孔部分64(也稱為通孔或導電通孔)，延伸至聚合物層48中，且墊部分66(也稱為導電墊或金屬墊)在聚合物層48之上。根據一些實施例，導電墊66具有平坦頂部表面。根據替代實施例，由於電鍍製程，導電墊66的頂部表面在相應的導電通孔64的正上方具有凹陷，其中虛線67用來表示導電墊66的凹陷頂部表面。
通孔64具有中心64C，而導電墊66具有中心66C。根據一些實施例，一些或所有的導電墊66從在相應的下方的導電通孔64橫向偏移，這代表一些或所有的導電墊66的中心66C從在相應的下方的導電通孔64的中心64C橫向偏移。根據一些實施例，導電墊66包括第一部分66-A以及第二部分66-B，第一部分66-A以及第二部分66-B位於相應的導電通孔64的相對側(例如，所示的左側以及右側)。第一部分66-A以及第二部分66-B是橫向延伸超出在下方的導電通孔64的相應邊緣的部分。
第一部分66-A以及第二部分66-B分別具有橫向延伸距離L1以及橫向延伸距離L2。根據一些實施例，橫向延伸距離L1大於橫向延伸距離L2，其中橫向延伸距離L1可為導電墊66延伸超出在相應的下方的導電通孔64的最大距離，如可從第11A圖、第11B圖、第11C圖、第11D圖以及第13圖理解的。橫向延伸距離L2可為導電墊66延伸超出在相應的下方的導電通孔64的最小距離。橫向延伸距離L1以及橫向延伸距離L2均具有非零值。
應當理解的是，由於使用具有不同熱膨脹係數(Coefficients of Thermal Extension, CTEs)的不同材料，應力可能會在裝置裸晶22中產生。此外，材料中存在密度差異，也會造成應力。已經發現的是，應力導致所得裝置裸晶/晶圓以及封裝體的翹曲。翹曲可能進一步導致重分佈線62裂開，且可能導致不同層之間的脫層(delamination)，例如鈍化層46以及聚合物層48之間的脫層。藉由從相應的導電通孔64橫向偏移導電墊66，導電墊66具有臂(arms)，臂具有不同的長度L1以及長度L2，長度L1與長度L2不同於彼此。這有助於減輕應力。另一方面，已經發現的是，如果導電墊66從相應的導電通孔64對稱地延伸，則沒有降低應力的效果，且可能出現裂紋以及脫層。
為了將降低應力的效果最大化，橫向延伸距離L1以及橫向延伸距離L2具有非零值。否則，就沒有減輕應力的臂。根據一些實施例，橫向延伸距離L1以及橫向延伸距離L2均大約大於0.5微米，且可大約大於1微米、2微米或5微米。此外，橫向延伸距離L1與橫向延伸距離L2的差(L1-L2)足夠大，以使降低應力的效果足夠強。根據一些實施例，比例L1/L2大約大於1.2、大約大於1.5或大約大於2.0。比例L1/L2也可在大約1.2到大約10之間的範圍中。長度差(L1-L2)大約大於0.5微米，且可大約大於1微米、2微米或5微米，且可為在大約1微米到大約20微米之間的範圍中。
根據一些實施例，在裝置裸晶22中，所有導電墊66從在相應的下方的導電通孔64橫向偏移。根據替代實施例，一些導電墊66從在相應的下方的導電通孔64橫向偏移。然而，一些其他導電墊66沒有橫向偏移，而是與在相應的下方的導電通孔64縱向對齊，這代表導電墊66的中心66C與在相應的下方的導電通孔64的中心64C重疊(在相同位置)。例如，虛線68-1示意性地示出一個導電墊66的位置，此導電墊66沒有從在相應的下方的導電通孔64橫向偏移。
在同一裝置裸晶22中的導電墊66也可相對於在相應的下方的導電通孔64在相同或不同的方向偏移。例如，第6圖示出了一些導電墊66(如圖左側的導電墊66所示)向左橫向偏移，而一些其他導電墊66(如使用虛線68-2所示)可向右偏移。
第7圖示出介電層70的形成。根據一些實施例，介電層70是聚合物層，聚合物層由聚合物(其可為光敏的)(例如，聚醯亞胺、聚苯噁唑、苯並環丁烯、環氧樹脂等等)形成，或包括聚合物。相應的製程被示為如第16圖中所顯示的製程流程200中的製程216。根據一些實施例，介電層70的形成包括以可流動的形式塗布介電層，然後執行固化製程以硬化介電層。可(或可不)執行平坦化製程(例如，機械研磨製程)以使介電層70的頂部表面齊平。因此，介電層70也被稱為平坦化層。根據替代實施例，不執行平坦化製程，且介電層70的頂部表面可具有拓撲結構(topology)。
在隨後的製程中，介電層70被圖案化，例如，通過曝光製程然後是光顯影製程。因此在介電層70中形成開口72，且暴露導電墊66。
第8圖示出根據一些實施例的凸塊下金屬(Under-Bump Metallurgies, UBMs)的形成以及金屬柱以及焊料區域(如果形成的話)的形成。相應的製程被示為如第16圖中所顯示的製程流程200中的製程218。在示例形成製程中，金屬晶種層74被沉積為毯覆層(blanket layer)，其中第8圖示出毯覆晶種層74的一些剩餘部分。根據一些實施例，金屬晶種層74包括鈦層以及在鈦層之上的銅層。根據替代實施例，整個金屬晶種層74由例如銅或銅合金的同質材料(homogeneous material)形成，同質材料與介電層70以及導電墊66的頂部表面接觸。金屬晶種層74可通過物理氣相沉積、原子層沉積等等形成。
接下來，電鍍導電材料76。用於電鍍導電材料76的製程可包括形成圖案化電鍍光罩(例如，光阻(未顯示))，以及在圖案化電鍍光罩中的開口中電鍍導電材料76。導電材料76可包括銅、鎳、鈀、鋁、其合金以及/或其多層。根據一些實施例，焊料層也電鍍在導電材料76上以及圖案化電鍍光罩中的開口中。然後，去除圖案化電鍍光罩。
然後，蝕刻金屬晶種層74，且去除在電鍍光罩去除之後暴露的金屬晶種層74的部分，而留下金屬晶種層74在導電材料76的正下方的部分。所得結構如第8圖中所顯示。金屬晶種層的剩餘部分也稱為凸塊下金屬(UBMs)74。凸塊下金屬74以及導電材料76組合形成通孔80以及電性連接器82(其也稱為金屬凸塊)。根據還形成焊料層的一些實施例，可在蝕刻金屬晶種層之後執行回流製程(reflow process)，以使焊料層78具有圓的表面。
根據一些實施例，通孔80與在相應的下方的通孔64縱向對齊。根據替代實施例，通孔80與在相應的下方的通孔64未縱向對齊(橫向偏移)，且可縱向對齊或不對齊在相應的下方的導電墊66的中心。根據又一替代實施例，通孔80未縱向對齊在相應的下方的導電通孔64的中心64C以及在相應的下方的導電墊66的中心66C兩者。
根據替代實施例，不形成導電材料76。因此，如第8圖中所顯示的導電材料76使用虛線示出，以表示導電材料76可形成或不形成。在所得結構中，凸塊下金屬74被暴露。對應的凸塊下金屬74的形成製程可包括在鈦層之上沉積一個或複數個金屬層(例如，鈦層以及銅層)，然後通過微影製程來圖案化金屬層。焊料區域78可直接形成在凸塊下金屬74上，例如，藉由將焊球放置在凸塊下金屬74上，然後執行回流製程。
在隨後的製程中，晶圓20可被分割，例如，沿著劃片線(scribe lines)83切割，以形成單獨的裝置裸晶22。相應的製程被示為如第16圖中所顯示的製程流程200中的製程220。根據替代實施例，晶圓20的分割在稍後的階段執行。因此，第16圖中的製程220被顯示為虛線，以表示製程220可或可不在此時執行。裝置裸晶22也稱為裝置裸晶22或封裝部件22，因為裝置裸晶22可用來接合到其他封裝部件以形成封裝體。如前所述，裝置裸晶22可為裝置裸晶、中介層、封裝基材、封裝體等等。
參照第9圖，裝置裸晶22與封裝部件85接合。相應的製程被示為如第16圖中所顯示的製程流程200中的製程222。根據一些實施例，封裝部件85是裝置裸晶(包括在其中的主動裝置)、中介層、封裝基材、印刷電路板、封裝體等等，或包括裝置裸晶(包括在其中的主動裝置)、中介層、封裝基材、印刷電路板、封裝體等等。封裝部件85包括電性連接器84，電性連接器84可為金屬柱、接合墊等等。電性連接器84可形成在金屬墊87上，金屬墊87被介電層88部分地罩住。封裝部件85中的電性連接器84可通過焊料區域86接合到裝置裸晶22。焊料區域86可包括如第8圖中所顯示的焊料區域78，且封裝部件85中可包括也可不包括額外的焊料。
參照第10圖，底部填充劑90被分配在裝置裸晶22以及封裝部件85之間。相應的製程被示為如第16圖中所顯示的製程流程200中的製程224。封裝體92因此形成。根據一些實施例，如前所述，在將封裝部件85接合到裝置裸晶22之前切割晶圓20。根據替代實施例，晶圓20在接合封裝部件85之前沒有被分割。相反的是，如第9圖中所顯示的封裝部件85通過晶圓上晶片接合製程(chip-on-wafer bonding process)接合到未切割晶圓20中的裝置裸晶22。切割製程可在複數個封裝部件85接合到晶圓20中的複數個裝置裸晶22之後執行。晶圓20的切割可在底部填充劑90的分配之後執行。
第11A圖、第11B圖、第11C圖、第11D圖、第11E圖以及第11F圖示出根據各種實施例的一些示例性導電墊66以及通孔64的俯視圖。根據一些實施例，導電墊66的每一個以及其下方的通孔64可具有圓的俯視形狀、六邊形俯視形狀、八邊形俯視形狀、橢圓形俯視形狀、細長六邊形俯視形狀、細長八邊形俯視形狀等等的任意組合。例如，雖然附圖示出圓的俯視形狀的導電墊66可在圓的俯視形狀的導電通孔64正上方，但是圓的俯視形狀的導電墊66可替代地在六邊形俯視形狀的導電通孔64之上、八邊形俯視形狀的導電通孔64之上、橢圓形俯視形狀的導電通孔64之上、細長六邊形俯視形狀的導電通孔64之上、細長八邊形俯視形狀的導電通孔64之上，反之亦然。
第11A圖、第11B圖、第11C圖以及第11D圖示出橫向偏移的導電墊66以及通孔64的俯視圖。根據一些實施例，橫向延伸距離L1可為最大橫向延伸距離。另一方面，延伸距離L2可為也可不為最小延伸距離，取決於導電墊66以及通孔64的形狀以及相對位置。根據一些實施例，如第11B圖、第11C圖以及第11D圖中所顯示，導電通孔64的中心64C，除了如所示的偏移之外，還可在箭頭69的方向相對於導電墊66的中心66C進一步偏移。
在第11A圖中，導電墊66以及通孔64均具有圓的俯視形狀。示出了橫向延伸距離L1以及橫向延伸距離L2，其中橫向延伸距離L1以及橫向延伸距離L2可沿著穿過中心64C以及中心66C兩者的直線測量。橫向延伸距離L1以及橫向延伸距離L2可沿著圓的導電墊66的相同直徑測量。
在第11B圖中，導電墊66以及通孔64均具有六邊形俯視形狀。示出了一些示例性的橫向延伸距離L1以及橫向延伸距離L2，其中橫向延伸距離L1以及橫向延伸距離L2是沿著穿過中心64C以及中心66C兩者的直線94測量的。因此，橫向延伸距離L1以及橫向延伸距離L2可在穿過六邊形的角的方向測量。
第11C圖示出導電墊66具有橢圓形俯視形狀。根據一些實施例，通孔64不是細長的。根據替代實施例，通孔64也可為細長的。根據一些實施例，互連中心64C以及中心66C的線94將與橢圓的長軸重疊，且橫向延伸距離L1以及橫向延伸距離L2是沿著橢圓的長軸測量的。
第11D圖示出導電墊66以及導電通孔64均具有細長六邊形俯視形狀。根據替代實施例，導電墊66或導電通孔64兩者任一不是細長的。
第11E圖以及第11F圖示出一些未偏移的導電墊66以及通孔64的俯視圖，其中導電墊66的中心66C與相應的導電通孔64的中心64C重疊。相似地，導電墊66以及導電通孔64的其一或兩者可為細長的，例如，具有如第11C圖以及第11D圖中所顯示的細長形狀。
第12圖到第15圖示出根據一些實施例的一個裝置裸晶22以及一些示例性的導電墊66以及導電通孔64的俯視圖。雖然沒有標記所有導電墊66以及導電通孔64，但較大的實線形狀表示導電墊66的俯視圖，且較小的虛線形狀表示導電通孔64的俯視圖。此外，在第12圖到第15圖中，導電墊66以及導電通孔64作為示例顯示為使用圓的俯視形狀，而如第11A圖、第11B圖、第11C圖、第11D圖、第11E圖以及第11F圖中所顯示的所示以及所述的俯視形狀也可適用。
根據一些實施例，每一個導電墊66與相應的導電通孔64形成一對導電墊/通孔對66/64，且裸晶22包括複數個導電墊/通孔對66/64。複數個導電墊/通孔對66/64可形成陣列(array)。根據一些實施例，中心66C對齊以形成如第12圖到第15圖中所示的陣列，而中心64C可能與相應的中心66C不對齊，因此可形成陣列或可不形成任何陣列。根據替代實施例，中心64C對齊以形成陣列，而中心66C可與對應的中心64C不對齊，因此可形成陣列或可不形成任何陣列。
參照第12圖，根據一些實施例，綜觀整個裝置裸晶22，所有導電墊66從相應的導電通孔64橫向偏移。根據一些實施例，所有導電墊66沿著相同的方向偏移。例如，如圖所示，所有導電墊66可相對於在相應的下方的導電通孔64向左偏移。而且，綜觀所有導電墊66的橫向延伸距離L1以及橫向延伸距離L2可彼此相同。換言之，不同導電墊/通孔對66/64的偏移距離D1(在對應的中心64C以及中心66C之間的距離)可彼此相等。此設定可簡化設計。根據替代實施例，不同導電墊/通孔對66/64的偏移距離D1可彼此不同。
參照第13圖，根據一些實施例，綜觀整個裝置裸晶22，所有導電墊66從相應的導電通孔64橫向偏移。然而，導電墊66相對於在對應的下方的導電通孔64的偏移方向具有隨機的形態。舉例來說，一些橫向延伸距離L1以及橫向延伸距離L2被示出以表示對應的偏移方向。根據一些實施例，綜觀所有導電墊/通孔對66/64的橫向延伸距離L1以及橫向延伸距離L2彼此相同。根據替代實施例，不同導電墊/通孔對66/64的橫向延伸距離L1以及橫向延伸距離L2可彼此不同。
第14圖示出其中大部分或所有導電墊66在從裝置裸晶22的中心22C指向對應的導電墊66的方向偏移離開的實施例。根據一些實施例，偏移方向是沿著連接中心22C到相應的導電墊66的中心66C的直線。因此，偏移方向具有半徑的形態。當導電墊/通孔對66/64恰好在裝置裸晶22的中心22C時，相應的導電墊66可或可不從相應的導電通孔64偏移。
第15圖示出其中大部分或所有導電墊66都偏移的實施例。這些實施例相似於第14圖中所顯示的實施例，除了導電墊66是遠離中心22C而不是朝向中心22C偏移(相對於在相應的下方的導電通孔64)之外。當導電墊/通孔對66/64恰好在裝置裸晶22的中心22C時，相應的導電墊66可或可不從相應的導電通孔64偏移。
在第12圖到第15圖中所顯示的每一個實施例中，根據一些實施例，導電墊66的每一個的橫向延伸距離L1以及橫向延伸距離L2可相等於所有其他導電墊的相應的橫向延伸距離L1以及L2。根據替代實施例，比例L1/L2可有關於從相應的導電墊66到裝置裸晶22的中心22C的距離。遠離中心22C的導電墊66可具有比更靠近中心22C的導電墊66的更大的L1/L2比例。根據一些實施例，裝置裸晶中的任何導電墊66的L1/L2比例可與導電墊66到中心22C的距離成比例。例如，如第13圖中所顯示，假設從中心22C到導電墊66-1以及導電墊66-2的距離分別為距離S1以及距離S2，則導電墊66-1的比例(L1-1/L2-1)/S1被設計成相等於導電墊66-2的比例(L1-2/L2-2)/S2。由於遠離中心22C的導電墊66可能由於較高的翹曲而承受較高的應力，因此使遠離中心22C的導電墊66的L1/L2比例更大可提高吸收應力的能力。
本揭露的實施例具有一些有利的特徵。藉由相對於在相應的下方的導電通孔偏移導電墊，施加到導電墊以及導電通孔以及相鄰的介電層(例如，聚合物層)的應力被降低。減少了導電墊以及導電通孔的裂紋，且減少了相鄰的介電層之間的脫層。
根據一些實施例，一種方法包括在複數個金屬墊之上形成第一聚合物層；圖案化第一聚合物層以在第一聚合物層中形成複數個開口，其中複數個金屬墊通過複數個開口暴露；形成複數個導電通孔以及複數個導電墊，複數個導電通孔形成在複數個開口中，複數個導電墊形成在複數個導電通孔之上且接觸複數個導電通孔，其中複數個導電墊中的一導電墊從在導電墊正下方的一導電通孔橫向偏移且物理接觸導電墊；以及形成第二聚合物層，覆蓋複數個導電墊且物理接觸複數個導電墊。
在一實施例中，此方法更包括形成複數個凸塊下金屬，延伸至第二聚合物層中，其中複數個凸塊下金屬與複數個導電墊的頂部表面物理接觸。在一實施例中，形成複數個導電通孔以及複數個導電墊包括沉積金屬晶種層，延伸至複數個開口中；在金屬晶種層之上形成圖案化光罩層；以及電鍍導電材料至圖案化光罩層中以及金屬晶種層之上。在一實施例中，複數個導電墊以及複數個導電通孔的每一個具有一俯視形狀，此俯視形狀選自由圓形、六邊形以及八邊形組成的群組。
在一實施例中，此方法更包括執行分割製程以形成裸晶，其中第一聚合物層以及第二聚合物層被切割，其中裸晶中的所有複數個導電墊從複數個導電通孔中的相應下方者橫向偏移。在一實施例中，裸晶中的所有複數個導電墊相對於複數個導電通孔中的相應下方者都橫向偏移至相同方向。在一實施例中，裸晶中的所有複數個導電墊相對於複數個導電通孔中的相應下方者都橫向偏移相同距離。
在一實施例中，裸晶中的複數個導電墊相對於複數個導電通孔的相應下方者在隨機方向橫向偏移。在一實施例中，裸晶具有中心，且其中裸晶中的複數個導電墊的第一導電墊比複數個導電墊的第二導電墊更遠離中心，且其中複數個導電墊的第一導電墊比第二導電墊偏移更多。
根據一些實施例，一種裝置包括複數個金屬墊、第一聚合物層、複數個導電通孔、複數個導電墊以及第二聚合物層，第一聚合物層在複數個金屬墊之上，複數個導電通孔延伸至第一聚合物層中以接觸複數個金屬墊，複數個導電墊在複數個導電通孔之上且接觸複數個導電通孔，其中複數個導電墊從複數個導電通孔中的相應下方者橫向偏移，第二聚合物層在複數個導電墊之上且接觸複數個導電墊。在一實施例中，此裝置更包括無機鈍化層，在複數個金屬墊之上且在第一聚合物層下方。
在一實施例中，此裝置更包括複數個凸塊下金屬，延伸至第二聚合物層中，其中複數個凸塊下金屬與複數個導電墊的頂部表面物理接觸。在一實施例中，複數個導電通孔以及複數個導電墊在裸晶中，且其中裸晶中的所有複數個導電墊從複數個導電通孔中的對應者橫向偏移。在一實施例中，裸晶中的所有複數個導電墊相對於複數個導電通孔中的對應者都橫向偏移至相同方向。
在一實施例中，裸晶中的所有複數個導電墊相對於複數個導電通孔中的對應者都橫向偏移相同距離。在一實施例中，裸晶中的複數個導電墊相對於複數個導電通孔中的對應者在隨機方向橫向偏移。在一實施例中，裸晶具有中心，且其中裸晶中的複數個導電墊的第一導電墊比複數個導電墊的第二導電墊更遠離中心，且其中複數個導電墊的第一導電墊比第二導電墊偏移更多。
根據一些實施例，一種半導體裝置包括複數個金屬墊、第一介電層、複數個導電通孔、複數個導電墊以及電性連接器，第一介電層在複數個金屬墊之上，複數個導電通孔延伸至第一介電層中以接觸複數個金屬墊，複數個導電墊在複數個導電通孔之上且接觸複數個導電通孔，其中複數個導電墊形成陣列，且其中複數個導電墊的第一中心從複數個導電通孔中的相應下方者的第二中心橫向偏移，電性連接器在複數個導電墊之上且接觸複數個導電墊。在一實施例中，此裝置更包括焊接區域，在電性連接器之上，且接觸電性連接器。在一實施例中，所有第一中心在相同方向從第二中心橫向偏移相同距離。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
20:積體電路裝置/裝置/晶圓 22:晶圓/裝置裸晶/封裝部件/裸晶 22C,64C,66C:中心 24:半導體基材 26:積體電路裝置 28:層間介電 30:接觸栓塞 32:互連結構 34:金屬線 34A:頂部導電特徵/頂部金屬特徵 36,80:通孔 38:介電層 38A:介電層/頂部介電層 40,46:鈍化層 42:接觸通孔/通孔 44,87:金屬墊 47,50,58,72:開口 48:介電層/聚合物層 54:金屬晶種層 56:電鍍光罩 60:導電特徵 62:重分佈線 64:通孔部分/導電通孔/通孔 66,66-1,66-2:導電墊 66-A:第一部分 66-B:第二部分 67,68-1,68-2:虛線 69:箭頭 70,88:介電層 74:金屬晶種層/毯覆晶種層/凸塊下金屬 76:導電材料 78:焊料層/焊料區域 82:電性連接器 83:劃片線 84:電性連接器 85:封裝部件 86:焊接區域 90:底部填充劑 92:封裝體 94:直線/線 200:流程圖 202,204,206,208,210,212,214,216,218,220,222,224:製程 D1:偏移距離 L1,L2:橫向延伸距離/長度 S1,S2:距離
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。 第1圖到第10圖示出根據一些實施例的形成封裝體的中間階段的剖面圖。 第11A圖、第11B圖、第11C圖、第11D圖、第11E圖以及第11F圖示出根據一些實施例的一些通孔以及導電墊的俯視圖。 第12圖到第15圖示出根據一些實施例的封裝部件中的通孔以及導電墊的俯視圖。 第16圖示出根據一些實施例的用於形成封裝體的製程流程。
200:流程圖
202,204,206,208,210,212,214,216,218,220,222,224:製程

Claims (20)

  1. 一種形成半導體裝置的方法，包括： 在複數個金屬墊之上形成一第一聚合物層； 圖案化該第一聚合物層以在該第一聚合物層中形成複數個開口，其中該等金屬墊通過該等開口暴露； 形成複數個導電通孔以及複數個導電墊，該等導電通孔形成在該等開口中，該等導電墊形成在該等導電通孔之上且接觸該等導電通孔，其中該等導電墊中的一導電墊從在該導電墊正下方的一導電通孔橫向偏移且物理接觸該導電墊；以及 形成一第二聚合物層，覆蓋該等導電墊且物理接觸該等導電墊。
  2. 如請求項1之形成半導體裝置的方法，更包括形成複數個凸塊下金屬，延伸至該第二聚合物層中，其中該等凸塊下金屬與該等導電墊的數個頂部表面物理接觸。
  3. 如請求項1之形成半導體裝置的方法，其中形成該等導電通孔以及該等導電墊包括： 沉積一金屬晶種層，延伸至該等開口中； 在該金屬晶種層之上形成一圖案化光罩層；以及 電鍍一導電材料至該圖案化光罩層中以及該金屬晶種層之上。
  4. 如請求項1之形成半導體裝置的方法，其中該等導電墊以及該等導電通孔的每一個具有一俯視形狀，該俯視形狀選自由一圓形、一六邊形以及一八邊形組成的群組。
  5. 如請求項1之形成半導體裝置的方法，更包括執行一分割製程以形成一裸晶，其中該第一聚合物層以及該第二聚合物層被切割，其中該裸晶中的所有該等導電墊從該等導電通孔中的相應下方者橫向偏移。
  6. 如請求項5之形成半導體裝置的方法，其中該裸晶中的所有該等導電墊相對於該等導電通孔中的該等相應下方者都橫向偏移至一相同方向。
  7. 如請求項5之形成半導體裝置的方法，其中該裸晶中的所有該等導電墊相對於該等導電通孔中的該等相應下方者都橫向偏移一相同距離。
  8. 如請求項5之形成半導體裝置的方法，其中該裸晶中的該等導電墊相對於該等導電通孔中的該等相應下方者在數個隨機方向橫向偏移。
  9. 如請求項5之形成半導體裝置的方法，其中該裸晶具有一中心，且其中該裸晶中的該等導電墊的數個第一導電墊比該等導電墊的數個第二導電墊更遠離該中心，且其中該等導電墊的該等第一導電墊比該等第二導電墊偏移更多。
  10. 一種半導體裝置，包括： 複數個金屬墊； 一第一聚合物層，在該等金屬墊之上； 複數個導電通孔，延伸至該第一聚合物層中以接觸該等金屬墊； 複數個導電墊，在該等導電通孔之上且接觸該等導電通孔，其中該等導電墊從該等導電通孔中的相應下方者橫向偏移；以及 一第二聚合物層，在該等導電墊之上且接觸該等導電墊。
  11. 如請求項10之半導體裝置，更包括一無機鈍化層，在該等金屬墊之上且在該第一聚合物層下方。
  12. 如請求項10之半導體裝置，更包括複數個凸塊下金屬，延伸至該第二聚合物層中，其中該等凸塊下金屬與該等導電墊的數個頂部表面物理接觸。
  13. 如請求項10之半導體裝置，其中該等導電通孔以及該等導電墊在一裸晶中，且其中該裸晶中的所有該等導電墊從該等導電通孔中的對應者橫向偏移。
  14. 如請求項13之半導體裝置，其中該裸晶中的所有該等導電墊相對於該等導電通孔中的該等對應者都橫向偏移至一相同方向。
  15. 如請求項13之半導體裝置，其中該裸晶中的所有該等導電墊相對於該等導電通孔中的該等對應者都橫向偏移一相同距離。
  16. 如請求項13之半導體裝置，其中該裸晶中的該等導電墊相對於該等導電通孔中的該等對應者在數個隨機方向橫向偏移。
  17. 如請求項13之半導體裝置，其中該裸晶具有一中心，且其中該裸晶中的該等導電墊的數個第一導電墊比該等導電墊的數個第二導電墊更遠離該中心，且其中該等導電墊的該等第一導電墊比該等第二導電墊偏移更多。
  18. 一種半導體裝置，包括： 複數個金屬墊； 一第一介電層，在該等金屬墊之上； 複數個導電通孔，延伸至該第一介電層中以接觸該等金屬墊； 複數個導電墊，在該等導電通孔之上且接觸該等導電通孔，其中該等導電墊形成一陣列，且其中該等導電墊的數個第一中心從該等導電通孔中的相應下方者的數個第二中心橫向偏移；以及 數個電性連接器，在該等導電墊之上且接觸該等導電墊。
  19. 如請求項18之半導體裝置，更包括數個焊接區域，在該等電性連接器之上，且接觸該等電性連接器。
  20. 如請求項18之半導體裝置，其中所有該等第一中心在一相同方向從該等第二中心橫向偏移一相同距離。
TW112101310A 2022-02-25 2023-01-12 半導體裝置及其形成方法 TW202349520A (zh)

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