TW202338764A - Narrow bezel display module and data output device - Google Patents
Narrow bezel display module and data output device Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
Description
本發明是關於窄邊框顯示模組以及用於其的資料輸出裝置。若具體說明，則本發明是關於用於實現顯示面板的窄邊框的COF（Chip On Film：薄膜覆晶）配線技術。The present invention relates to a narrow frame display module and a data output device used therefor. Specifically, the present invention relates to COF (Chip On Film) wiring technology for realizing a narrow frame of a display panel.
筆記型電腦或平板電腦等行動裝置市場中，一直在要求消耗電力降低及成本降低。另一方面，隨著面板解析度的提升或顯示畫質的提升，資料處理量及動作頻率有増無減，而相反地要求降低消耗電力及降低成本是一大課題。筆記型電腦或平板電腦中，對顯示面板輸入繪圖資料的訊號的電路是由：負責繪圖資料本身的運算或各種運算處理或圖形處理的CPU（Central Processing Unit，中央處理單元）或GPU（Graphics Processing Unit，圖形處理單元）等處理器；以傳送自此處理器的繪圖資料作為輸入，執行顯示面板的時序控制或圖像處理的時序控制器（Timing Controller，TCON）；以及以來自時序控制器的繪圖資料作為輸入，並配合顯示面板的型式而類比輸出繪圖資料的源極驅動器（Source Driver：SD）等驅動晶片，所構成。The market for mobile devices such as notebook computers and tablet computers has been demanding reductions in power consumption and costs. On the other hand, as panel resolution or display quality improves, the amount of data processed and the frequency of operations continue to increase. On the contrary, reducing power consumption and cost are a major issue. In a laptop or tablet computer, the circuit that inputs graphics data signals to the display panel is composed of: a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) that is responsible for the calculation of the graphics data itself or various calculation processing or graphics processing. Unit, graphics processing unit) and other processors; a timing controller (Timing Controller, TCON) that uses the graphics data transmitted from this processor as input to perform timing control of the display panel or image processing; and a Timing Controller (TCON) from the timing controller. It takes drawing data as input, and is composed of a source driver (SD) and other driver chips that output the drawing data in accordance with the type of the display panel.
筆記型電腦或平板電腦等行動裝置中，時序控制器和源極驅動器大多是呈分離的情況。例如，圖1所示的FHD（Full High Definition，高畫質：1920×1080像素）顯示面板的情況中，大多需要1個時序控制器1及4個源極驅動器。此外，4K2K面板（解析度接近4000×2000像素的面板）的情況中，需要1個時序控制器1及8個源極驅動器的情況很多。再者，如圖1所示，將時序控制器與源極驅動器連接的FPC（Flexible Printed Cable，撓性印刷電纜）需要配合使用數個源極驅動器，而隨著面板解析度的增高，組件數亦増加，因而構成成本上升的主因。而且，時序控制器和源極驅動器間雖有設置介面的必要，卻因此介面而導致電力消耗。由於這種背景因素，使圖1所示的電路構成處在難以降低成本及消耗電力的狀況。In mobile devices such as notebook computers or tablet computers, the timing controller and the source driver are mostly separated. For example, in the case of the FHD (Full High Definition, high-definition: 1920×1080 pixels) display panel shown in Figure 1, one timing controller 1 and four source drivers are often required. In addition, in the case of 4K2K panels (panels with a resolution close to 4000×2000 pixels), one timing controller 1 and eight source drivers are often required. Furthermore, as shown in Figure 1, the FPC (Flexible Printed Cable) that connects the timing controller to the source driver requires the use of several source drivers. As the panel resolution increases, the number of components increases. also increased, thus constituting the main reason for the increase in costs. Moreover, although it is necessary to provide an interface between the timing controller and the source driver, power consumption is caused by the interface. Due to this background factor, the circuit configuration shown in Figure 1 is in a situation where it is difficult to reduce costs and consume power.
因此，為了減少組件數及消耗電力，如圖2及圖3所示的時序控制器及源極驅動器形成1個晶片的所謂系統驅動器（TCON＋SD）也可加以探究。圖2是表示設有2個系統驅動器的構成，圖3則顯示系統驅動器集成為1個的構成。透過系統驅動器化，即可使組件數減少及成本降低。更進一步，由於時序控制器與源極驅動器之間不存在介面，所以消耗電力也可降低。特別是，從組件數及消耗電力降低的觀點來看，如圖3所示，可謂系統驅動器以只有一個為較佳。但，系統驅動器則和以前的源極驅動器一樣安裝在液晶面板的玻璃上。繪圖資料則從處理器（CPU／GPU）直接輸入系統驅動器，或者透過eDP介面或mipi介面輸入系統驅動器。Therefore, in order to reduce the number of components and power consumption, the so-called system driver (TCON+SD) in which the timing controller and source driver as shown in Figures 2 and 3 form one chip can also be explored. Figure 2 shows a configuration with two system drivers, and Figure 3 shows a configuration with one system driver integrated. Through system driverization, the number of components can be reduced and the cost can be reduced. Furthermore, since there is no interface between the timing controller and the source driver, power consumption can also be reduced. In particular, from the viewpoint of reducing the number of components and power consumption, as shown in Figure 3, it can be said that it is better to have only one system driver. However, the system driver is mounted on the glass of the LCD panel like the previous source driver. The graphics data is directly input to the system driver from the processor (CPU/GPU), or input to the system driver through the eDP interface or mipi interface.
此處，液晶面板是以源極線與閘極線所構成。FHD面板的情況中，源極線需要1920×3（RGB）條線，閘極線則需要1080條線。源極線為將繪圖資料從源極驅動器類比輸出的線（資料線），並隔開預定間隔地配線成互相平行。閘極線則是按逐條閘極線一邊作時間性移動一邊驅動源極線的繪圖資料的控制線，其是朝和源極線正交與源極線正交的方向隔開預定間隔配線成互相平行。閘極線與源極線的各交叉點則設有顯示像素（pixel）。此外，在目前階段，源極驅動器或系統驅動器是以實裝在液晶玻璃上之方式，亦即所謂COG（Chip On the Glass，玻璃覆晶）方式為主流。Here, the liquid crystal panel is composed of source lines and gate lines. In the case of an FHD panel, the source line requires 1920×3 (RGB) lines, and the gate line requires 1080 lines. The source lines are lines (data lines) for analog outputting graphics data from the source driver, and are wired parallel to each other at predetermined intervals. The gate line is a control line of the drawing data that drives the source line while moving temporally one by one. It is wired at predetermined intervals in a direction orthogonal to the source line and orthogonal to the source line. become parallel to each other. Display pixels are provided at each intersection of the gate line and the source line. In addition, at the current stage, the source driver or system driver is installed on the liquid crystal glass, which is the so-called COG (Chip On the Glass) method.
液晶面板（顯示面板）源極線的模型揭示於圖4。液晶面板是分為屬於源極驅動器實裝區域的扇出區域（Fan out Area），及液晶像素作矩陣排列的有效區域（Active Area）。從此有效區域至包含扇出區域的玻璃模組邊緣部分是稱為液晶面板的邊框區域，此邊框區域較狹窄者即被認為商品價值較高。A model of the source line of a liquid crystal panel (display panel) is shown in Figure 4. The LCD panel is divided into a fan-out area (Fan out Area), which is the source driver installation area, and an active area (Active Area) where liquid crystal pixels are arranged in a matrix. The portion from this effective area to the edge of the glass module including the fan-out area is called the frame area of the LCD panel. The narrower frame area is considered to have higher product value.
如圖4所示，設有4個源極驅動器的情況中，1個源極驅動器進行驅動所需的COG上源極線配線數只要少數即可。例如，FHD面板的情況中，源極線有1920×3（RGB）＝5860條，而源極驅動器設有4個的情況中，每1個源極驅動器就要驅動1440條源極線。例如，專利文獻1中，即揭示了設有4個源極驅動器的構成。另一方面，如圖2、圖3及圖5所示，時序控制器（TCON）及源極驅動器（SD）加以整合的情況，或者源極驅動器進行集成化而組件數為1個或2個時，1個源極驅動器需要驅動的COG上源極線配線數就增多，而產生邊框區域的高度變大的問題。As shown in Figure 4, when four source drivers are provided, only a small number of source line wirings on the COG are required to drive one source driver. For example, in the case of an FHD panel, there are 1920 × 3 (RGB) = 5860 source lines, and in the case of four source drivers, each source driver drives 1440 source lines. For example, Patent Document 1 discloses a configuration in which four source drivers are provided. On the other hand, as shown in Figure 2, Figure 3 and Figure 5, the timing controller (TCON) and the source driver (SD) are integrated, or the source driver is integrated and the number of components is 1 or 2 , the number of source line wirings on the COG that needs to be driven by one source driver increases, causing a problem that the height of the frame area becomes larger.
此處，參照圖6針對顯示面板（液晶面板）邊框區域的構成加以說明。邊框區域的中心具有時序控制器與源極驅動器已施以整合的驅動晶片，源極線即從此驅動晶片上邊朝向有效區域進行配線。而且，源極線的配線一般是使全部的線以一定角度θ從最左端或者最右端的線向面板的中心線實施配線。從此驅動晶片與源極線的連接部至有效區域之間的區域，在本案說明書中是定義為「扇出區域」，圖中，此扇出區域的高度是以H 1來表示。再者，邊框區域中存在有位於較此扇出區域更遠離有效區域的區域，在本案說明書中，此區域是定義為「扇入區域」。此扇入區域中，從晶片下邊向左右延伸的閘極訊號驅動線是朝面板的左右方向實施配線，邊框區域的左右部分則配置有測試墊。此外，扇入區域中配置有源極線的測試線或其測試墊，甚至進一步配置有閘極驅動控制訊號線或其測試墊等。此扇入區域的高度在圖中是以H 2來表示。上述H 1＋H 2的值即為邊框區域整體的高度。因此，本申請的申請人提出了如下技術：在顯示面板的邊框區域中，特別是通過對源極線等訊號線的配線進行研究，來削減H 1所示的扇出區域的高度（專利文獻2）。 [習知技術文獻] [專利文獻] Here, the structure of the frame region of the display panel (liquid crystal panel) will be described with reference to FIG. 6 . In the center of the frame area, there is a driver chip with integrated timing controller and source driver. The source lines are routed from the top of the driver chip toward the active area. Furthermore, the wiring of the source lines is generally such that all the lines are laid out at a certain angle θ from the leftmost or rightmost line to the center line of the panel. The area from the connection between the driver chip and the source line to the effective area is defined as the "fan-out area" in the specification of this case. In the figure, the height of this fan-out area is represented by H1 . Furthermore, there is an area in the frame area that is further away from the effective area than the fan-out area. In the specification of this case, this area is defined as the "fan-in area". In this fan-in area, the gate signal drive lines extending from the bottom of the chip to the left and right are wired in the left and right directions of the panel, and test pads are arranged on the left and right parts of the frame area. In addition, the fan-in area is equipped with test lines or test pads for the source lines, and is even further equipped with gate drive control signal lines or test pads thereof. The height of this fan-in area is represented by H 2 in the figure. The above value of H 1 + H 2 is the overall height of the frame area. Therefore, the applicant of the present application has proposed the following technology: in the frame area of the display panel, especially by studying the wiring of signal lines such as source lines, to reduce the height of the fan-out area indicated by H1 (Patent Document 2). [Known technical documents] [Patent documents]
[專利文獻1]日本特開2005-031332號公報 [專利文獻2]日本特開2018-072783號公報 [Patent Document 1] Japanese Patent Application Publication No. 2005-031332 [Patent Document 2] Japanese Patent Application Publication No. 2018-072783
[發明所欲解決的課題] 如前所述，如圖2、圖3、及圖5所示，時序控制器（TCON）與源極驅動器（SD）施以整合時，或者源極驅動器進行集成化而組件數為1個或2個時，1個源極驅動器進行驅動所需的COG上源極線配線數會增多，有邊框區域高度變大的問題。特別是，此種情況中，邊框區域之中以H 1表示的扇出區域的高度較難以刪減。 [Problems to be solved by the invention] As mentioned above, as shown in Figures 2, 3, and 5, when the timing controller (TCON) and the source driver (SD) are integrated, or the source driver is integrated If the number of components is reduced to 1 or 2, the number of source line wirings on the COG required to drive one source driver will increase, and the height of the frame area will become larger. In particular, in this case, the height of the fan-out area represented by H 1 in the border area is more difficult to delete.
此處，參照圖7，舉傳統液晶面板的配線構造為例來說明求取邊框區域高度H 1的方法。首先，假設有效區域源極線的配線節距為P pix、扇出區域源極線的配線節距為P w，驅動晶片上源極線的連接部（輸出墊）節距為P bp，從驅動晶片最邊端的連接部至顯示面板最邊端的源極線為止的距離為Dx。此處，由於P pix＞P bp，連接驅動晶片與有效區域的源極線的一部分必須以一定角度使其傾斜。位於扇出區域最邊端的源極線配線與、有效區域中和源極線延伸方向正交的正交方向的方向軸的角度θ，是以θ＝sin－1（P w／P pix）表示。於是，區域邊框中扇出區域的高度H 1即為H 1＝D x・tanθ＝D x・tan（sin－1（P w／P pix））。 Here, referring to FIG. 7 , the method of obtaining the height H 1 of the frame area is explained by taking the wiring structure of a conventional liquid crystal panel as an example. First, assuming that the wiring pitch of the source lines in the active area is P pix , the wiring pitch of the source lines in the fan-out area is P w , and the pitch of the connection portion (output pad) of the source lines on the driver chip is P bp , from The distance from the connection portion at the outermost end of the driving chip to the source line at the outermost end of the display panel is Dx. Here, since P pix >P bp , a part of the source line connecting the driver chip and the active area must be tilted at a certain angle. The angle θ between the source line wiring located at the extreme end of the fan-out area and the direction axis in the orthogonal direction orthogonal to the source line extension direction in the effective area is expressed by θ = sin-1 (P w / P pix ) . Therefore, the height H 1 of the fan-out area in the area frame is H 1 =D x ·tanθ=D x ·tan (sin-1 (P w /P pix )).
依此方式，即可知H 1的數值是取決於D x，此D x值越大，H 1的數值亦越大。而且可知，θ越大，H 1的數值也越大。還有，P w越大，H 1的數值也越大。因P pix是由顯示面板尺寸及解析度所決定的值，故在實施源極線配線的時候，P pix可說是無法改變的固定值。P pix為一定的情況中，P w越大，θ也越大，H 1也跟著變大。依此方式，θ即屬於由P w及P pix所決定的值。 In this way, it can be seen that the value of H 1 depends on D x . The greater the value of D x , the greater the value of H 1 . Moreover, it can be seen that the larger θ is, the larger the value of H 1 is. Also, the larger P w is, the larger the value of H 1 is. Since P pix is a value determined by the size and resolution of the display panel, when implementing source line wiring, P pix can be said to be a fixed value that cannot be changed. When P pix is constant, the larger P w is, the larger θ will be, and H 1 will also become larger. In this way, θ is a value determined by P w and P pix .
以往，在1個面板上安裝多個源極驅動器的情況下，能夠減小D x的值，因此也能夠減小H 1的值。但是，若將源極驅動器和TCON施以整合而集成於1個晶片，則安裝於面板上的源極驅動器為1個，因此產生了D x的值變大，H 1的值也變大這樣的新的課題。 Conventionally, when multiple source drivers are mounted on one panel, the value of D x can be reduced, and therefore the value of H 1 can also be reduced. However, if the source driver and TCON are integrated into one chip, only one source driver will be mounted on the panel. Therefore, the value of D x will become larger, and the value of H 1 will also become larger. new topics.
在此，作為減小邊框尺寸的其他技術，已知有COF（Chip On Film）安裝。利用圖8說明與COG比較的由COF實現的邊框尺寸的縮小效果。Here, as another technology for reducing the frame size, COF (Chip On Film) mounting is known. The reduction effect of the frame size achieved by COF compared with COG will be explained using FIG. 8 .
如上所述，在COG安裝的情況下，H 1的值由H 1＝D x・tanθ決定。由於D x由從面板的兩端到晶片尺寸的橫向的尺寸決定，所以若安裝於面板上的晶片的數量變少，則D x的值變大，H 1的值也變大。另外，H 2的值由晶片的縱向尺寸和引出到面板的下部的配線區域的合計尺寸決定。例如，若14英寸顯示器的面板的橫向尺寸為309mm，晶片尺寸為30mm，則D x的值為309mm/2-30mm/2＝139.5mm。若將面板上的配線節距P w設為4mm，則H 1成為5.2mm。角度θ為2.1度。若將晶片的縱向的尺寸設為1mm，將面板下部的配線區域設為1mm，則H 2成為2mm。因此，將H 1和H 2合計後的面板的邊框尺寸為7.2mm。 As mentioned above, in the case of COG installation, the value of H 1 is determined by H 1 =D x ·tanθ. Since D x is determined by the lateral dimension from both ends of the panel to the chip size, as the number of chips mounted on the panel decreases, the value of D x increases and the value of H 1 also increases. In addition, the value of H2 is determined by the vertical size of the wafer and the total size of the wiring area led to the lower part of the panel. For example, if the lateral size of the panel of a 14-inch monitor is 309mm and the chip size is 30mm, the value of D x is 309mm/2-30mm/2=139.5mm. If the wiring pitch P w on the panel is 4 mm, H 1 becomes 5.2 mm. The angle θ is 2.1 degrees. If the vertical dimension of the wafer is 1 mm and the wiring area at the bottom of the panel is 1 mm, H 2 becomes 2 mm. Therefore, the bezel size of the panel after adding H 1 and H 2 is 7.2mm.
與此相對，在COF安裝的情況下，能夠增大膜的橫向尺寸。通常流通的COF的膜的橫向尺寸為60mm左右，D x的值為309mm/2-60mm/2＝124.5mm。若面板的英寸數、配線節距、θ與COG安裝的情況相同，則H 1的值由H1＝D x・tanθ決定，因此能夠縮短至4.6mm。另外，在COF安裝的情況下，不需要COG安裝所需的H 2中的晶片的縱向尺寸，因此COF中的H 2為1mm即可。因此，將H 1和H 2合計後的面板的邊框尺寸能夠縮小至5.6mm。另外，COF膜是薄膜，能夠向顯示器背面折彎，因此COF膜的縱向尺寸不會對面板的邊框尺寸產生影響。 On the other hand, when COF is mounted, the lateral dimension of the membrane can be increased. The lateral size of the generally circulated COF membrane is about 60mm, and the value of D x is 309mm/2-60mm/2=124.5mm. If the panel inches, wiring pitch, and θ are the same as those for COG installation, the value of H1 is determined by H1 = D x tanθ, so it can be shortened to 4.6mm. In addition, in the case of COF mounting, the longitudinal dimension of the wafer in H2 required for COG mounting is not required, so H2 in COF is 1mm. Therefore, the frame size of the panel after adding H 1 and H 2 can be reduced to 5.6mm. In addition, the COF film is a thin film that can be bent toward the back of the display, so the longitudinal size of the COF film will not affect the frame size of the panel.
這樣，若使用COF安裝技術，則能得到能夠縮小邊框尺寸的效果。但是，在將具有多個源極驅動器輸出通道的晶片安裝於COF的情況下，由於COF膜的配線節距的制約，此前需要具有2層配線構造的膜。其結果，與製造成本為1層的COF相比格外昂貴，沒有進展到普及。In this way, if COF mounting technology is used, the effect of reducing the frame size can be achieved. However, when a wafer having a plurality of source driver output channels is mounted on a COF, a film having a two-layer wiring structure has previously been required due to restrictions on the wiring pitch of the COF film. As a result, the manufacturing cost is extremely expensive compared to the COF with a single layer, and it has not been popularized.
通過圖9對利用了具有2層配線構造的膜的以往的COF安裝進行說明。若將COG安裝的多通道源極驅動器的通道數設為2880通道，則從晶片引出的部分（放大圖A）的COF配線節距至少需要10μm。另外，若將通常流通的COF的膜的橫向尺寸設為60mm，則COF膜的端部（放大圖B）的配線節距是60mm/2880＝20.8μm為最小節距。當前流通的COF的大半為1層配線構造，1層配線的最小節距為20μm左右是極限。因此，該COG安裝的多通道源極驅動器無法在1層配線構造的COF中安裝。市場上還存在2層配線構造的COF，如圖8所示，如果使用2層配線，則能夠對以10μm節距設計的COG安裝的多通道源極驅動器進行COF安裝。但是，2層配線構造的COF與1層配線構造的COF相比格外昂貴，因此幾乎沒有使用。Conventional COF mounting using a film having a two-layer wiring structure will be described with reference to FIG. 9 . If the number of channels of the COG-mounted multi-channel source driver is set to 2880 channels, the COF wiring pitch of the part leading out from the chip (enlarged view A) needs to be at least 10 μm. In addition, if the lateral dimension of the COF membrane that circulates normally is 60 mm, the wiring pitch at the end of the COF membrane (enlarged view B) is 60 mm/2880 = 20.8 μm as the minimum pitch. Most of the COFs currently in circulation have a single-layer wiring structure, and the minimum pitch of one-layer wiring is about 20 μm. Therefore, this COG-mounted multi-channel source driver cannot be mounted in a COF with a 1-layer wiring structure. There are also COFs with a 2-layer wiring structure on the market. As shown in Figure 8, if 2-layer wiring is used, COF mounting of multi-channel source drivers designed with COG mounting at a 10 μm pitch can be performed. However, COF with a two-layer wiring structure is extremely expensive compared to COF with a single-layer wiring structure, so it is rarely used.
因此，本發明的主要目的在於，提供一種用於將在COG安裝中使用的具有多個源極驅動器輸出通道的晶片安裝於1層配線構造的COF的技術，從而實現廉價的窄邊框顯示器。Therefore, a main object of the present invention is to provide a technology for mounting a wafer having a plurality of source driver output channels used in COG mounting on a COF with a single-layer wiring structure, thereby realizing an inexpensive narrow-frame display.
解決課題的技術方案 本發明的發明人對上述問題的解決手段進行了深入研究，結果得到如下見解：採用多個連接端子排列配置為多列的驅動晶片，並且通過在屬於某列的連接端子和屬於其下一列的連接端子使訊號線的引出方式不同，藉此，能夠將具有多個源極驅動器輸出通道的驅動晶片安裝於1層配線構造的COF。而且，發明人等基於上述見解想到能夠解決先前技術的問題，並完成了本發明。以下，對本發明的構成進行具體說明。 Technical solutions to solve problems The inventor of the present invention conducted in-depth research on the solution to the above problem and obtained the following insights: using a plurality of connection terminals arranged in a plurality of rows of drive chips, and connecting the connection terminals belonging to a certain column and the connection terminals belonging to the next column. The connection terminals allow the signal lines to be drawn out differently, thereby enabling a driver chip with multiple source driver output channels to be mounted on a COF with a single-layer wiring structure. Furthermore, the inventors thought that the problems of the prior art could be solved based on the above knowledge, and completed the present invention. Hereinafter, the structure of this invention is demonstrated concretely.
本發明的第一側面是關於用於向液晶面板等顯示面板輸出繪圖資料的資料輸出裝置（10）。此資料輸出裝置（10）較佳為COF（Chip On Film）安裝的模組。本發明的資料輸出裝置（10）具備：驅動晶片（20）以及與此連接的多個訊號線（31、32、41）。驅動晶片（20）具有多個連接端子（21、22）。驅動晶片（20）可以是源極驅動器，也可以是閘極驅動器，也可以是將源極驅動器和時序控制器施以整合而得的所謂的系統驅動器。在本發明中，驅動晶片（20）較佳為僅在膜（11）上配置一個，但並不限定於此，也可以在膜（11）上配置多個（例如2～4個）。另外，多個訊號線（31、32、41）各自的一端與驅動晶片（20）的連接端子（21、22）連接，訊號線的另一端與用於往顯示面板輸出訊號的輸出端子（13）連接。這樣，訊號線（31、32、41）在膜（11）上以將連接端子（21、22）和輸出端子（13）連接之方式配線。此外，訊號線（31、32、41）可以是與源極驅動器連接的源極線，也可以是與閘極驅動器連接的閘極線。A first aspect of the present invention relates to a data output device (10) for outputting drawing data to a display panel such as a liquid crystal panel. This data output device (10) is preferably a COF (Chip On Film) installed module. The data output device (10) of the present invention includes a driving chip (20) and a plurality of signal lines (31, 32, 41) connected thereto. The driver chip (20) has a plurality of connection terminals (21, 22). The driver chip (20) may be a source driver, a gate driver, or a so-called system driver that integrates a source driver and a timing controller. In the present invention, it is preferable that only one driving chip (20) is arranged on the film (11), but it is not limited to this, and a plurality of driving wafers (20) may be arranged on the film (11) (for example, 2 to 4). In addition, one end of each of the plurality of signal lines (31, 32, 41) is connected to the connection terminal (21, 22) of the driver chip (20), and the other end of the signal line is connected to the output terminal (13) for outputting a signal to the display panel. ) connection. In this way, the signal lines (31, 32, 41) are wired on the membrane (11) to connect the connection terminals (21, 22) and the output terminal (13). In addition, the signal lines (31, 32, 41) may be source lines connected to the source driver, or may be gate lines connected to the gate driver.
在此，驅動晶片（20）的連接端子（21、22）排列配置為3列。即，在本申請的圖中，往顯示面板的多個輸出端子（13）所排列的方向用「x軸」表示，將與此x軸正交的方向用「y軸」表示（例如參照圖10）。在此情況下，連接端子（21、22）的列沿著x軸方向延伸，相對於y軸方向以多層排列。在此，將多個連接端子、特別是源極連接端子（21）的列按照接近輸出端子的順序設為第一列、第二列、第三列。在此情況下，在屬於第一列及第三列的多個連接端子（21）中，包含訊號線（31）以向朝向輸出端子（13）的方向引出之方式連接的連接端子。另一方面，在屬於第二列的多個連接端子（21）中，包含訊號線（32）以朝向與連接於屬於第一列的連接端子（21）的訊號線（31）不同的方向引出之方式連接的連接端子。此外，這裡所說的「不同的方向」包括例如遠離輸出端子（13）的方向。而且，從屬於第二列的連接端子（21）引出的訊號線（32）中包含通過屬於第三列的連接端子（21）之間的訊號線。此外，從屬於第三列的連接端子（21）引出的訊號線（31）中包含通過屬於第一列及第二列的連接端子（21）之間的訊號線。此外，不需要從多個連接端子（21）的全部引出訊號線（31、32），也可以從連接端子（21）的一部分引出訊號線（31、32）。另外，這裡所說的訊號線從連接端子「引出」的方向是指訊號線中最靠近連接端子的部分被配線的方向，不是指訊號線整體的配線方向。Here, the connection terminals (21, 22) of the driver chip (20) are arranged in three rows. That is, in the drawings of the present application, the direction in which the plurality of output terminals (13) of the display panel are arranged is represented by the "x-axis", and the direction orthogonal to the x-axis is represented by the "y-axis" (for example, refer to FIG. 10). In this case, the rows of connection terminals (21, 22) extend in the x-axis direction and are arranged in multiple layers with respect to the y-axis direction. Here, the rows of the plurality of connection terminals, particularly the source connection terminals ( 21 ), are designated as the first row, the second row, and the third row in order of being closer to the output terminals. In this case, the plurality of connection terminals (21) belonging to the first and third columns include connection terminals in which the signal lines (31) are connected so as to be drawn out in the direction toward the output terminal (13). On the other hand, among the plurality of connection terminals (21) belonging to the second column, the signal line (32) is drawn out in a direction different from the signal line (31) connected to the connection terminal (21) belonging to the first column. way to connect the connection terminals. In addition, the "different directions" mentioned here include, for example, the direction away from the output terminal (13). Furthermore, the signal lines (32) drawn from the connection terminals (21) belonging to the second column include signal lines passing between the connection terminals (21) belonging to the third column. In addition, the signal lines (31) drawn from the connection terminals (21) belonging to the third column include signal lines passing between the connection terminals (21) belonging to the first column and the second column. In addition, the signal lines (31, 32) do not need to be led out from all of the plurality of connection terminals (21), and the signal lines (31, 32) may be led out from a part of the connection terminals (21). In addition, the direction in which the signal line "leads out" from the connection terminal mentioned here refers to the direction in which the portion of the signal line closest to the connection terminal is wired, and does not refer to the wiring direction of the entire signal line.
如上述構成那樣，針對在驅動晶片（20）以多列設置的連接端子（21），通過某列的連接端子（21）和其下一列的連接端子（21）改變訊號線（31、32、41）的引出方式，從而能夠有效利用配置驅動晶片（20）及訊號線（31、32、41）的膜上的空間。特別是，通過在驅動晶片（20）上將連接端子（21）排列配置為3列以上，以穿過各訊號端子（21）之間之方式將訊號線（31、32）配線，從而能夠有效利用配置驅動晶片（20）及訊號線（31、32）的膜上的空間。結果，能夠將在COG安裝中使用的具有多個源極驅動器輸出通道的晶片安裝於1層配線構造的COF。藉此，能夠廉價地實現顯示模組的窄邊框化。As configured above, for the connection terminals (21) arranged in multiple rows on the driver chip (20), the signal lines (31, 32, 41), thereby effectively utilizing the space on the film where the driver chip (20) and the signal lines (31, 32, 41) are arranged. In particular, by arranging the connection terminals (21) in three or more rows on the driver chip (20) and wiring the signal lines (31, 32) so as to pass between the respective signal terminals (21), it is possible to effectively Utilize the space on the film where the driver chip (20) and the signal lines (31, 32) are arranged. As a result, a wafer having a plurality of source driver output channels used in COG mounting can be mounted on a COF with a single-layer wiring structure. In this way, the bezel of the display module can be realized at a low cost.
在本發明的資料輸出裝置（10）中，也可以是，驅動晶片（20）的連接端子（21）以4列以上配置。在此，將多個連接端子、特別是源極連接端子（21）的列按照接近輸出端子的順序設為第一列、第二列、第三列、第四列。在此情況下，較佳為從屬於第二列的連接端子（21）引出的訊號線（32）中包含通過屬於第三列及第四列的連接端子（21）之間的訊號線。這樣，通過在驅動晶片（20）上配置4列以上的連接端子（21），能夠更有效地利用膜上的空間。In the data output device (10) of the present invention, the connection terminals (21) of the drive chip (20) may be arranged in four or more rows. Here, the columns of the plurality of connection terminals, particularly the source connection terminals ( 21 ), are designated as the first column, the second column, the third column, and the fourth column in order of being closer to the output terminals. In this case, it is preferable that the signal line (32) drawn from the connection terminal (21) belonging to the second column includes a signal line passing between the connection terminals (21) belonging to the third column and the fourth column. In this way, by arranging four or more rows of connection terminals (21) on the drive wafer (20), the space on the film can be used more effectively.
在本發明的資料輸出裝置（10）中，也可以是，與屬於第二列的連接端子（21）連接的多個訊號線（32）中，包含從連接端子（21）向遠離輸出端子（13）的方向引出，之後向朝向輸出端子（13）的方向配線的訊號線。藉此，能夠有效利用驅動晶片20的背後側（與輸出端子相反的一側）的空間。In the data output device (10) of the present invention, the plurality of signal lines (32) connected to the connection terminals (21) belonging to the second column may include a line extending from the connection terminal (21) to the output terminal ( The signal wire is led out in the direction of 13) and then wired in the direction of the output terminal (13). Thereby, the space on the rear side of the driving chip 20 (the side opposite to the output terminal) can be effectively utilized.
在本發明的資料輸出裝置（10）中，也可以是，在與屬於所述某列的接下來靠近輸出端子（13）的列的連接端子（21）連接的多個訊號線（32）中，包含在與輸出端子（13）的排列方向（x軸方向）平行的方向上從連接端子（21）引出，之後向朝向輸出端子（13）的方向配線的訊號線。藉此，能夠有效利用驅動晶片（20）的側邊的空間。In the data output device (10) of the present invention, the plurality of signal lines (32) connected to the connection terminals (21) of the column next to the output terminal (13) belonging to the certain column may be , including a signal line that is led out from the connection terminal (21) in a direction parallel to the arrangement direction (x-axis direction) of the output terminal (13) and then wired in a direction toward the output terminal (13). Thereby, the space on the side of the driving chip (20) can be effectively utilized.
在本發明的資料輸出裝置（10）中，較佳為在引入了虛擬線的情況下，各連接端子（21）以此虛擬線不與其他連接端子（21）重疊之方式配置，所述虛擬線與從驅動晶片（20）的多個連接端子（21）朝向往顯示面板的輸出端子（13）的方向（y軸方向）平行。即，在各列中，連接端子（21）以相互不同之方式偏移配置。藉此，容易以全部的訊號線（31、32、41）不發生干擾之方式從各連接端子（21）引出訊號線（31、32、41）。In the data output device (10) of the present invention, when a virtual line is introduced, each connection terminal (21) is preferably arranged in such a manner that the virtual line does not overlap with other connection terminals (21). The line is parallel to the direction (y-axis direction) from the plurality of connection terminals (21) of the driving chip (20) toward the output terminal (13) of the display panel. That is, in each column, the connection terminals (21) are shifted and arranged in a mutually different manner. This makes it easy to lead the signal lines (31, 32, 41) from each connection terminal (21) without causing interference to all the signal lines (31, 32, 41).
本發明的第二側面是關於顯示模組。本發明的顯示模組具備：所述第一側面的資料輸出裝置（10）；以及透過輸出端子（13）連接有訊號線（31、32、41）的顯示面板。The second aspect of the present invention relates to a display module. The display module of the present invention includes: a data output device (10) on the first side; and a display panel connected to signal lines (31, 32, 41) through the output terminal (13).
[發明功效] 根據本發明，提供將在COG安裝中使用的具有多個源極驅動器輸出通道的晶片安裝於1層配線構造的COF的技術，藉此能夠廉價地實現窄邊框顯示器。另外，由於能夠無設計變更地對設計成COG安裝用的晶片進行COF安裝，因此能夠抑制半導體製造商的開發費用，在面板製造商、PC製造商中能夠抑制晶片的再評價時間、成本。 [Invention effect] According to the present invention, a technology for mounting a chip having a plurality of source driver output channels used in COG mounting on a COF with a single-layer wiring structure is provided, whereby a narrow-frame display can be realized at low cost. In addition, since COF mounting can be performed on wafers designed for COG mounting without design changes, development costs for semiconductor manufacturers can be reduced, and wafer re-evaluation time and costs for panel manufacturers and PC manufacturers can be reduced.
另外，以往，在削減了驅動器的個數的情況下，難以進行顯示面板的窄邊框化，但根據本發明，能夠廉價地實現顯示面板的窄邊框化。例如，在14英寸的FHD面板中，在先前技術中邊框尺寸為7.2mm的面板能夠削減至5.6mm，能夠將邊框尺寸削減20～30％左右。In addition, conventionally, it was difficult to narrow the frame of the display panel when the number of drivers was reduced. However, according to the present invention, the frame of the display panel can be narrowed at low cost. For example, in a 14-inch FHD panel, the panel with a frame size of 7.2mm in the previous technology can be reduced to 5.6mm, which can reduce the frame size by about 20 to 30%.
以下，使用圖式對用於實施本發明的方式進行說明。本發明並不限定於以下說明的實施方式，還包括從以下的方式中在本發明所屬技術領域中具有通常知識者顯而易見的範圍內適當變更的內容。本發明也能夠適當組合以下說明的各實施方式，也能夠單獨利用各實施方式。Hereinafter, the mode for carrying out the present invention will be described using the drawings. The present invention is not limited to the embodiments described below, but includes modifications in the following forms as appropriate within the scope that is obvious to a person skilled in the art to which the present invention belongs. In the present invention, each of the embodiments described below can be appropriately combined, or each embodiment can be used individually.
圖10表示本發明的一個實施方式。另外，圖11是將圖10的一部分放大並加入了輔助說明之圖。本實施方式是關於用於以COF技術來實現窄邊框液晶面板的COF模組10。COF模組10例如能夠應用於筆記型電腦、平板電腦，有助於液晶面板的窄邊框化。Fig. 10 shows an embodiment of the present invention. In addition, FIG. 11 is a diagram in which a part of FIG. 10 is enlarged and supplementary explanation is added. This embodiment relates to a COF module 10 for realizing a narrow-frame liquid crystal panel using COF technology. The COF module 10 can be applied to, for example, notebook computers and tablet computers, and contributes to narrowing the bezel of the liquid crystal panel.
如圖10所示，COF模組10基本上包括膜11、驅動晶片20、多個訊號線31、32、41、51而構成。在訊號線中包含源極線31、32、閘極訊號驅動線41、影像訊號和電力的輸入線51。在此COF模組10中，驅動晶片20和多個訊號線31、32、41、51安裝在作為配線電路基板發揮功能的膜11上。膜11沒有特別限制，能夠適當採用習知的膜。As shown in FIG. 10 , the COF module 10 basically includes a film 11 , a driving chip 20 , and a plurality of signal lines 31 , 32 , 41 , and 51 . The signal lines include source lines 31 and 32, a gate signal driving line 41, and an input line 51 for image signals and power. In this COF module 10, the driver chip 20 and the plurality of signal lines 31, 32, 41, 51 are mounted on the film 11 functioning as a printed circuit board. The membrane 11 is not particularly limited, and a conventional membrane can be appropriately used.
驅動晶片20是將時序控制器（TCON）和源極驅動器（SD）施以整合而成的晶片，承擔對顯示面板的源極線輸出繪圖資料的功能、以及對輸出所述繪圖資料的時序進行控制的功能。在圖8所示的例子中，由於驅動晶片20是承擔時序控制器和源極驅動器雙方的功能的晶片，所以在此驅動晶片20上除了源極線31、32之外還連接有閘極訊號驅動線41。但是，雖然省略了圖示，但也可以使驅動晶片20僅具有源極驅動器的功能，使時序控制器獨立存在。在驅動晶片20僅作為源極驅動器發揮功能的情況下，閘極訊號驅動線41與另外設置的時序控制器連接即可。The driver chip 20 is a chip that integrates a timing controller (TCON) and a source driver (SD). It is responsible for the function of outputting graphics data to the source lines of the display panel and controlling the timing of outputting the graphics data. Control function. In the example shown in FIG. 8 , since the driver chip 20 is a chip that functions as both a timing controller and a source driver, in addition to the source lines 31 and 32 , the driver chip 20 is also connected to gate signals. Drive line 41. However, although illustration is omitted, the driver chip 20 may only have the function of a source driver, and the timing controller may exist independently. When the driving chip 20 only functions as a source driver, the gate signal driving line 41 only needs to be connected to a separately provided timing controller.
時序控制器（驅動晶片20的功能的一部分）將從CPU或GPU等處理器發送的繪圖資料作為輸入，進行顯示面板的時序控制、圖像處理。源極驅動器（驅動晶片20的功能的一部分）是用於驅動顯示面板的源極線的電路。源極驅動器將來自時序控制器的繪圖資料作為輸入，配合顯示面板型式而類比輸出繪圖資料。源極驅動器與多個源極線連接，對各源極線施加驅動電壓（灰階顯示電壓）。在顯示模組中，也能夠針對一個顯示面板配備多個源極驅動器，但從削減組件數以及削減消耗電力的觀點出發，相對於一個顯示面板較佳為僅配備一個源極驅動器。另外，雖然省略圖示，但顯示模組除了源極驅動器之外，還可以具備驅動顯示面板的閘極線的閘極驅動器。閘極驅動器向各閘極線依次施加用於使TFT（Thin Film Transistor：薄膜電晶體）接通的掃描訊號。在通過閘極驅動器對閘極線施加操作訊號而TFT為接通狀態時，若從源極驅動器對源極線施加驅動電壓，則會在位於這些交點的顯示元件中蓄積電荷。藉此，顯示元件的光透射率根據施加於源極線的驅動電壓而變化，進行透過顯示元件之圖像顯示。The timing controller (part of the function of the driver chip 20) takes drawing data sent from a processor such as a CPU or a GPU as input to perform timing control and image processing of the display panel. The source driver (part of the function of the driver chip 20) is a circuit for driving the source lines of the display panel. The source driver takes the drawing data from the timing controller as input and outputs the drawing data analogously according to the display panel type. The source driver is connected to a plurality of source lines and applies a driving voltage (grayscale display voltage) to each source line. In a display module, one display panel can also be equipped with multiple source drivers, but from the viewpoint of reducing the number of components and reducing power consumption, it is better to be equipped with only one source driver than one display panel. In addition, although illustration is omitted, the display module may include a gate driver that drives the gate lines of the display panel in addition to the source driver. The gate driver sequentially applies a scanning signal for turning on a TFT (Thin Film Transistor: thin film transistor) to each gate line. When an operation signal is applied to the gate line through the gate driver and the TFT is in the on state, if a driving voltage is applied to the source line from the source driver, charges will be accumulated in the display elements located at these intersections. Thereby, the light transmittance of the display element changes according to the driving voltage applied to the source line, and an image is displayed through the display element.
此外，顯示面板通常由源極線、閘極線以及顯示像素構成。源極線在由玻璃等構成的面板基板上隔開預定的間隔而相互平行地設置有多條。閘極線在相同的面板基板上沿著與源極線正交的方向隔開預定的間隔而相互平行地設置有多條。顯示像素設置於源極線與閘極線的各交叉點。各顯示像素與作為開關元件的TFT連接。例如，在FHD的液晶面板的情況下，源極線需要1920×3（RGB）線，閘極線需要1080線。In addition, the display panel is usually composed of source lines, gate lines and display pixels. A plurality of source lines are provided in parallel with each other at predetermined intervals on a panel substrate made of glass or the like. A plurality of gate lines are provided in parallel with each other at predetermined intervals along a direction orthogonal to the source lines on the same panel substrate. Display pixels are arranged at each intersection of the source line and the gate line. Each display pixel is connected to a TFT as a switching element. For example, in the case of an FHD LCD panel, the source line requires 1920×3 (RGB) lines, and the gate line requires 1080 lines.
如圖10所示，在膜11上設置有多個輸入端子12及多個輸出端子13。在設想膜11是矩形的情況下，多個輸入端子12在膜11的下邊沿著x軸方向排列設置，多個輸出端子13在膜11的上邊沿著x軸方向排列設置。此外，這裡所說的膜11的上邊是指顯示面板側的邊，膜11的下邊是指與顯示面板相反一側的邊。在輸入端子12連接有用於從處理器接收影像訊號的輸入線51、用於從電源接受電力的輸入線51。輸出端子13是用於將由驅動晶片20處理後的影像訊號往顯示面板輸出的端子，在輸出端子13連接有顯示面板的閘極線、源極線。As shown in FIG. 10 , a plurality of input terminals 12 and a plurality of output terminals 13 are provided on the film 11 . When it is assumed that the film 11 is rectangular, a plurality of input terminals 12 are arranged along the x-axis direction on the lower side of the film 11 , and a plurality of output terminals 13 are arranged on the upper side of the film 11 along the x-axis direction. In addition, the upper side of the film 11 here refers to the side on the display panel side, and the lower side of the film 11 refers to the side opposite to the display panel. The input terminal 12 is connected to an input line 51 for receiving an image signal from the processor and an input line 51 for receiving power from a power source. The output terminal 13 is a terminal for outputting the image signal processed by the driving chip 20 to the display panel. The output terminal 13 is connected to the gate line and the source line of the display panel.
另外，在驅動晶片20具備用於與膜11上的輸入端子12及輸出端子13電性連接的多個連接端子21、22、23。多個連接端子包括多個源極連接端子21、多個閘極連接端子22以及多個輸入連接端子23。各源極連接端子21通過源極線31、32與輸出端子13電性連接。即，源極線31、32的一端與源極連接端子21連接，源極線31、32的另一端與輸出端子13連接。另外，各閘極連接端子22通過閘極訊號驅動線41與輸出端子13電性連接。即，閘極訊號驅動線41的一端與閘極連接端子22連接，閘極訊號驅動線41的另一端與輸出端子13連接。另外，各輸入連接端子23通過輸入用的訊號線與輸出端子13連接。在設想驅動晶片20為矩形的情況下，閘極連接端子22及輸入連接端子23在膜11的下邊沿著x軸方向排列設置。另一方面，源極連接端子21在驅動晶片20上的平面區域排列配置為多列。In addition, the driving chip 20 is provided with a plurality of connection terminals 21 , 22 , and 23 for electrically connecting to the input terminal 12 and the output terminal 13 on the film 11 . The plurality of connection terminals include a plurality of source connection terminals 21 , a plurality of gate connection terminals 22 and a plurality of input connection terminals 23 . Each source connection terminal 21 is electrically connected to the output terminal 13 through source lines 31 and 32 . That is, one end of the source lines 31 and 32 is connected to the source connection terminal 21 , and the other end of the source lines 31 and 32 is connected to the output terminal 13 . In addition, each gate connection terminal 22 is electrically connected to the output terminal 13 through the gate signal driving line 41 . That is, one end of the gate signal driving line 41 is connected to the gate connection terminal 22 , and the other end of the gate signal driving line 41 is connected to the output terminal 13 . In addition, each input connection terminal 23 is connected to the output terminal 13 through an input signal line. When the drive chip 20 is assumed to be rectangular, the gate connection terminals 22 and the input connection terminals 23 are arranged in an array along the x-axis direction under the film 11 . On the other hand, the source connection terminals 21 are arranged in a plurality of columns in a planar area on the drive wafer 20 .
針對源極連接端子21的配置進行具體說明。如圖10及圖11所示，源極連接端子21排列配置為多列。在這些圖所示的例子中，源極連接端子21排列為4列。在圖10及圖11中，為了容易理解源極連接端子21的列的概念，設源極連接端子21的第一列為白色、第二列為黑色、第三列為白色、第四列為黑色，將奇數列表示為白色，將偶數列表示為黑色。即，如圖11所示，源極連接端子21的第一列是形成於最接近輸出端子13的位置的列，第二列、第三列、第四列依此順序與輸出端子13的距離遠離。源極連接端子21的列沿著圖10的x軸方向延伸，可以說此各列在y軸方向上形成了階梯。The arrangement of the source connection terminal 21 will be described in detail. As shown in FIGS. 10 and 11 , the source connection terminals 21 are arranged in a plurality of columns. In the examples shown in these figures, the source connection terminals 21 are arranged in four columns. In FIGS. 10 and 11 , in order to easily understand the concept of the rows of the source connection terminals 21 , it is assumed that the first row of the source connection terminals 21 is white, the second row is black, the third row is white, and the fourth row is white. Black, represents odd-numbered columns as white and even-numbered columns as black. That is, as shown in FIG. 11 , the first row of source connection terminals 21 is the row formed closest to the output terminal 13 , and the distances between the second row, the third row, and the fourth row in this order from the output terminal 13 are Stay away. The rows of source connection terminals 21 extend along the x-axis direction in FIG. 10 , and each row can be said to form a step in the y-axis direction.
另外，屬於各列的源極連接端子21以各自相互不同之方式偏移配置。即，如圖11所示，較佳為在以通過各源極連接端子21的中心之方式引出與y軸平行的虛擬線時，使各虛擬線不與其他源極連接端子21重疊。換言之，屬於某列的源極連接端子21間的x軸方向上的間隔（節距）較佳為源極連接端子21的橫寬的N倍以上（N為源極連接端子21的列數）。藉此，容易從各源極連接端子21引出源極線31、32。In addition, the source connection terminals 21 belonging to each column are offset and arranged so as to be different from each other. That is, as shown in FIG. 11 , when an imaginary line parallel to the y-axis is drawn so as to pass through the center of each source connection terminal 21 , it is preferable that each imaginary line does not overlap with other source connection terminals 21 . In other words, the spacing (pitch) in the x-axis direction between the source connection terminals 21 belonging to a certain column is preferably N times or more of the lateral width of the source connection terminals 21 (N is the number of columns of the source connection terminals 21). . This makes it easy to draw out the source lines 31 and 32 from each source connection terminal 21 .
在此，在本實施方式中，將與屬於第一列及第三列的多個源極連接端子21連接的源極線稱為第一源極線組31。此第一源極線組31從源極連接端子21朝向輸出端子13引出，直接與輸出端子13連接。特別是，從屬於第一列的源極連接端子21引出的第一源極線組31全部以一條直線狀朝向輸出端子13延伸。另外，在從屬於第三列的源極連接端子21引出的第一源極線組31中，包含為了避開第二列的源極連接端子21而以迂回之方式進行配線的源極線，但也包含一條直線狀地朝向輸出端子13延伸的源極線。此時，如圖11等所示，從屬於第三列的源極連接端子21引出的第一源極線組31以通過屬於第二列的源極連接端子21之間且通過屬於第一列的源極連接端子21之間之方式朝向輸出端子13配線。因此，較佳為，屬於第一列的源極連接端子21之間的間隔與屬於第二列的源極連接端子21之間的間隔分別確保至少從屬於第三列的源極連接端子21引出的第一源極線組31能夠通過的程度的間隔。Here, in this embodiment, the source lines connected to the plurality of source connection terminals 21 belonging to the first column and the third column are called the first source line group 31 . The first source line group 31 is led out from the source connection terminal 21 toward the output terminal 13 and is directly connected to the output terminal 13 . In particular, all the first source line groups 31 drawn out from the source connection terminals 21 belonging to the first column extend in a straight line toward the output terminal 13 . In addition, the first source line group 31 drawn from the source connection terminals 21 belonging to the third column includes source lines wired in a roundabout way to avoid the source connection terminals 21 of the second column. However, it also includes a source line extending linearly toward the output terminal 13 . At this time, as shown in FIG. 11 etc., the first source line group 31 drawn from the source connection terminals 21 belonging to the third column passes between the source connection terminals 21 belonging to the second column and passes through the source connection terminals 21 belonging to the first column. The source connection terminals 21 are wired toward the output terminal 13 . Therefore, it is preferable that the intervals between the source connection terminals 21 belonging to the first column and the intervals between the source connection terminals 21 belonging to the second column ensure that at least the source connection terminals 21 belonging to the third column are drawn out. The spacing is such that the first source line group 31 can pass through.
另一方面，在本實施方式中，將與屬於第二列及第四列的多個源極連接端子21連接的源極線稱為第二源極線組32。第二源極線組32從屬於第二列及第四列的源極連接端子21暫時向遠離輸出端子13的方向引出。第二源極線組32在這樣朝向遠離輸出端子13的方向從源極連接端子21引出而與y軸平行地前進之後，朝向左右（x軸方向）的外側前進，而且之後朝向輸出端子13以與y軸方向平行地前進之方式進行配線。此時，第二源極線組32至少在前進至第一列的多個源極連接端子21的左右外側之後，以不與其他源極線31、32發生干擾之方式，朝向輸出端子13以一條直線狀地前進之方式配線。另外，在從屬於第二列的源極連接端子21引出的第二源極線組32中，包含為了避開第三列的源極連接端子21而以迂回之方式進行配線的源極線。此時，如圖11等所示，在從屬於第二列的源極連接端子21引出的第二源極線組32中，包含以通過屬於第三列的源極連接端子21之間且通過屬於第四列的源極連接端子21之間之方式，朝向遠離輸出端子13的方向配線的源極線。因此，屬於第三列的源極連接端子21之間的間隔與屬於第四列的源極連接端子21之間的間隔較佳為分別確保至少從屬於第二列的源極連接端子21引出的第二源極線組32能夠通過的程度的間隔。這樣，在本實施方式中，通過屬於奇數列的源極連接端子21（白色）和屬於偶數列的源極連接端子21（黑色）使源極線31、32的引出方向不同。On the other hand, in this embodiment, the source lines connected to the plurality of source connection terminals 21 belonging to the second column and the fourth column are called the second source line group 32 . The second source line group 32 is temporarily led out from the source connection terminals 21 belonging to the second column and the fourth column in a direction away from the output terminal 13 . After being drawn out from the source connection terminal 21 in the direction away from the output terminal 13 and advancing parallel to the y-axis, the second source line group 32 advances to the left and right (x-axis direction) outside, and then moves toward the output terminal 13 in the direction of the y-axis. Wire in such a way that it advances parallel to the y-axis direction. At this time, the second source line group 32 advances to at least the left and right outer sides of the plurality of source connection terminals 21 in the first row, and then moves toward the output terminal 13 without interfering with the other source lines 31 and 32 . Wire in a straight line. In addition, the second source line group 32 drawn from the source connection terminals 21 belonging to the second column includes source lines wired in a roundabout way to avoid the source connection terminals 21 of the third column. At this time, as shown in FIG. 11 etc., the second source line group 32 drawn from the source connection terminals 21 belonging to the second column includes lines passing between the source connection terminals 21 belonging to the third column and passing through The sources belonging to the fourth column are source lines wired in a direction away from the output terminals 13 so as to connect between the terminals 21 . Therefore, the intervals between the source connection terminals 21 belonging to the third column and the intervals between the source connection terminals 21 belonging to the fourth column are preferably such that at least the distances drawn from the source connection terminals 21 belonging to the second column are ensured respectively. The distance is such that the second source line group 32 can pass through. In this way, in this embodiment, the source connection terminals 21 (white) belonging to the odd-numbered columns and the source connection terminals 21 (black) belonging to the even-numbered columns have different extraction directions of the source lines 31 and 32 .
另外，如圖10及圖11所示，針對第一列及第三列的源極連接端子21，從全部的所述源極連接端子引出第一源極線組31。另一方面，針對第二列及第四列的源極連接端子21，不是從全部的所述源極連接端子引出第二源極線組32，而是僅在位於驅動晶片20的左右外側的幾個源極連接端子21引出第二源極線組32。在圖示的例子中，對於第二列以及第四列的源極連接端子21中的各列，僅在左右各4個（各列合計8個）源極連接端子21引出有第二源極線組32。這樣，不一定需要對於所有的源極連接端子21連接源極線31、32。此外，針對第二列和第四列，連接第二源極線組32的源極連接端子21的數量不限於上述的左右各4個，例如可以是左右各2個，也可以是左右5個以上。此數量可以適當調整。In addition, as shown in FIGS. 10 and 11 , for the source connection terminals 21 in the first and third columns, the first source line group 31 is drawn out from all the source connection terminals. On the other hand, for the source connection terminals 21 in the second and fourth columns, the second source line group 32 is not drawn out from all the source connection terminals, but only from the left and right outer sides of the driving chip 20 . Several source connection terminals 21 lead out a second source line group 32 . In the example shown in the figure, for each of the source connection terminals 21 in the second and fourth columns, only four source connection terminals 21 on the left and right (a total of eight in each column) have second sources drawn out. Line set 32. In this way, it is not necessarily necessary to connect the source lines 31 and 32 to all the source connection terminals 21 . In addition, for the second column and the fourth column, the number of source connection terminals 21 connected to the second source line group 32 is not limited to the above-mentioned 4 on the left and right, for example, it may be 2 on the left and 5 on the left, or 5 on the left and right. above. This quantity can be adjusted appropriately.
如圖10及圖11所示，通過在膜11上設置向朝向輸出端子13的方向引出的第一源極線組31與向遠離輸出端子13的方向引出的第二源極線組32，即使驅動晶片20的源極連接端子21的節距例如為10μm，在膜11上配線的配線節距也能夠設為2倍的20μm。第二源極線組32在暫時向圖的下部方向引出後，向橫向前進，之後以向上部方向前進之方式進行配線，藉此能夠與顯示面板的源極線連接。另外，第一源極線組31在膜11上僅存在向圖的上部方向引出的配線。在驅動晶片20的源極連接端子21的節距例如為10μm的情況下，以在膜11上配線的配線節距成為2倍的20μm之方式，例如跳過1層向上部方向引出。此外，由於在驅動晶片20的下部方向存在向驅動晶片20輸入的影像輸入線、電源輸入線等51的配線，所以無法引出第一以及第二源極線組31、32。As shown in FIGS. 10 and 11 , by providing the first source line group 31 drawn in the direction toward the output terminal 13 and the second source line group 32 drawn in the direction away from the output terminal 13 on the film 11 , even The pitch of the source connection terminals 21 of the drive wafer 20 is, for example, 10 μm, and the wiring pitch of the wiring on the film 11 can be doubled to 20 μm. The second source line group 32 is temporarily drawn out in the lower direction of the figure, then advances laterally, and then is wired in an upward direction, thereby being connected to the source lines of the display panel. In addition, the first source line group 31 has only wiring extending in the upper direction of the figure on the film 11 . When the pitch of the source connection terminals 21 of the driver wafer 20 is, for example, 10 μm, the wiring on the film 11 is led out in the upper direction, skipping one layer, so that the wiring pitch becomes twice 20 μm. In addition, since the wiring of the image input line, power input line, etc. 51 input to the driving chip 20 exists in the lower direction of the driving chip 20, the first and second source line groups 31 and 32 cannot be drawn out.
例如，若將COG安裝的多通道的驅動晶片20整體的輸出端子13的通道數設為2880通道，則第二源極線組32設為左右分別為例如800通道，第一源極線組31設為中央部的例如640通道，能夠引出合計2240通道的源極線。例如，在FHD面板中，具有多工器構成的LTPS面板、OXIDE面板需要將1920個通道的源極線從驅動晶片20引出，但在本實施方式中如果引出2240通道則能夠應對。藉此，能夠將在COG安裝中使用的具有多個源極驅動器輸出通道的晶片安裝於1層配線構造的COF，能夠廉價地實現窄邊框顯示器。For example, if the number of channels of the entire output terminal 13 of the COG-mounted multi-channel driver chip 20 is set to 2880 channels, then the second source line group 32 is set to have, for example, 800 channels on the left and right, and the first source line group 31 Assuming, for example, 640 channels in the center, a total of 2240 channels of source lines can be drawn. For example, among FHD panels, LTPS panels and OXIDE panels having a multiplexer configuration require 1920 channels of source lines to be led out from the driver chip 20, but in this embodiment, 2240 channels can be led out. This makes it possible to mount a chip with multiple source driver output channels used in COG mounting on a COF with a single-layer wiring structure, enabling a narrow-frame display to be realized at low cost.
此外，如圖10所示，在驅動晶片20的下邊側設置有多個閘極連接端子22。在此閘極連接端子22分別連接有閘極訊號驅動線41。閘極訊號驅動線41暫時從閘極連接端子22朝向遠離輸出端子13的方向引出。另外，閘極訊號驅動線41在以這樣的方式從閘極連接端子22朝向遠離輸出端子13的方向引出之後，朝向左右外側前進，而且之後以朝向輸出端子13前進之方式進行配線。閘極訊號驅動線41最終與多個輸出端子13中的位於比連接有多個源極線31、32的輸出端子13更靠左右的外側的輸出端子13（Gate Output，閘極輸出）連接。In addition, as shown in FIG. 10 , a plurality of gate connection terminals 22 are provided on the lower side of the driver chip 20 . The gate connection terminals 22 are respectively connected to the gate signal driving lines 41 . The gate signal driving line 41 is temporarily led out from the gate connection terminal 22 in a direction away from the output terminal 13 . In addition, after the gate signal driving line 41 is led out from the gate connection terminal 22 in a direction away from the output terminal 13 in this manner, it proceeds toward the left and right outer sides, and then is wired in such a manner that it proceeds toward the output terminal 13 . The gate signal driving line 41 is finally connected to the output terminal 13 (Gate Output) located on the left and right outer side of the output terminals 13 to which the plurality of source lines 31 and 32 are connected among the plurality of output terminals 13 .
以上，在本申請說明書中，為了表現本發明的內容，參照圖式對本發明的實施方式進行了說明。但是，本發明並不限定於上述實施方式，還包括本發明所屬技術領域中具有通常知識者基於本申請說明書所記載的事項而顯而易見的變更方式、改良方式。As mentioned above, in the specification of this application, in order to express the content of this invention, the embodiment of this invention was described with reference to the drawings. However, the present invention is not limited to the above-described embodiments, and includes modifications and improvements that are obvious to a person of ordinary skill in the technical field to which the present invention belongs based on the matters described in the specification of this application.
10:COF模組（資料輸出裝置） 1:膜 12:輸入端子 13:輸出端子 20:驅動晶片 21:源極連接端子 22:閘極連接端子 23:輸入連接端子 31:第一源極線組（訊號線） 32:第二源極線組（訊號線） 41:閘極訊號驅動線（訊號線） 51:輸入線 10:COF module (data output device) 1: membrane 12:Input terminal 13:Output terminal 20: Driver chip 21: Source connection terminal 22: Gate connection terminal 23:Input connection terminal 31: First source line group (signal line) 32: Second source line group (signal line) 41: Gate signal drive line (signal line) 51:Input line
圖1（先前技術）是表示時序控制器和源極驅動器分離的顯示模組的整體構成之方塊圖。 圖2（先前技術）是表示時序控制器和源極驅動器一體化的顯示模組的整體構成之方塊圖。 圖3（先前技術）是表示時序控制器和源極驅動器一體化的顯示模組的整體構成之方塊圖。 圖4（先前技術）是表示在時序控制器和源極驅動器分離的顯示模組中，顯示面板的有效區域和邊框區域之圖。 圖5（先前技術）是表示在時序控制器和源極驅動器一體化的顯示模組中，顯示面板的有效區域和邊框區域之圖。 圖6（先前技術）是表示顯示面板的源極線的以往的配線方式之圖。 圖7（先前技術）是從圖6所示的顯示面板的中央放大了左側一半之圖，是用於說明在以往的配線方式中如何求出邊框區域的尺寸之圖。 圖8（先前技術）是用於表示具有多通道源極驅動器輸出的驅動晶片的COF安裝的構成之圖。 圖9（先前技術）是用於表示利用了具有2層配線構造的膜的COF安裝的構成之圖。 圖10（本發明）是表示本發明的一個實施方式之圖。 圖11（本發明）是將圖10的一部分放大之圖。 FIG. 1 (prior art) is a block diagram showing the overall structure of a display module in which a timing controller and a source driver are separated. FIG. 2 (prior art) is a block diagram showing the overall structure of a display module in which a timing controller and a source driver are integrated. FIG. 3 (prior art) is a block diagram showing the overall structure of a display module in which a timing controller and a source driver are integrated. FIG. 4 (prior art) is a diagram showing the effective area and frame area of the display panel in a display module in which the timing controller and the source driver are separated. FIG. 5 (prior art) is a diagram showing the effective area and frame area of the display panel in a display module in which a timing controller and a source driver are integrated. FIG. 6 (prior art) is a diagram showing a conventional wiring method of source lines of a display panel. FIG. 7 (prior art) is an enlarged view of the left half of the display panel shown in FIG. 6 from the center, and is a view for explaining how to determine the size of the frame area in the conventional wiring method. FIG. 8 (prior art) is a diagram showing the structure of a COF mounting of a driver chip having multi-channel source driver outputs. FIG. 9 (prior art) is a diagram showing the structure of COF mounting using a film having a two-layer wiring structure. FIG. 10 (present invention) is a diagram showing an embodiment of the present invention. FIG. 11 (present invention) is an enlarged view of a part of FIG. 10 .
10:COF模組(資料輸出裝置) 10:COF module (data output device)
11:膜 11: Membrane
12:輸入端子 12:Input terminal
13:輸出端子 13:Output terminal
20:驅動晶片 20: Driver chip
21:源極連接端子 21: Source connection terminal
22:閘極連接端子 22: Gate connection terminal
23:輸入連接端子 23:Input connection terminal
31:第一源極線組(訊號線) 31: First source line group (signal line)
32:第二源極線組(訊號線) 32: Second source line group (signal line)
41:閘極訊號驅動線(訊號線) 41: Gate signal drive line (signal line)
51:輸入線 51:Input line
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Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3285168B2 (en) * | 1993-08-06 | 2002-05-27 | シャープ株式会社 | Display device mounting structure and mounting method |
| JPH08313925A (en) * | 1995-05-18 | 1996-11-29 | Citizen Watch Co Ltd | Semiconductor integrated circuit |
| JP3696512B2 (en) * | 2001-02-13 | 2005-09-21 | シャープ株式会社 | Display element driving device and display device using the same |
| JP4271435B2 (en) * | 2002-12-09 | 2009-06-03 | シャープ株式会社 | Semiconductor device |
| JP4103703B2 (en) | 2003-07-11 | 2008-06-18 | 三菱電機株式会社 | TFT display device |
| KR100632257B1 (en) * | 2004-11-09 | 2006-10-11 | 삼성전자주식회사 | Wiring pattern structure of tap package for driving liquid crystal display |
| KR101147990B1 (en) * | 2005-03-29 | 2012-05-24 | 엘지디스플레이 주식회사 | plate with IC pad |
| KR100723492B1 (en) * | 2005-07-18 | 2007-06-04 | 삼성전자주식회사 | Display driver integrated circuit device, film package and module including them |
| KR101082893B1 (en) * | 2005-08-24 | 2011-11-11 | 삼성전자주식회사 | Array substrate and display apparatus hving the same |
| KR101217083B1 (en) * | 2006-01-13 | 2012-12-31 | 삼성디스플레이 주식회사 | Flexible printed circuit board and, display unit and display apparatus having the board |
| JP5226070B2 (en) * | 2008-06-25 | 2013-07-03 | シャープ株式会社 | Wiring substrate and liquid crystal display device |
| KR101535223B1 (en) * | 2008-08-18 | 2015-07-09 | 삼성전자주식회사 | Tape wiring substrate, chip on film package and device assembly including the same |
| KR101030990B1 (en) * | 2008-12-31 | 2011-04-22 | 삼성에스디아이 주식회사 | Semiconductor package and plasma display device having the same |
| KR101680115B1 (en) * | 2010-02-26 | 2016-11-29 | 삼성전자 주식회사 | Semicoductor chip, film and TAB package comprising the chip and film |
| JP2012242698A (en) * | 2011-05-20 | 2012-12-10 | Panasonic Corp | Drive unit and display panel module |
| JP5940679B2 (en) * | 2012-11-16 | 2016-06-29 | シャープ株式会社 | Drive module, display device, and multi-display device |
| JP6182928B2 (en) * | 2013-03-27 | 2017-08-23 | セイコーエプソン株式会社 | Semiconductor device |
| JP5739554B2 (en) * | 2014-01-29 | 2015-06-24 | 株式会社ワンダーフューチャーコーポレーション | Touch panel, touch panel manufacturing method, and touch panel integrated display device |
| US10147328B2 (en) | 2015-10-22 | 2018-12-04 | Thales USA, Inc. | Ground based navigation aid equipment for aircraft safety |
| KR102458382B1 (en) * | 2015-11-19 | 2022-10-26 | 삼성디스플레이 주식회사 | Display apparatus and method of manufacturing the same |
| JP6152464B1 (en) * | 2016-11-05 | 2017-06-21 | 株式会社セレブレクス | Narrow frame display module and data output device |
| KR102322539B1 (en) * | 2018-02-07 | 2021-11-04 | 삼성전자주식회사 | Semiconductor package and display apparatus comprising the same |
| KR20210024339A (en) * | 2019-08-22 | 2021-03-05 | 삼성디스플레이 주식회사 | Display device |
| CN113785353B (en) * | 2020-04-10 | 2022-10-18 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN112037649A (en) * | 2020-08-12 | 2020-12-04 | 上海中航光电子有限公司 | Display panel and display device |
| CN112150933A (en) * | 2020-10-28 | 2020-12-29 | 天马微电子股份有限公司 | Display panel and display device |
-
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| TWI794134B (en) | 2023-02-21 |
| JP2023142909A (en) | 2023-10-06 |
| CN115410540A (en) | 2022-11-29 |
| KR102450037B1 (en) | 2022-10-06 |
| JP7108350B1 (en) | 2022-07-28 |
| CN115410540B (en) | 2023-03-28 |
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