TW202331855A - 用於嵌入式晶片的封裝製程 - Google Patents

用於嵌入式晶片的封裝製程 Download PDF

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TW202331855A
TW202331855A TW111102463A TW111102463A TW202331855A TW 202331855 A TW202331855 A TW 202331855A TW 111102463 A TW111102463 A TW 111102463A TW 111102463 A TW111102463 A TW 111102463A TW 202331855 A TW202331855 A TW 202331855A
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insulating adhesive
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李家銘
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大陸商廣東則成科技有限公司
李家銘
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Priority to US17/716,184 priority patent/US20230230929A1/en
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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Abstract

本發明提供一種用於嵌入式晶片的封裝製程，包括以下步驟：（1）在一電路基板表面貼裝至少一IC晶片，IC晶片具有至少一裸露的接腳；（2）在電路基板表面貼附一背膠銅箔，其中背膠銅箔具有一銅箔層及一B階段的絕緣膠層，絕緣膠層塗布於銅箔層上，絕緣膠層中不具有玻璃纖維，接腳接觸絕緣膠層但不接觸銅箔層，絕緣膠層覆蓋IC晶片，銅箔層具有至少一對應於接腳的孔位銅箔區，絕緣膠層具有至少一對應於接腳的孔位絕緣膠區；（3）移除孔位銅箔區；（4）利用蝕刻液移除孔位絕緣膠區；（5）將絕緣膠層完全固化。

Description

用於嵌入式晶片的封裝製程
本發明是關於一種嵌入式晶片封裝技術。
有別於許多貼裝於電路板表面的IC晶片，嵌入式晶片封裝則是將IC晶片內嵌於電路板的內層中。為了要與內嵌的IC晶片的接腳形成電連接，需要在與接腳對應的位置形成通孔，並在通孔內鍍銅。現有技術中，這些通孔是以雷射雕刻方式形成，過程中IC晶片的一部份受到雷射照射而容易受到傷害，實有改良的必要。
有鑑於此，本發明之主要目的在於提供一種能避免IC晶片被雷射照射的內嵌式晶片封裝技術。
為了達成上述及其他目的，本發明提供一種用於嵌入式晶片的封裝製程，包括以下步驟： （1）在一電路基板表面貼裝至少一IC晶片，該IC晶片具有至少一裸露的接腳； （2）在該電路基板表面貼附一背膠銅箔，其中該背膠銅箔具有一銅箔層及一B階段的絕緣膠層，該絕緣膠層塗布於該銅箔層上，該絕緣膠層中不具有玻璃纖維，該接腳接觸該絕緣膠層但不接觸該銅箔層，該絕緣膠層覆蓋該IC晶片，該銅箔層具有至少一對應於所述接腳的孔位銅箔區，該絕緣膠層具有至少一對應於所述接腳的孔位絕緣膠區； （3）移除該孔位銅箔區； （4）利用蝕刻液移除該孔位絕緣膠區，從而在該背膠銅箔上形成至少一對應於所述接腳的通孔；以及 （5）將該絕緣膠層完全固化。
由於本發明使用的絕緣膠層並不具有玻璃纖維，並且剛貼附於電路基板時還處於B階段，從而可通過蝕刻液來將孔位絕緣膠區移除，無須使用雷射雕刻，進而避免IC晶片被雷射照射而容易損壞的問題。
本發明揭示一種用於嵌入式晶片的封裝製程，以下通過第1至10圖說明本發明其中一實施例的製程，其中的電路設計是出於說明的目的而簡化，但實際電路設計並不以此為限。
本實施例的嵌入式晶片封裝結構是由包括以下步驟的製程所製作：
步驟（1）：
請參考第1、2圖，在一電路基板10表面貼裝至少一IC晶片20，IC晶片20具有至少一裸露的接腳21，該裸露的接腳21未直接接觸該電路基板10表面，IC晶片20例如是貼裝於電路基板10表面的介質層11上，但並不以此為限。所述電力基板10可用任何適當的方法依需求製作，IC晶片20例如可為有源元件、無源元件、MEMS或其他晶片。
步驟（2）：
請參考第3、4圖，在電路基板10表面再貼附一背膠銅箔30，其中，背膠銅箔30具有一銅箔層31及一B階段（B-Stage）的絕緣膠層32，絕緣膠層32塗布於銅箔層31上，絕緣膠層32中不具有玻璃纖維，接腳21接觸絕緣膠層32但不接觸銅箔層31，絕緣膠層32覆蓋並包覆IC晶片20；絕緣膠層32例如可為環氧樹脂類、壓克力類、聚醯亞胺類的光及/或熱可固化樹脂，所述B階段是指所述可固化樹脂並未完全固化，但已被乾燥而具有指觸乾燥性的狀態；根據其光固化及/或熱固化的特性，B階段的樹脂可在特定光波照射下及/或特定固化溫度下被完全固化至C階段；本發明中，絕緣膠層32在步驟（5）前都維持在B階段。其中，銅箔層31具有至少一對應於所述接腳21的孔位銅箔區311，該絕緣膠層32具有至少一對應於所述接腳21的孔位絕緣膠區321，孔位絕緣膠區321被孔位銅箔區311覆蓋。
步驟（3）：
請參考第5圖，移除孔位銅箔區311，從而裸露孔位絕緣膠區321。在可能的實施方式中，孔位銅箔區311是通過貼附光阻、曝光、顯影、蝕刻等常規方式移除，但並不以此為限，例如可以雷射雕刻方式移除。
步驟（4）：
請參考第6圖，利用蝕刻液移除孔位絕緣膠區321，從而在背膠銅箔30上形成至少一對應於所述接腳21的通孔33；所述蝕刻液是指可將與其接觸的B階段絕緣膠層移除的藥劑。孔位絕緣膠區321被移除後，可以裸露所述接腳21。值得一提的是，在步驟（3）、（4）中，接腳21及IC晶片20的其他部分不會暴露於雷射，而可避免損壞。
步驟（5）：
根據絕緣膠層32的光固化及/或熱固化的特性，B階段的絕緣膠層32可在特定光波照射下及/或特定固化溫度下被完全固化，其外觀仍維持第6圖所示的外觀。
步驟（7）：
如第7圖所示，通過化學鍍方式在銅箔層31上及該通孔33中形成化鍍銅層40。
步驟（8）：
如第8圖所示，通過電鍍方式在化鍍銅層40上形成電鍍銅層50。
步驟（9）：
對銅箔層31、化鍍銅層40及電鍍銅層50以及進行圖形化處理，形成如第9圖所示的狀態。其中，電路基板可以形成其他盲孔或貫孔，這些盲孔與貫孔的製作可以但不限於在步驟（3）、（4）中一併進行，在本案圖式中並未特別表示這些盲孔與貫孔的製作流程。
一個嵌入式晶片封裝結構1可在上述步驟後完成，其具有一電路基板10、至少一IC晶片20、一完全固化的絕緣膠層32、一銅箔層31、至少一形成於該絕緣膠層32及銅箔層31的通孔33、一化鍍銅層40及一電鍍銅層50，IC晶片20貼裝於該電路基板10表面，IC晶片20具有至少一裸露的接腳21，絕緣膠層32中不具有玻璃纖維，接腳21接觸絕緣膠層32但不接觸銅箔層31，絕緣膠層32覆蓋並包覆IC晶片20，銅箔層31覆蓋絕緣膠層32，通孔33分別對應於接腳21，化鍍銅層40電連接於接腳21及銅箔層31間，電鍍銅層50形成於化鍍銅層40上。其中，嵌入式晶片封裝結構1可再依設計需求進行其他後續處理。
1:嵌入式晶片封裝結構 10:電路基板 11:介質層 20:IC晶片 21:接腳 30:背膠銅箔 31:銅箔層 311:孔位銅箔區 32:絕緣膠層 321:孔位絕緣膠區 33:通孔 40:化鍍銅層 50:電鍍銅層
第1至10圖是本發明其中一實施例的製程示意圖。
1:嵌入式晶片封裝結構
10:電路基板
11:介質層
20:IC晶片
21:接腳
31:銅箔層
32:絕緣膠層
33:通孔
40:化鍍銅層
50:電鍍銅層

Claims (3)

  1. 一種用於嵌入式晶片的封裝製程，包括以下步驟： （1）在一電路基板表面貼裝至少一IC晶片，該IC晶片具有至少一裸露的接腳； （2）在該電路基板表面貼附一背膠銅箔，其中該背膠銅箔具有一銅箔層及一B階段（B-Stage）的絕緣膠層，該絕緣膠層塗布於該銅箔層上，該絕緣膠層中不具有玻璃纖維，該接腳接觸該絕緣膠層但不接觸該銅箔層，該絕緣膠層覆蓋該IC晶片，該銅箔層具有至少一對應於所述接腳的孔位銅箔區，該絕緣膠層具有至少一對應於所述接腳的孔位絕緣膠區； （3）移除該孔位銅箔區； （4）利用蝕刻液移除該孔位絕緣膠區，從而在該背膠銅箔上形成至少一對應於所述接腳的通孔；以及 （5）將該絕緣膠層完全固化。
  2. 如請求項1所述的軟硬複合板的製程，其中在該步驟（5）後更包括以下步驟： （6）通過化學鍍方式在該銅箔層上及該通孔中形成化鍍銅層；以及 （7）通過電鍍方式在該化鍍銅層上形成電鍍銅層。
  3. 如請求項2所述的軟硬複合板的製程，其中在該步驟（7）後更包括以下步驟： （8）對該銅箔層、該化鍍銅層及該電鍍銅層進行圖形化處理。
TW111102463A 2022-01-20 2022-01-20 用於嵌入式晶片的封裝製程 TWI808618B (zh)

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TW111102463A TWI808618B (zh) 2022-01-20 2022-01-20 用於嵌入式晶片的封裝製程
CN202210209020.4A CN116525458A (zh) 2022-01-20 2022-03-03 用于嵌入式芯片的封装制程
US17/716,184 US20230230929A1 (en) 2022-01-20 2022-04-08 Packaging process for embedded chips

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