TW201937558A - Method for manufacturing semiconductor epitaxial wafer which can have higher gettering capability even under the same conditions of cluster ion implantation - Google Patents

Method for manufacturing semiconductor epitaxial wafer which can have higher gettering capability even under the same conditions of cluster ion implantation Download PDF

Info

Publication number
TW201937558A
TW201937558A TW107138317A TW107138317A TW201937558A TW 201937558 A TW201937558 A TW 201937558A TW 107138317 A TW107138317 A TW 107138317A TW 107138317 A TW107138317 A TW 107138317A TW 201937558 A TW201937558 A TW 201937558A
Authority
TW
Taiwan
Prior art keywords
wafer
semiconductor
epitaxial
defect
heat treatment
Prior art date
Application number
TW107138317A
Other languages
Chinese (zh)
Other versions
TWI708279B (en
Inventor
廣瀬諒
Original Assignee
日商Ｓｕｍｃｏ股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商Ｓｕｍｃｏ股份有限公司 filed Critical 日商Ｓｕｍｃｏ股份有限公司
Publication of TW201937558A publication Critical patent/TW201937558A/en
Application granted granted Critical
Publication of TWI708279B publication Critical patent/TWI708279B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26566—Bombardment with radiation with high-energy radiation producing ion implantation of a cluster, e.g. using a gas cluster ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The present invention provides a method for manufacturing a semiconductor epitaxial wafer for which gettering capability is enhanced even under the same conditions of cluster ion implantation. The method for manufacturing a semiconductor epitaxial wafer of this invention comprises: a first step of injecting the multi-element cluster ions containing three elements of carbon, hydrogen, and oxygen as constituent elements to the surface of a semiconductor wafer, such that a modified layer is formed in which the constituent elements of the multi-element cluster ions are solid-solved in a surface layer portion of the semiconductor wafer; a second step, performed after the first step, of performing a defect-forming heat treatment to increase the defect density of the black spot defects formed in the modified layer; and a third step, immediately following the second step, of forming an epitaxial layer on the modified layer of the semiconductor wafer.

Description

半導體磊晶晶圓的製造方法Manufacturing method of semiconductor epitaxial wafer

本發明是有關於一種半導體磊晶晶圓的製造方法。本發明特別是有關於一種發揮更高的吸除（gettering）能力的半導體磊晶晶圓的製造方法。The invention relates to a method for manufacturing a semiconductor epitaxial wafer. The present invention particularly relates to a method for manufacturing a semiconductor epitaxial wafer that exhibits a higher gettering capability.

使半導體器件（device）的特性劣化的主要原因可列舉金屬污染。例如於背面照射型固體攝像元件中，混入至成為該元件的基板的半導體磊晶晶圓中的金屬成為使固體攝像元件的暗電流增加的主要原因，產生被稱為白痕缺陷的缺陷。背面照射型固體攝像元件藉由將配線層等配置於較感測器部更靠下層的位置，而將來自外部的光直接取入至感測器中，於暗處等亦可拍攝更清晰的圖像或動態影像，因此近年來被廣泛地用於數位視訊攝影機（digital video camera）或智慧型電話（smartphone）等行動電話中。因此，期望極力減少白痕缺陷。A major cause of deterioration of the characteristics of a semiconductor device is metal contamination. For example, in a back-illuminated solid-state imaging element, metal mixed into a semiconductor epitaxial wafer that becomes the substrate of the element becomes a cause of increasing the dark current of the solid-state imaging element, and a defect called a white mark defect occurs. The back-illuminated solid-state imaging element can arrange the wiring layer and the like at a lower level than the sensor section, and directly take in light from the outside into the sensor, and can shoot more clearly in dark places. Images or motion pictures have been widely used in recent years in mobile phones such as digital video cameras and smartphones. Therefore, it is desirable to minimize white mark defects.

半導體元件基板中的金屬混入主要是於半導體磊晶晶圓的製造步驟及固體攝像元件的製造步驟（器件製造步驟）中產生。認為前者的半導體磊晶晶圓的製造步驟中的金屬污染是由源自磊晶成長爐的構成材料的重金屬顆粒所致，或者由於使用氯系氣體作為磊晶成長時的爐內氣體，因此是由其配管材料發生金屬腐蝕而產生的重金屬顆粒所致等。近年來，藉由將磊晶成長爐的構成材料更換成耐腐蝕性優異的材料等而於某種程度上改善了該些金屬污染，但並不充分。另一方面，於後者的固體攝像元件的製造步驟中，於離子注入、擴散及氧化熱處理等各處理中，半導體磊晶晶圓的重金屬污染令人擔憂。The metal in the semiconductor element substrate is mainly produced in the manufacturing steps of the semiconductor epitaxial wafer and the manufacturing steps (device manufacturing steps) of the solid-state imaging element. It is considered that the metal contamination in the manufacturing process of the former semiconductor epitaxial wafer is caused by heavy metal particles originating from the constituent materials of the epitaxial growth furnace, or because a chlorine-based gas is used as the furnace gas during epitaxial growth, so it is It is caused by heavy metal particles generated by metal corrosion of piping materials. In recent years, these metal contaminations have been improved to some extent by replacing the constituent materials of the epitaxial growth furnace with materials having excellent corrosion resistance, etc., but this is not sufficient. On the other hand, in the manufacturing steps of the latter solid-state imaging device, the heavy metal contamination of semiconductor epitaxial wafers is worrying in various processes such as ion implantation, diffusion, and oxidation heat treatment.

因此，通常藉由在半導體磊晶晶圓上形成用以捕獲金屬的吸除層，來避免對半導體磊晶晶圓的金屬污染。Therefore, metal contamination of semiconductor epitaxial wafers is usually avoided by forming a gettering layer on the semiconductor epitaxial wafers to capture metal.

此處，作為形成吸除層的技術，存在於形成磊晶層之前照射簇離子（cluster ion）的技術。專利文獻1中揭示有於半導體磊晶晶圓的製造方法中，注入包含碳、氫及氧作為構成元素的簇離子的技術。而且，專利文獻1中亦揭示有：藉由注入包含碳、氫及氧此三種元素的簇離子，而形成推斷為由晶格隙矽引起的比較大的尺寸的黑點狀缺陷（專利文獻1中的第2黑點狀缺陷）。根據專利文獻1的實驗結果而暗示出該黑點狀缺陷作為強力的吸除點（gettering site）發揮功能。
[現有技術文獻]
[專利文獻]Here, as a technique for forming the gettering layer, there is a technique for irradiating cluster ions before forming the epitaxial layer. Patent Document 1 discloses a technique for implanting cluster ions containing carbon, hydrogen, and oxygen as constituent elements in a method of manufacturing a semiconductor epitaxial wafer. In addition, Patent Document 1 also discloses that by implanting cluster ions containing three elements of carbon, hydrogen, and oxygen, black dot-like defects that are presumed to be caused by lattice gap silicon are formed (Patent Document 1). 2nd black spot-like defect in). According to the experimental results of Patent Document 1, it is suggested that the black dot-like defect functions as a powerful gettering site.
[Prior Art Literature]
[Patent Literature]

[專利文獻1]日本專利特開2017-157613號公報[Patent Document 1] Japanese Patent Laid-Open No. 2017-157613

[發明所欲解決之課題]
藉由使用專利文獻1中所揭示的簇離子注入技術，可獲得具有極其優異的吸除能力的半導體磊晶晶圓。但是，利用簇離子注入的吸除點的形成機制及其特性雖於某程度上逐步明瞭，但仍處於研究過程中。特別是關於除了碳及氫以外亦進而包含另外一種以上的元素作為簇離子的構成元素的多元素簇離子，未解明的方面多。以下，於本說明書中，在簇離子的構成元素包含三種以上的元素的情況下，稱為「多元素簇離子」。[Problems to be Solved by the Invention]
By using the cluster ion implantation technology disclosed in Patent Document 1, a semiconductor epitaxial wafer having extremely excellent gettering ability can be obtained. However, although the formation mechanism and characteristics of the gettering point by cluster ion implantation are gradually understood to some extent, it is still in the research process. In particular, there are many unexplained aspects of a multi-element cluster ion including, in addition to carbon and hydrogen, one or more other elements as constituent elements of the cluster ion. Hereinafter, in this specification, when a constituent element of a cluster ion includes three or more elements, it is referred to as a "multi-element cluster ion".

此處，為了進一步提高專利文獻1中的利用改質層的吸除能力，例如有效的是增多簇離子的劑量。但是，若過於增多劑量，則存在於改質層上所形成的磊晶層中產生大量的磊晶缺陷的情況。如此，於藉由增加劑量來改善吸除能力的方面存在極限。Here, in order to further improve the gettering ability using the modified layer in Patent Document 1, it is effective to increase the dose of cluster ions, for example. However, if the dose is excessively increased, a large number of epitaxial defects may be generated in the epitaxial layer formed on the modified layer. As such, there is a limit in terms of improving the suction ability by increasing the dose.

因此，就簇離子注入條件以外的觀點而言，期待確立用以進一步提高吸除能力的新的方法。Therefore, from a viewpoint other than the cluster ion implantation conditions, it is expected to establish a new method for further improving the gettering ability.

因此，本發明的目的在於提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。
[解決課題之手段]Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor epitaxial wafer that can have a higher gettering ability even if the cluster ion implantation conditions are the same.
[Means for solving problems]

為了解決所述課題，本發明者進行了努力研究。而且，本發明者對如下情況進行了研究：代替簇離子注入條件而調整磊晶成長條件，藉此能否提高吸除能力。此處，使用圖1說明伴隨磊晶成長處理的熱處理順序（sequence）的通常的概念圖。該熱處理順序可大致區分為如下三個過程：（i）將半導體晶圓投入至磊晶成長爐內後，直至到達磊晶成長溫度為止的升溫過程；（ii）於半導體晶圓表面上使磊晶層成長的磊晶成長過程；（iii）形成磊晶層後，直至自磊晶成長爐取出所獲得的半導體磊晶晶圓為止的降溫過程。In order to solve the problems, the present inventors have made intensive studies. Furthermore, the present inventors have studied whether the epitaxial growth conditions can be adjusted instead of the cluster ion implantation conditions, thereby improving the gettering ability. Here, the general conceptual diagram of the heat treatment sequence accompanying an epitaxial growth process is demonstrated using FIG. 1. FIG. The heat treatment sequence can be roughly divided into the following three processes: (i) the temperature rising process after the semiconductor wafer is put into the epitaxial growth furnace until the epitaxial growth temperature is reached; (ii) the epitaxial growth is performed on the surface of the semiconductor wafer The epitaxial growth process of crystal layer growth; (iii) the cooling process after the epitaxial layer is formed until the semiconductor epitaxial wafer obtained from the epitaxial growth furnace is taken out.

本發明者進行了努力研究，結果得知成為吸除點的黑點狀缺陷的生成數量大幅依存於所述（i）升溫過程。而且，本發明者得知：藉由進行兼作為用以增大黑點狀缺陷的缺陷密度的缺陷形成熱處理的升溫過程，即便簇離子注入條件相同，亦可進一步提高吸除能力。本發明是基於所述見解而完成，其主旨構成如下所述。The present inventors conducted diligent research, and as a result, it was found that the number of generation of black spot-like defects that become absorption points largely depends on the (i) heating process. In addition, the present inventors have learned that by performing a temperature increasing process of the defect formation heat treatment that also serves to increase the density of black dot defects, even if the cluster ion implantation conditions are the same, the gettering ability can be further improved. This invention is completed based on the said knowledge, and the summary structure is as follows.

（1）一種半導體磊晶晶圓的製造方法，其特徵在於包括：
第1步驟，對半導體晶圓的表面注入包含碳、氫及氧此三種元素作為構成元素的多元素簇離子，於該半導體晶圓的表層部形成所述多元素簇離子的構成元素固溶而成的改質層；
第2步驟，於該第1步驟之後，進行用以增大所述改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理；以及
第3步驟，緊接該第2步驟，於所述半導體晶圓的改質層上形成磊晶層。(1) A method for manufacturing a semiconductor epitaxial wafer, comprising:
In a first step, a multi-element cluster ion containing three elements of carbon, hydrogen, and oxygen as constituent elements is implanted on the surface of a semiconductor wafer, and the constituent elements forming the multi-element cluster ion are solid-solved on the surface layer portion of the semiconductor wafer. Reformed layer
A second step, after the first step, performing a defect formation heat treatment for increasing a defect density of black dot-like defects formed in the modified layer; and a third step, following the second step, An epitaxial layer is formed on the modified layer of the semiconductor wafer.

（2）如所述（1）所記載的半導體磊晶晶圓的製造方法，其中所述第2步驟中的所述缺陷形成熱處理的熱處理條件中，於小於800℃的第1溫度區域保持所述半導體晶圓的第1保持時間為0秒以上且45秒以下，且自第1溫度區域升溫後的、於800℃以上且小於1000℃的第2溫度區域保持所述半導體晶圓的第2保持時間為30秒以上。(2) The method for manufacturing a semiconductor epitaxial wafer according to (1), wherein the heat treatment conditions of the defect formation heat treatment in the second step are maintained in a first temperature region of less than 800 ° C. The first holding time of the semiconductor wafer is 0 seconds or more and 45 seconds or less, and the second holding time of the semiconductor wafer in the second temperature range of 800 ° C or higher and less than 1000 ° C after the temperature rise in the first temperature range is maintained. The holding time is more than 30 seconds.

（3）如所述（1）或（2）所記載的半導體磊晶晶圓的製造方法，其中所述多元素簇離子的構成元素由碳、氫及氧此三種元素所組成。(3) The method for manufacturing a semiconductor epitaxial wafer according to (1) or (2), wherein the constituent elements of the multi-element cluster ion are composed of three elements: carbon, hydrogen, and oxygen.

（4）如所述（1）至（3）中任一項所記載的半導體磊晶晶圓的製造方法，其中所述半導體晶圓為矽晶圓。
[發明的效果](4) The method for manufacturing a semiconductor epitaxial wafer according to any one of (1) to (3), wherein the semiconductor wafer is a silicon wafer.
[Effect of the invention]

根據本發明，可提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。According to the present invention, it is possible to provide a method for manufacturing a semiconductor epitaxial wafer that can have a higher gettering ability even if the cluster ion implantation conditions are the same.

於實施形態的詳細說明之前，首先對完成本發明的實驗（參考實驗例1、參考實驗例2）進行說明。Prior to the detailed description of the embodiment, the experiments (refer to Experimental Example 1 and Reference Experimental Example 2) for completing the present invention will be described first.

[參考實驗例1]
準備由CZ單晶矽錠獲得的矽晶圓（直徑：300 mm，厚度：725 μm，摻雜劑種類：磷，電阻率：10 Ω·cm）。繼而，使用簇離子產生裝置（日新離子機器公司製造，型號：克拉麗絲（CLARIS）（註冊商標）），將包含使二乙基醚（C4 H10 O）簇離子化而成的CH3 O的多元素簇離子以加速電壓80 keV/Cluster的注入條件注入至矽晶圓的表面。另外，將該簇離子的劑量設為1.0×1015 cluster/cm2 。[Reference Experimental Example 1]
A silicon wafer (diameter: 300 mm, thickness: 725 μm, dopant type: phosphorus, resistivity: 10 Ω · cm) obtained from a CZ single crystal silicon ingot was prepared. Next, using a cluster ion generator (manufactured by Nisshin Ion Machinery Co., Ltd., model: CLARIS (registered trademark)), CH containing ionized diethyl ether (C 4 H 10 O) clusters was ionized. Multi-element cluster ions of 3 O were implanted on the surface of the silicon wafer under an implantation condition of an acceleration voltage of 80 keV / Cluster. The dose of this cluster ion was 1.0 × 10 15 cluster / cm 2 .

其次，將所述矽晶圓搬送至高速熱處理裝置（海索爾（hisol）公司製造，型號艾庫薩摩（AccuThermo）Aw610）內。而且，為了進行模擬1100℃、300秒的磊晶成長的熱處理（以下，模擬成長熱處理），而於氮氣氣體環境下，以如下條件進行熱處理。
爐內投入溫度：500℃
直至模擬成長溫度為止的升溫速率：60℃/sNext, the silicon wafer was transferred into a high-speed heat treatment apparatus (manufactured by hisol company, model AccuThermo Aw610). In order to perform a heat treatment (hereinafter, a simulated growth heat treatment) that simulates epitaxial growth at 1100 ° C and 300 seconds, the heat treatment was performed under the following conditions in a nitrogen gas environment.
Furnace input temperature: 500 ℃
Heating rate up to the simulated growth temperature: 60 ° C / s

（樣品2～樣品4）
除了將樣品1中的升溫速率60℃/s變更為15℃/s、8℃/s、4℃/s以外，與樣品1同樣地分別製作樣品2～樣品4。(Sample 2 to Sample 4)
Samples 2 to 4 were prepared in the same manner as Sample 1 except that the temperature rise rate of Sample 1 was changed from 60 ° C / s to 15 ° C / s, 8 ° C / s, and 4 ° C / s.

對於樣品1～樣品4各樣品，取得進行模擬成長熱處理前後的TEM剖面。將結果示於圖2中。For each of samples 1 to 4, TEM cross sections were obtained before and after the simulated growth heat treatment. The results are shown in FIG. 2.

[參考實驗例2]
（樣品5）
以與樣品1相同的條件，將包含CH3 O的多元素簇離子注入至矽晶圓的表面。繼而，為了進行800℃、300秒的模擬成長熱處理，而與參考實驗例1同樣地將簇離子注入後的矽晶圓搬送至高速熱處理裝置（海索爾（hisol）公司製造）內，並且以如下條件進行熱處理。
爐內投入溫度：500℃
直至模擬成長溫度為止的升溫速率：8℃/s[Reference Experimental Example 2]
(Sample 5)
A multi-element cluster containing CH 3 O was ion-implanted onto the surface of the silicon wafer under the same conditions as in Sample 1. Next, in order to perform a simulated growth heat treatment at 800 ° C for 300 seconds, the silicon wafer after the cluster ion implantation was transferred to a high-speed heat treatment apparatus (manufactured by Hisol) in the same manner as in Reference Experimental Example 1. The heat treatment was performed under the following conditions.
Furnace input temperature: 500 ℃
Heating rate up to the simulated growth temperature: 8 ° C / s

（樣品6～樣品8）
除了將樣品5中的模擬成長熱處理的熱處理溫度800℃變更為900℃、1000℃、1100℃以外，與樣品5同樣地分別製作樣品6～樣品8。(Sample 6 to Sample 8)
Samples 6 to 8 were prepared in the same manner as Sample 5 except that the heat treatment temperature of the simulated growth heat treatment in Sample 5 was changed from 800 ° C to 900 ° C, 1000 ° C, and 1100 ° C.

對於樣品5～樣品8各樣品，取得進行模擬磊晶成長的熱處理後後的TEM剖面。將結果示於圖3中。For each of samples 5 to 8, a TEM cross section was obtained after heat treatment to simulate epitaxial growth. The results are shown in FIG. 3.

＜參考實驗例1、參考實驗例2的考察＞
首先，基於根據參考實驗例1的圖2，可確認到：於1100℃、300秒的模擬成長熱處理前，所形成的黑點狀缺陷的缺陷密度並不大幅依存於升溫速率。另一方面，於模擬成長熱處理後，黑點狀缺陷的缺陷密度雖均減少，但其減少量大幅依存於升溫速率。<Examination of Reference Experimental Example 1 and Reference Experimental Example 2>
First, based on FIG. 2 of Reference Experimental Example 1, it was confirmed that the defect density of the black dot-like defects formed before the simulated growth heat treatment at 1100 ° C. for 300 seconds does not largely depend on the heating rate. On the other hand, after the simulated growth heat treatment, although the defect densities of the black spot-shaped defects are all reduced, the decrease amount depends largely on the heating rate.

而且，基於根據參考實驗例2的圖3，可確認到：藉由800℃、900℃及1000℃的模擬成長熱處理而黑點狀缺陷的生成量比較大。In addition, based on FIG. 3 according to Reference Experimental Example 2, it was confirmed that the amount of black dot defects generated was relatively large by the simulated growth heat treatment at 800 ° C, 900 ° C, and 1000 ° C.

若綜合考慮以上結果，則認為是如下假設：經簇離子注入的矽晶圓若受到800℃以上且小於1000℃的熱處理，則黑點狀缺陷成長，另一方面，若小於800℃，則黑點狀缺陷種其自身消失，若受到1000℃以上的熱處理，則黑點狀缺陷分解。將基於該假設的熱處理順序示於圖4中。樣品1～樣品3中，小於800℃的黑點狀缺陷種消失的溫度帶的通過時間雖然比較短，但黑點狀缺陷成長的溫度帶的通過時間亦比較短。樣品4中，小於800℃的黑點狀缺陷種消失的溫度帶的通過時間雖然比較長，但若受到800℃以上且小於1000℃的熱處理，則黑點狀缺陷成長的時間亦長。因此推測，如圖2上段的TEM剖面照片般，於模擬成長熱處理前的狀態下，黑點狀缺陷的缺陷密度是以相同程度被觀察到。而且，如圖2下段的TEM剖面照片般，於模擬成長熱處理後，黑點狀缺陷的缺陷密度產生非偶然的差異。If the above results are taken into consideration, it is considered to be the following assumption: if the silicon wafer subjected to cluster ion implantation is subjected to a heat treatment of 800 ° C. or more and less than 1000 ° C., black spot defects grow; on the other hand, if it is less than 800 ° C., black The point-like defect species disappears by itself, and if subjected to a heat treatment of 1000 ° C. or higher, the black-point-like defect is decomposed. The heat treatment sequence based on this assumption is shown in FIG. 4. In samples 1 to 3, although the passage time of the temperature zone where the black spot-like defect species disappeared below 800 ° C was relatively short, the passage time of the temperature zone where the black spot-like defect grew was also short. In Sample 4, although the passage time of the temperature range where the black spot-like defect species less than 800 ° C disappeared is relatively long, if the heat treatment is performed at a temperature of 800 ° C or more and less than 1000 ° C, the black spot-like defect growth time is also long. Therefore, it is presumed that, as in the TEM cross-section photograph in the upper stage of FIG. 2, in a state before the simulated growth heat treatment, the defect density of black spot-like defects is observed to the same degree. Moreover, as shown in the TEM cross-section photograph in the lower part of FIG. 2, after the simulated growth heat treatment, the defect density of the black spot-shaped defects has a non-accidental difference.

因此，本發明者得知：藉由在形成磊晶層之前進行用以增大改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理，可提高吸除能力。Therefore, the present inventors have learned that by performing a defect formation heat treatment for increasing the density of black dot-like defects formed in the modified layer before forming the epitaxial layer, the gettering ability can be improved.

基於以上實驗結果，一邊參照所述圖4的熱處理順序及圖5中的（A）至（C）的表示製造流程的示意剖面圖，一邊對本發明的一實施形態的磊晶矽晶圓的雜質擴散舉動預測方法進行說明。再者，圖5中的（A）至（C）中，為了便於說明而與實際的厚度的比例不同，相對於半導體晶圓10而誇張地示出改質層18及磊晶層20的厚度。Based on the above experimental results, referring to the heat treatment sequence of FIG. 4 and the schematic cross-sectional views showing manufacturing processes in (A) to (C) of FIG. 5, impurities in an epitaxial silicon wafer according to an embodiment of the present invention are described. The diffusion behavior prediction method will be described. In addition, in (A) to (C) of FIG. 5, the ratio of the actual thickness to the thickness of the semiconductor wafer 10 is exaggerated relative to the semiconductor wafer 10 for the convenience of explanation. .

（半導體磊晶晶圓的製造方法）
依照本發明的一實施形態的半導體磊晶晶圓100的製造方法包括：第1步驟，對半導體晶圓10的表面10A注入包含三種元素以上的元素作為構成元素的多元素簇離子16，於該半導體晶圓10的表層部形成多元素簇離子16的構成元素固溶而成的改質層18（圖5中的（A）至（C）的步驟A、步驟B）；第2步驟，於該第1步驟之後，進行用以增大改質層18內所形成的黑點狀缺陷D的缺陷密度的缺陷形成熱處理；以及第3步驟，緊接該第2步驟，於半導體晶圓的改質層18上形成磊晶層（圖5中的（A）至（C）的步驟C）。此處，多元素簇離子16的構成元素包含碳、氫及氧。以下，為了簡略化，存在將包含碳、氫及氧作為構成元素的多元素簇離子簡稱為「CHO簇」的情況。CHO簇可包含碳、氫及氧以外的元素作為構成元素，亦可設為僅碳、氫及氧此三種元素。再者，圖5中的（A）至（C）的步驟C是該製造方法的結果所得的半導體磊晶晶圓100的示意剖面圖。磊晶層20成為用以製造背面照射型固體攝像元件等半導體元件的器件層。半導體晶圓10為矽晶圓，磊晶層20為矽磊晶層的磊晶矽晶圓為半導體磊晶晶圓100的較佳態樣之一。以下，依次對各步驟的詳細情況進行說明。(Manufacturing method of semiconductor epitaxial wafer)
A method for manufacturing a semiconductor epitaxial wafer 100 according to an embodiment of the present invention includes: a first step of implanting a multi-element cluster ion 16 including three or more elements as constituent elements on the surface 10A of the semiconductor wafer 10; The surface layer portion of the semiconductor wafer 10 forms a modified layer 18 formed by solid-solving the constituent elements of the multi-element cluster ion 16 (steps A and B of (A) to (C) in FIG. 5); the second step is in After the first step, a defect formation heat treatment for increasing the defect density of the black dot-like defects D formed in the modified layer 18 is performed; and the third step is followed by the second step, in the semiconductor wafer modification. An epitaxial layer is formed on the plasma layer 18 (steps C in (A) to (C) in FIG. 5). Here, the constituent elements of the multi-element cluster ion 16 include carbon, hydrogen, and oxygen. Hereinafter, for simplicity, a multi-element cluster ion containing carbon, hydrogen, and oxygen as constituent elements may be simply referred to as a "CHO cluster". The CHO cluster may contain elements other than carbon, hydrogen, and oxygen as constituent elements, or may be set to only three elements: carbon, hydrogen, and oxygen. Furthermore, step C in (A) to (C) in FIG. 5 is a schematic cross-sectional view of the semiconductor epitaxial wafer 100 obtained as a result of the manufacturing method. The epitaxial layer 20 is a device layer for manufacturing a semiconductor element such as a back-illuminated solid-state imaging element. The semiconductor wafer 10 is a silicon wafer, and the epitaxial silicon wafer with the epitaxial layer 20 being a silicon epitaxial layer is one of the preferred aspects of the semiconductor epitaxial wafer 100. Hereinafter, details of each step will be described in order.

＜第1步驟＞
本發明中的第1步驟（圖5中的（A）至（C）的步驟A、步驟B）中，如所述般，對半導體晶圓10的表面10A注入包含三種元素以上的元素作為構成元素的多元素簇離子16，於該半導體晶圓10的表層部形成多元素簇離子16的構成元素固溶而成的改質層18。第1步驟中所使用的多元素簇離子16如所述般包含碳、氫及氧作為構成元素。＜ First step ＞
In the first step (steps A and B of (A) to (C) in FIG. 5) of the present invention, as described above, the surface 10A of the semiconductor wafer 10 is implanted with an element containing three or more elements as a composition. The elemental multi-element cluster ion 16 forms a modified layer 18 formed by solid-solving constituent elements of the multi-element cluster ion 16 on the surface layer portion of the semiconductor wafer 10. The multi-element cluster ion 16 used in the first step includes carbon, hydrogen, and oxygen as constituent elements as described above.

＜＜半導體晶圓＞＞
作為半導體晶圓10，例如可列舉：包含矽、化合物半導體（GaAs、GaN、SiC）且於表面不具有磊晶層的塊狀的單晶晶圓。於製造背面照射型固體攝像元件的情況下，通常使用塊狀的單晶矽晶圓。另外，半導體晶圓10可使用利用線鋸（wire saw）等將藉由柴可斯基法（Czochralski，CZ法）或浮融區法（Floating Zone，FZ法）所育成的單晶矽錠切片（slice）所得的晶圓。另外，為了獲得更高的吸除能力，亦可於半導體晶圓10中添加碳及/或氮。進而，亦可於半導體晶圓10中添加規定濃度的任意的摻雜劑，製成所謂n+型或者p+型、或n-型或者p-型的基板。＜＜ Semiconductor wafer ＞＞
Examples of the semiconductor wafer 10 include a bulk single crystal wafer containing silicon, compound semiconductors (GaAs, GaN, and SiC) and having no epitaxial layer on the surface. When manufacturing a back-illuminated solid-state imaging device, a bulk single crystal silicon wafer is generally used. In addition, for the semiconductor wafer 10, a single crystal silicon ingot sliced by a Czochralski method (CZ method) or a floating zone method (FZ method) using a wire saw or the like can be used. (Slice) the resulting wafer. In addition, in order to obtain a higher gettering ability, carbon and / or nitrogen may be added to the semiconductor wafer 10. Furthermore, an arbitrary dopant having a predetermined concentration may be added to the semiconductor wafer 10 to form a so-called n + -type or p + -type, or n-type or p-type substrate.

另外，作為半導體晶圓10，亦可使用於塊狀半導體晶圓表面上形成有半導體磊晶層的磊晶晶圓。例如為於塊狀單晶矽晶圓的表面上形成有矽磊晶層的磊晶矽晶圓。該矽磊晶層可藉由化學氣相沈積（Chemical Vapor Deposition，CVD）法於通常的條件下形成。磊晶層較佳為將厚度設為0.1 μm～20 μm的範圍內，更佳為設為0.2 μm～10 μm的範圍內。In addition, as the semiconductor wafer 10, an epitaxial wafer in which a semiconductor epitaxial layer is formed on the surface of a bulk semiconductor wafer can also be used. For example, an epitaxial silicon wafer having a silicon epitaxial layer formed on the surface of a bulk single crystal silicon wafer. The silicon epitaxial layer can be formed by a chemical vapor deposition (CVD) method under normal conditions. The thickness of the epitaxial layer is preferably within a range of 0.1 μm to 20 μm, and more preferably within a range of 0.2 μm to 10 μm.

＜＜簇離子照射＞＞
此處，所謂本說明書中的「簇離子」，是藉由如下方式而獲得：利用電子碰撞法使電子與氣體狀分子相撞而使氣體狀分子的鍵結解離，藉此製成多種原子數的原子集合體，並產生碎片（fragment）而使該原子集合體離子化，並且進行經離子化的多種原子數的原子集合體的質量分離，進而抽出特定質量數的經離子化的原子集合體。即，簇離子為對多個原子集合成塊而成的簇賦予正電荷或負電荷並加以離子化而成者，可明確區別為碳離子等單原子離子、或一氧化碳離子等單分子離子。＜ cluster ion irradiation ＞
Here, the “cluster ions” in this specification are obtained by colliding electrons with gaseous molecules by the electron collision method to dissociate the bonds of the gaseous molecules, thereby producing a variety of atomic numbers. Atomic aggregates, and generate fragments to ionize the atomic aggregates, and perform mass separation of the ionized atomic aggregates with multiple atomic numbers, and then extract the ionized atomic aggregates with a specific mass. . That is, cluster ions are those obtained by adding a positive charge or a negative charge to a cluster formed by aggregating a plurality of atoms and ionizing them, and can be clearly distinguished as monoatomic ions such as carbon ions or monomolecular ions such as carbon monoxide ions.

於對作為半導體晶圓10的矽晶圓照射簇離子的情況下，若將簇離子照射至矽晶圓，則因其能量而瞬間成為1350℃～1400℃左右的高溫狀態，矽熔解。其後，矽經急速冷卻，簇離子的構成元素於矽晶圓中的表面附近固溶。即，所謂本說明書中的｢改質層｣，是指所照射的離子的構成元素固溶於矽晶圓表層部的結晶的晶格隙位置或置換位置而成的層。作為構成元素的一例，例如若著眼於碳，則由二次離子質譜分析法（Secondary Ion Mass Spectrometry，SIMS）所得的矽晶圓的深度方向上的碳的濃度分佈（profile）雖依存於簇離子的加速電壓及簇尺寸，但與單體離子的情況相比變尖銳（sharp），所照射的碳局部地存在的區域（即改質層）的厚度大致成為500 nm以下（例如50 nm～400 nm左右）。因此，於多元素簇離子16的構成元素包含碳等有助於吸除的元素的情況下，改質層18作為強力的吸除點發揮功能。When cluster ions are irradiated to the silicon wafer as the semiconductor wafer 10, if the cluster ions are irradiated to the silicon wafer, the energy will instantly become a high-temperature state of about 1350 ° C to 1400 ° C, and the silicon will melt. Thereafter, the silicon was rapidly cooled, and the constituent elements of the cluster ions were solid-dissolved near the surface in the silicon wafer. That is, the “modified layer” in the present specification refers to a layer in which the constituent elements of the ions to be irradiated are dissolved in the lattice gap positions or replacement positions of the crystals in the surface layer portion of the silicon wafer. As an example of the constituent elements, for example, when focusing on carbon, the concentration profile of carbon in the depth direction of a silicon wafer obtained by Secondary Ion Mass Spectrometry (SIMS) depends on cluster ions. Acceleration voltage and cluster size, but sharper than the case of monomer ions, and the thickness of the region where the irradiated carbon locally exists (ie, the reforming layer) is approximately 500 nm or less (for example, 50 nm to 400 nm or so). Therefore, when the constituent elements of the multi-element cluster ion 16 include an element that contributes to gettering such as carbon, the modified layer 18 functions as a strong gettering point.

於本實施形態中，所注入的多元素簇離子16為CHO簇，包含碳、氫及氧作為構成元素。晶格位置的碳原子的共價鍵半徑較矽單晶小而形成矽結晶晶格的收縮場（contraction field），因此吸引晶格隙的雜質的吸除能力變高。而且，認為藉由以CHO簇的形態注入碳及氧，並經過其後的伴隨磊晶成長的熱處理，而形成黑點狀缺陷D。再者，氫使矽磊晶層（磊晶層20）的點缺陷鈍化，且就有助於改善使用由本實施形態所得的半導體磊晶晶圓100來製成半導體器件時的器件特性的方面而言亦有利。In this embodiment, the implanted multi-element cluster ion 16 is a CHO cluster, and contains carbon, hydrogen, and oxygen as constituent elements. The covalent bond radius of the carbon atoms at the lattice position is smaller than that of a silicon single crystal and forms a contraction field of the silicon crystal lattice. Therefore, the absorption ability of impurities that attract the lattice gap becomes higher. In addition, it is thought that black dot-like defects D are formed by injecting carbon and oxygen in the form of CHO clusters and subjecting to subsequent heat treatment accompanied with epitaxial growth. Furthermore, the passivation of the point defects of the silicon epitaxial layer (epitaxial layer 20) by hydrogen contributes to the improvement of the device characteristics when the semiconductor epitaxial wafer 100 obtained in this embodiment is used to form a semiconductor device. Speech is also beneficial.

＜第2步驟＞
於所述第1步驟之後，第2步驟中進行用以增大改質層18內所形成的黑點狀缺陷D的缺陷密度的缺陷形成熱處理。如使用參考實驗例1、參考實驗例2進行說明般，黑點狀缺陷D的缺陷密度大幅依存於直至到達磊晶成長溫度為止的升溫過程中的溫度。因此，藉由在形成磊晶層之前進行用以形成缺陷的熱處理，可增大最終所獲得的半導體磊晶晶圓100中的黑點狀缺陷D的缺陷密度，且可提高吸除能力。＜ Second step ＞
After the first step, a defect forming heat treatment is performed in a second step to increase the defect density of the black dot-like defects D formed in the modified layer 18. As described with reference experimental example 1 and reference experimental example 2, the defect density of the black spot-shaped defect D largely depends on the temperature during the temperature increase until the epitaxial growth temperature is reached. Therefore, by performing a heat treatment for forming a defect before forming an epitaxial layer, the density of black dot defects D in the semiconductor epitaxial wafer 100 finally obtained can be increased, and the gettering ability can be improved.

該第2步驟中的缺陷形成熱處理的熱處理條件若可增大黑點狀缺陷D的缺陷密度，則並無限制，較佳為於小於800℃的第1溫度區域保持半導體晶圓的第1保持時間為0秒以上且45秒以下，且自第1溫度區域升溫後的、於800℃以上且小於1000℃的第2溫度區域保持所述半導體晶圓的第2保持時間為30秒以上。The heat treatment conditions of the defect formation heat treatment in the second step are not limited as long as the defect density of the black spot-shaped defect D can be increased, and it is preferable to hold the first holding of the semiconductor wafer in the first temperature region of less than 800 ° C. The time is 0 seconds or more and 45 seconds or less, and the second holding time for holding the semiconductor wafer in the second temperature range of 800 ° C. or more and less than 1000 ° C. after the temperature rise in the first temperature range is 30 seconds or more.

參照圖4，如所述般，第1溫度區域相當於缺陷種消失的溫度帶，因此通過該溫度帶的時間較佳為儘可能短。因此，較佳為將第1保持時間設為45秒以下，更佳為設為30秒以下，進而佳為設為10秒以下，特佳為設為5秒以下。另外，只要將向磊晶成長爐內投入半導體晶圓10的爐內投入溫度設為800℃以上，則亦可將第1保持時間設為0秒。Referring to FIG. 4, as described above, the first temperature region corresponds to a temperature band in which the defect species disappears. Therefore, the time to pass through the temperature band is preferably as short as possible. Therefore, the first holding time is preferably 45 seconds or less, more preferably 30 seconds or less, even more preferably 10 seconds or less, and particularly preferably 5 seconds or less. In addition, the first holding time may be set to 0 seconds as long as the in-furnace charging temperature of the semiconductor wafer 10 into the epitaxial growth furnace is 800 ° C or higher.

另外，第2溫度區域相當於缺陷成長的溫度帶，因此通過該溫度帶的時間較佳為比較長。因此，較佳為將第2保持時間設為30秒以上，更佳為設為60秒以上。雖認為第2保持時間越長越佳，但若考慮到製造效率，則可將第2保持時間的上限設為300秒。In addition, since the second temperature region corresponds to a temperature zone in which the defect grows, it is preferable that the time to pass through this temperature zone is relatively long. Therefore, the second holding time is preferably set to 30 seconds or more, and more preferably set to 60 seconds or more. Although the second holding time is considered to be longer, the upper limit of the second holding time may be set to 300 seconds in consideration of manufacturing efficiency.

再者，圖4中，圖示出於第2溫度區域中以固定溫度進行保持的態樣，但本發明並不受該態樣的任何限定。例如，於第2溫度區域中，可將升溫速率設為數℃/秒（例如1℃/秒～3℃/秒）左右、或以進而慢的升溫速率進行升溫來實現所述第2保持時間，亦可重覆進行升溫及固定溫度的保持等。In addition, FIG. 4 shows a state where the temperature is maintained at a fixed temperature in the second temperature range, but the present invention is not limited to this state. For example, in the second temperature region, the second holding time may be achieved by setting the temperature increase rate to about several degrees Celsius / second (for example, 1 ° C / second to 3 ° C / second), or by increasing the temperature at a further slow temperature increase rate. It is also possible to repeatedly increase the temperature and maintain a fixed temperature.

另外，利用本步驟的缺陷形成熱處理與用以恢復結晶性的恢復熱處理不同。用以恢復結晶性的恢復熱處理是用以對藉由簇離子注入而形成的非晶狀態進行恢復，較缺陷形成熱處理而言，需要比較長時間地進行比較高的溫度的熱處理。In addition, the defect formation heat treatment using this step is different from the restoration heat treatment to restore crystallinity. The restoration heat treatment for restoring crystallinity is used for restoring the amorphous state formed by cluster ion implantation. Compared with the defect formation heat treatment, a relatively high temperature heat treatment is required for a long time.

＜第3步驟＞
緊接所述第2步驟，進行於半導體晶圓10的改質層18上形成磊晶層20的第3步驟（圖5中的（A）至（C）的步驟C）。作為所形成的磊晶層20，例如可列舉矽磊晶層，可藉由通常的條件而形成。於該情況下，例如將氫作為載氣，將二氯矽烷、三氯矽烷等源氣體導入至腔室內，成長溫度亦視所使用的源氣體而不同，可於1000℃～1200℃的範圍的溫度下藉由CVD法於半導體晶圓10上進行磊晶成長。磊晶層20較佳為將厚度設為1 μm～15 μm的範圍內。其原因在於：於小於1 μm的情況下，可能因摻雜劑自半導體晶圓10向外擴散而導致磊晶層20的電阻率變化，另外，於超過15 μm的情況下，有對固體攝像元件的分光感度特性產生影響之虞。＜ Step 3 ＞
Following the second step, a third step (step C of (A) to (C) in FIG. 5) of forming an epitaxial layer 20 on the modified layer 18 of the semiconductor wafer 10 is performed. Examples of the epitaxial layer 20 to be formed include a silicon epitaxial layer, and the epitaxial layer 20 can be formed under normal conditions. In this case, for example, hydrogen is used as a carrier gas, and a source gas such as dichlorosilane or trichlorosilane is introduced into the chamber. The growth temperature also varies depending on the source gas used, and can be in the range of 1000 ° C to 1200 ° C. Epitaxial growth is performed on the semiconductor wafer 10 by a CVD method at a temperature. The epitaxial layer 20 preferably has a thickness in a range of 1 μm to 15 μm. The reason is that in the case of less than 1 μm, the resistivity of the epitaxial layer 20 may change due to the diffusion of dopants from the semiconductor wafer 10 outward. In addition, in the case of more than 15 μm, there is a solid-state imaging. The spectral sensitivity characteristics of the device may be affected.

第3步驟後的黑點狀缺陷D的缺陷密度雖較剛進行第2步驟後的黑點狀缺陷D的缺陷密度減小，但因經過利用第2步驟的缺陷形成熱處理，而較先前所形成的缺陷密度而言，最終生成的缺陷密度變大。因此，即便將簇離子注入條件設為相同，亦可較先前而言非偶然地提高所獲得的半導體磊晶晶圓100的吸除能力。Although the defect density of the black dot-like defect D after the third step is smaller than that of the black dot-like defect D immediately after the second step, the defect density of the black dot-like defect D after the second step is lower than that of the previous one due to the heat treatment of the defect formation using the second step. In terms of the defect density, the resulting defect density becomes larger. Therefore, even if the cluster ion implantation conditions are set to be the same, the gettering ability of the obtained semiconductor epitaxial wafer 100 can be increased by accident than before.

再者，所謂本說明書中的黑點狀缺陷D，是指於利用TEM以亮模式觀察半導體磊晶晶圓100的劈開剖面的情況下，於改質層18內以黑點的形式觀察到的缺陷，直徑為數奈米（nm）左右的微小尺寸的缺陷除外。黑點狀缺陷D的尺寸為15 nm以上且100 nm以下，所謂「黑點狀缺陷的尺寸」，是設為TEM圖像中的缺陷的直徑。再者，於黑點狀缺陷D為並非圓形或不可視作圓形的形狀的情況下，使用內包黑點狀缺陷D的最小直徑的外接圓，近似於圓形而設定直徑。另外，關於黑點狀缺陷的「缺陷密度」，是對TEM圖像中存在黑點狀缺陷D的區域中的單位規定面積的缺陷的個數根據此時的TEM觀察中所使用的樣品的最終厚度而定義。It should be noted that the black dot-like defect D in this specification refers to a black dot in the modified layer 18 when the cleaved cross section of the semiconductor epitaxial wafer 100 is observed in a bright mode using a TEM. Defects, except for micro-sized defects with a diameter of a few nanometers (nm). The size of the black dot-like defect D is 15 nm or more and 100 nm or less, and the "size of the black dot-like defect" is the diameter of the defect in the TEM image. When the black dot-like defect D is not a circle or a shape that cannot be regarded as a circle, the outer diameter of the smallest diameter of the black dot-like defect D is used to approximate the circle to set the diameter. The "defect density" of black spot defects is the final number of defects per unit area in the area where black spot defects D are present in the TEM image. Thickness.

以下，對本實施形態的多元素簇離子的照射態樣進行說明。Hereinafter, the irradiation state of the multi-element cluster ion in this embodiment will be described.

所照射的多元素簇離子16的構成元素若含包含碳、氫及氧，則其他構成元素並無特別限定。多元素簇離子16的構成元素進而可包含的元素可列舉硼、磷、砷、銻等。As long as the constituent elements of the irradiated multi-element cluster ion 16 include carbon, hydrogen, and oxygen, other constituent elements are not particularly limited. Examples of elements that can be included in the constituent elements of the multi-element cluster ion 16 include boron, phosphorus, arsenic, and antimony.

再者，離子化的化合物並無特別限定，作為可離子化的化合物，例如可使用二乙基醚（C4 H10 O）、乙醇（C2 H6 O）、二乙基酮（C5 H10 O）等。特佳為使用藉由二乙基醚、乙醇等所生成的簇Cn Hm Ol （l、m、n彼此獨立，1≦n≦16，1≦m≦16，1≦l≦16）。特佳為簇離子的碳原子數為16個以下，且簇離子的氧原子數為16個以下。其原因在於容易控制小尺寸的簇離子射束。另外，例如若使用三甲基亞磷酸酯（C3 H9 O3 P）等，則除了碳、氫及氧以外，多元素簇離子16的構成元素中亦可包含磷。The ionized compound is not particularly limited. Examples of the ionizable compound include diethyl ether (C 4 H 10 O), ethanol (C 2 H 6 O), and diethyl ketone (C 5 H 10 O) and so on. Particularly preferred is the use of a cluster C n H m O l produced by diethyl ether, ethanol, etc. (l, m, n are independent of each other, 1 ≦ n ≦ 16, 1 ≦ m ≦ 16, 1 ≦ l ≦ 16) . Particularly preferably, the number of carbon atoms of the cluster ion is 16 or less, and the number of oxygen atoms of the cluster ion is 16 or less. The reason is that it is easy to control a cluster ion beam of a small size. In addition, for example, if trimethylphosphite (C 3 H 9 O 3 P) is used, in addition to carbon, hydrogen, and oxygen, the constituent elements of the multi-element cluster ion 16 may include phosphorus.

簇尺寸可於2個～100個、較佳為60個以下、更佳為50個以下的範圍內適宜設定。簇尺寸的調整可藉由調整自噴嘴噴出的氣體的氣體壓力及真空容器的壓力、離子化時對燈絲（filament）施加的電壓等而進行。再者，簇尺寸可藉由以下方式求出：藉由利用四極高頻電場的質譜分析或飛行時間（time-of-flight）質譜分析而求出簇個數分佈，取簇個數的平均值。The cluster size can be appropriately set within a range of 2 to 100, preferably 60 or less, and more preferably 50 or less. The cluster size can be adjusted by adjusting the gas pressure of the gas ejected from the nozzle, the pressure of the vacuum container, the voltage applied to the filament during ionization, and the like. In addition, the cluster size can be obtained by: mass distribution analysis using a quadrupole high-frequency electric field or time-of-flight mass spectrometry to obtain the cluster number distribution, and taking the average of the number of clusters .

簇離子的加速電壓與簇尺寸一起對簇離子的構成元素的深度方向的濃度分佈的峰值位置造成影響。於本實施形態中，可將多元素簇離子16的加速電壓設為超過0 keV/Cluster且小於200 keV/Cluster，較佳為設為100 keV/Cluster以下，進而佳為設為80 keV/Cluster以下。再者，關於加速電壓的調整，通常使用（1）靜電加速、（2）高頻加速此兩種方法。前者的方法有等間隔地排列多個電極，於該些電極間施加相等的電壓，於軸方向上製作等加速電場的方法。後者的方法有一邊使離子以直線狀行進一邊使用高頻進行加速的線性直線加速器（linac）法。The acceleration voltage of the cluster ions together with the cluster size affects the peak position of the concentration distribution in the depth direction of the constituent elements of the cluster ions. In this embodiment, the acceleration voltage of the multi-element cluster ion 16 can be set to more than 0 keV / Cluster and less than 200 keV / Cluster, preferably 100 keV / Cluster or less, and even more preferably 80 keV / Cluster. the following. Regarding the adjustment of the acceleration voltage, two methods (1) electrostatic acceleration and (2) high-frequency acceleration are generally used. The former method is a method in which a plurality of electrodes are arranged at equal intervals, an equal voltage is applied between the electrodes, and a constant acceleration electric field is produced in the axial direction. The latter method includes a linear linac method in which ions are accelerated in a linear manner while accelerating using high frequencies.

另外，簇離子的劑量可藉由控制離子照射時間而調整。碳、氫及氧各元素的劑量是由簇離子種類及簇離子的劑量（Cluster/cm2 ）來決定。本實施形態中，可以碳的劑量為1×1013 原子/cm2 ～1×1017 原子/cm2 的方式調整多元素簇離子16的劑量，較佳為將碳的劑量設為5×1013 原子/cm2 以上且5×1016 原子/cm2 以下。其原因在於：於碳的劑量小於1×1013 原子/cm2 的情況下，存在無法獲得充分的吸除能力的情況，於碳的劑量超過1×1016 原子/cm2 的情況下，有對磊晶層20的表面造成大的損傷之虞。In addition, the dose of cluster ions can be adjusted by controlling the ion irradiation time. The dose of each element of carbon, hydrogen, and oxygen is determined by the cluster ion type and the cluster ion dose (Cluster / cm 2 ). In this embodiment, the dose of the multi-element cluster ion 16 can be adjusted in such a manner that the dose of carbon is 1 × 10 13 atoms / cm 2 to 1 × 10 17 atoms / cm 2 , and the dose of carbon is preferably set to 5 × 10. 13 atoms / cm 2 or more and 5 × 10 16 atoms / cm 2 or less. The reason is that when the dose of carbon is less than 1 × 10 13 atoms / cm 2 , there may be cases where sufficient absorption capacity cannot be obtained, and when the dose of carbon exceeds 1 × 10 16 atoms / cm 2 , The surface of the epitaxial layer 20 may be greatly damaged.

另外，多元素簇離子16的射束電流值只要設為50 μA以上且5000 μA以下即可。再者，簇離子的射束電流值例如可藉由變更離子源中的原料氣體的分解條件等而調整。The beam current value of the multi-element cluster ion 16 may be set to 50 μA or more and 5000 μA or less. The beam current value of the cluster ions can be adjusted, for example, by changing the decomposition conditions of the source gas in the ion source.

以上，對本發明的代表性實施形態進行了說明，但本發明並不限定於該些實施形態。
[實施例]As mentioned above, although the typical embodiment of this invention was described, this invention is not limited to these embodiment.
[Example]

（試行例1）
準備由CZ單晶矽錠獲得的矽晶圓（直徑：300 mm，厚度：725 μm，摻雜劑種類：磷，電阻率：10 Ω·cm）。繼而，使用簇離子產生裝置（日新離子機器公司製造，型號：克拉麗絲（CLARIS）（註冊商標）），將包含使二乙基醚（C4 H10 O）簇離子化而成的CH3 O的多元素簇離子以加速電壓80 keV/Cluster的注入條件照射至矽晶圓的表面。另外，將該簇離子的劑量設為1.0×1015 cluster/cm2 （碳的劑量亦為1.0×1015 原子/cm2 ）。(Trial example 1)
A silicon wafer (diameter: 300 mm, thickness: 725 μm, dopant type: phosphorus, resistivity: 10 Ω · cm) obtained from a CZ single crystal silicon ingot was prepared. Next, using a cluster ion generator (manufactured by Nisshin Ion Machinery Co., Ltd., model: CLARIS (registered trademark)), CH containing ionized diethyl ether (C 4 H 10 O) clusters was ionized. Multi-element cluster ions of 3 O were irradiated onto the surface of the silicon wafer under an implantation condition of an acceleration voltage of 80 keV / Cluster. The dose of the cluster ions is 1.0 × 10 15 cluster / cm 2 (the dose of carbon is also 1.0 × 10 15 atoms / cm 2 ).

其次，將所述矽晶圓搬送至爐內溫度600℃的逐片式磊晶成長裝置（應用材料（Applied Materials）公司製造）內。繼而，將直至800℃為止的升溫時間設為5秒（升溫速率40℃/s），將800℃～1000℃為止的升溫時間設為5秒（升溫速率40℃/s）並上升至1000℃。緊接著，於裝置內升溫至1120℃，在該溫度下實施30秒的氫烘烤處理後，以氫作為載氣，以三氯矽烷作為源氣體，於1120℃下藉由CVD法於矽晶圓的形成有改質層的一側的表面上使矽的磊晶層（厚度：5 μm，摻雜劑種類：磷，電阻率：50 Ω·cm）進行磊晶成長，製作試行例1的磊晶矽晶圓。Next, the silicon wafer was transferred to a wafer-type epitaxial growth device (manufactured by Applied Materials) at a temperature of 600 ° C in the furnace. Next, the heating time up to 800 ° C was set to 5 seconds (heating rate 40 ° C / s), and the heating time up to 800 ° C to 1000 ° C was set to 5 seconds (heating rate 40 ° C / s), and the temperature was raised to 1000 ° C. . Next, the temperature was raised to 1120 ° C in the apparatus, and hydrogen baking was performed at this temperature for 30 seconds. Then, hydrogen was used as a carrier gas, trichlorosilane was used as a source gas, and the silicon crystal was subjected to CVD at 1120 ° C. An epitaxial layer of silicon (thickness: 5 μm, dopant type: phosphorous, resistivity: 50 Ω · cm) was epitaxially grown on the surface of the side where the modified layer was formed, and a trial example 1 was produced. Epicrystalline silicon wafer.

（試行例2～試行例25）
如下述表1所示般將直至800℃為止的升溫時間設為5秒（升溫速率40℃/s）、10秒（升溫速率20℃/s）、30秒（升溫速率6.7℃/s）、45秒（升溫速率6.7℃/s）、60秒（升溫速率3.3℃/s），將800℃～1000℃為止的升溫時間設為5秒（升溫速率40℃/s）、10秒（升溫速率20℃/s）、30秒（升溫速率6.7℃/s）、60秒（升溫速率3.3℃/s）、300秒（升溫速率0.67℃/s），除此以外，與試行例1同樣地製作試行例2～試行例25的磊晶矽晶圓。(Trial Example 2 to Trial Example 25)
As shown in Table 1 below, the heating time up to 800 ° C is set to 5 seconds (heating rate 40 ° C / s), 10 seconds (heating rate 20 ° C / s), 30 seconds (heating rate 6.7 ° C / s), 45 seconds (heating rate 6.7 ° C / s), 60 seconds (heating rate 3.3 ° C / s), and the heating time from 800 ° C to 1000 ° C is 5 seconds (heating rate 40 ° C / s), 10 seconds (heating rate Except for 20 ° C / s), 30 seconds (heating rate: 6.7 ° C / s), 60 seconds (heating rate: 3.3 ° C / s), and 300 seconds (heating rate: 0.67 ° C / s), they were produced in the same manner as in Test Example 1. The epitaxial silicon wafer of Trial Example 2 to Trial Example 25.

[表1]

[Table 1]

＜評價1：利用TEM剖面照片的觀察＞
關於試行例1～試行例25的磊晶矽晶圓的各晶圓，利用TEM（Transmission Electron Microscope：穿透式電子顯微鏡）觀察基板界面附近的剖面，求出黑點狀缺陷的缺陷密度。再者，將於自基板界面起深度為300 nm以內的範圍內觀察到的缺陷尺寸為15 nm～100 nm以下的缺陷設為黑點狀缺陷。將所觀察到的缺陷密度一併示於表1中。<Evaluation 1: Observation by TEM section photograph>
Regarding each of the epitaxial silicon wafers of Trial Example 1 to Trial Example 25, a cross section near the substrate interface was observed with a TEM (Transmission Electron Microscope), and the defect density of black spot defects was determined. In addition, a defect having a defect size of 15 nm to 100 nm observed within a range of a depth of 300 nm from the substrate interface is referred to as a black dot defect. The observed defect densities are shown in Table 1.

＜評價2：吸除能力評價＞
對試行例1～試行例25的磊晶矽晶圓的各晶圓，評價吸除能力。首先，使用Ni污染液（1.0×1013 原子/cm2 ）並藉由旋塗污染法將各磊晶矽晶圓的磊晶層的表面強制污染，繼而於氮氣環境中於900℃下實施30分鐘的擴散熱處理。其後，對於各磊晶矽晶圓，進行SIMS測定，分別測定簇離子注入區域（本評價中，為了簡便而設為自基板界面起300 nm）中的Ni濃度的分佈。而且，求出離子注入區域中的Ni的捕獲量（相當於SIMS分佈中的Ni濃度的積分值）。Ni的捕獲量是如下述般進行分類並設為評價基準。將評價結果一併示於表1。
◎：9.7×1012 原子/cm2 以上
○：9.5×1012 原子/cm2 以上且小於9.7×1012 原子/cm2
△：9.0×1012 原子/cm2 以上且小於9.5×1012 原子/cm2
×：小於9.0×1012 原子/cm2 ＜ Evaluation 2: Evaluation of absorption capacity ＞
For each of the epitaxial silicon wafers of Trial Example 1 to Trial Example 25, the absorption capability was evaluated. First, the surface of the epitaxial layer of each epitaxial silicon wafer was forcibly contaminated by using a Ni contamination solution (1.0 × 10 13 atoms / cm 2 ) by a spin coating contamination method, and then performed at 900 ° C. in a nitrogen atmosphere for 30 Diffusion heat treatment in minutes. Thereafter, SIMS measurement was performed on each epitaxial silicon wafer, and the Ni concentration distribution in the cluster ion implantation region (in this evaluation, it is set to 300 nm from the substrate interface for simplicity) was measured. The amount of Ni captured in the ion implantation region (corresponding to the integrated value of the Ni concentration in the SIMS distribution) was determined. The amount of Ni captured was classified as described below and used as an evaluation criterion. The evaluation results are shown in Table 1.
：: 9.7 × 10 12 atoms / cm 2 or more ○: 9.5 × 10 12 atoms / cm 2 or more and less than 9.7 × 10 12 atoms / cm 2
△: 9.0 × 10 12 atoms / cm 2 or more and less than 9.5 × 10 12 atoms / cm 2
×: less than 9.0 × 10 12 atoms / cm 2

＜評價結果的考察＞
首先，根據表1而可確認到吸除能力的高低、與黑點狀缺陷的缺陷密度存在明確的相關關係，可確認到黑點狀缺陷的缺陷密度越大，吸除能力亦越高。而且，亦可確認到推斷為缺陷種消失的溫度帶的通過時間越短、且推斷為缺陷成長的溫度帶的通過時間越長，黑點狀缺陷的缺陷密度越變大。因此，即便簇條件相同，藉由進行用以增大黑點狀缺陷的缺陷密度的缺陷形成熱處理，亦可提高吸除能力。
[產業上的可利用性]＜ Examination of evaluation results ＞
First, according to Table 1, it can be confirmed that the level of the gettering ability is clearly related to the defect density of black spot defects, and it can be confirmed that the larger the density of the black spot defects, the higher the gettering ability. In addition, it was also confirmed that the shorter the transit time of the temperature zone estimated to be that the defect species disappeared and the longer the transit time of the temperature zone estimated to be from the growth of the defect, the larger the defect density of the black-spot defects. Therefore, even if the cluster conditions are the same, it is possible to improve the gettering ability by performing a defect formation heat treatment for increasing the defect density of black spot-shaped defects.
[Industrial availability]

根據本發明，可提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。According to the present invention, it is possible to provide a method for manufacturing a semiconductor epitaxial wafer that can have a higher gettering ability even if the cluster ion implantation conditions are the same.

10‧‧‧半導體晶圓10‧‧‧Semiconductor wafer

10A‧‧‧半導體晶圓的表面 10A‧‧‧Surface of semiconductor wafer

16‧‧‧簇離子 16‧‧‧ cluster ions

18‧‧‧改質層 18‧‧‧ reformed layer

20‧‧‧磊晶層 20‧‧‧Epitaxial layer

100‧‧‧半導體磊晶晶圓 100‧‧‧ semiconductor epitaxial wafer

D‧‧‧黑點狀缺陷 D‧‧‧ Black dot defect

圖1是表示伴隨磊晶成長的通常的熱處理順序的概念圖。FIG. 1 is a conceptual diagram showing a general heat treatment sequence accompanying epitaxial growth.

圖2是表示參考實驗例1中的磊晶矽晶圓的基板界面附近的穿透式電子顯微鏡（Transmission Electron Microscope，TEM）剖面圖的圖。 2 is a view showing a transmission electron microscope (TEM) cross-sectional view near a substrate interface of an epitaxial silicon wafer in Reference Experimental Example 1. FIG.

圖3是表示參考實驗例2中的磊晶矽晶圓的基板界面附近的TEM剖面圖的圖。 3 is a view showing a TEM cross-sectional view near a substrate interface of an epitaxial silicon wafer in Reference Experimental Example 2. FIG.

圖4是說明本發明的一實施形態的伴隨磊晶成長的熱處理順序的一態樣的示意剖面圖。 FIG. 4 is a schematic cross-sectional view illustrating an aspect of a heat treatment sequence accompanying epitaxial growth according to an embodiment of the present invention.

圖5中的（A）至（C）是說明本發明的一實施形態的半導體磊晶晶圓100的製造方法的示意剖面圖。 (A) to (C) in FIG. 5 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor epitaxial wafer 100 according to an embodiment of the present invention.

Claims (4)

一種半導體磊晶晶圓的製造方法，其特徵在於包括： 第1步驟，對半導體晶圓的表面注入包含碳、氫及氧此三種元素作為構成元素的多元素簇離子，於所述半導體晶圓的表層部形成所述多元素簇離子的構成元素固溶而成的改質層； 第2步驟，於所述第1步驟之後，進行用以增大所述改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理；以及 第3步驟，緊接所述第2步驟，於所述半導體晶圓的改質層上形成磊晶層。A method for manufacturing a semiconductor epitaxial wafer, comprising: In the first step, a multi-element cluster ion containing three elements of carbon, hydrogen, and oxygen as constituent elements is implanted on the surface of the semiconductor wafer, and the constituent elements of the multi-element cluster ion are solid-solved on the surface layer portion of the semiconductor wafer. Modified layer A second step, after the first step, performing a defect formation heat treatment to increase a defect density of black dot-like defects formed in the modified layer; and The third step, following the second step, forms an epitaxial layer on the modified layer of the semiconductor wafer. 如申請專利範圍第1項所述的半導體磊晶晶圓的製造方法，其中所述第2步驟中的所述缺陷形成熱處理的熱處理條件中，於小於800℃的第1溫度區域保持所述半導體晶圓的第1保持時間為0秒以上且45秒以下，且自第1溫度區域升溫後的、於800℃以上且小於1000℃的第2溫度區域保持所述半導體晶圓的第2保持時間為30秒以上。The method for manufacturing a semiconductor epitaxial wafer according to item 1 of the scope of patent application, wherein in the heat treatment conditions of the defect formation heat treatment in the second step, the semiconductor is held in a first temperature region of less than 800 ° C. The second holding time of the wafer is 0 seconds or more and 45 seconds or less, and the second holding time of holding the semiconductor wafer in the second temperature range of 800 ° C or higher and less than 1000 ° C after the temperature rise in the first temperature range It is more than 30 seconds. 如申請專利範圍第1項所述的半導體磊晶晶圓的製造方法，其中所述多元素簇離子的構成元素由碳、氫及氧此三種元素所組成。The method for manufacturing a semiconductor epitaxial wafer according to item 1 of the scope of patent application, wherein the constituent elements of the multi-element cluster ion are composed of three elements: carbon, hydrogen, and oxygen. 如申請專利範圍第1項至第3項中任一項所述的半導體磊晶晶圓的製造方法，其中所述半導體晶圓為矽晶圓。The method for manufacturing a semiconductor epitaxial wafer according to any one of claims 1 to 3, wherein the semiconductor wafer is a silicon wafer.
TW107138317A 2018-03-01 2018-10-30 Method for manufacturing semiconductor epitaxial wafer TWI708279B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-036909 2018-03-01
JP2018036909A JP6874718B2 (en) 2018-03-01 2018-03-01 Manufacturing method of semiconductor epitaxial wafer

Publications (2)

Publication Number Publication Date
TW201937558A true TW201937558A (en) 2019-09-16
TWI708279B TWI708279B (en) 2020-10-21

Family

ID=67822413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107138317A TWI708279B (en) 2018-03-01 2018-10-30 Method for manufacturing semiconductor epitaxial wafer

Country Status (4)

Country Link
JP (1) JP6874718B2 (en)
KR (1) KR102148440B1 (en)
CN (1) CN110223907B (en)
TW (1) TWI708279B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7259706B2 (en) * 2019-11-06 2023-04-18 株式会社Sumco Passivation effect evaluation method for epitaxial silicon wafers

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198832A (en) * 1984-03-23 1985-10-08 Nec Corp Semiconductor device
JPS631037A (en) * 1986-06-20 1988-01-06 Toshiba Corp Epitaxial wafer and manufacture thereof
KR101455564B1 (en) * 2005-12-09 2014-10-27 세미이큅, 인코포레이티드 System and method for the manufacture of semiconductor devices by the implantation of carbon clusters
JP2010114409A (en) * 2008-10-10 2010-05-20 Sony Corp Soi substrate and method for manufacturing the same, solid-state image pickup device and method for manufacturing the same, and image pickup device
JP6278591B2 (en) * 2012-11-13 2018-02-14 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP6065848B2 (en) * 2014-01-07 2017-01-25 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP6221928B2 (en) * 2014-05-13 2017-11-01 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer and manufacturing method of solid-state imaging device
JP6485315B2 (en) * 2015-10-15 2019-03-20 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer and manufacturing method of solid-state imaging device
JP6508030B2 (en) * 2015-12-17 2019-05-08 株式会社Sumco Method of manufacturing silicon epitaxial wafer and method of manufacturing solid-state imaging device
JP6504082B2 (en) * 2016-02-29 2019-04-24 株式会社Sumco Semiconductor epitaxial wafer, method of manufacturing the same, and method of manufacturing solid-state imaging device

Also Published As

Publication number Publication date
TWI708279B (en) 2020-10-21
JP6874718B2 (en) 2021-05-19
CN110223907A (en) 2019-09-10
CN110223907B (en) 2023-05-02
JP2019153647A (en) 2019-09-12
KR102148440B1 (en) 2020-08-26
KR20190104856A (en) 2019-09-11

Similar Documents

Publication Publication Date Title
TWI539044B (en) Manufacturing method for semiconductor epitaxial wafer, semiconductor epitaxial wafer and manufacturing method for solid-state imaging device
WO2014076921A1 (en) Production method for semiconductor epitaxial wafer, semiconductor epitaxial wafer, and production method for solid-state imaging element
JP5799935B2 (en) Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
CN107134404B (en) Semiconductor epitaxial wafer, method for manufacturing same, and method for manufacturing solid-state imaging element
TWI611482B (en) Method for manufacturing semiconductor epitaxial wafer and method for manufacturing solid-state imaging device
JP6107068B2 (en) Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer, and solid-state imaging device manufacturing method
KR102393269B1 (en) Method for manufacturing an epitaxial silicon wafer, an epitaxial silicon wafer, and a method for manufacturing a solid-state image sensor
JP6535432B2 (en) Method of manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method of manufacturing solid-state imaging device
TWI683350B (en) Manufacturing method of semiconductor epitaxial wafer and manufacturing method of semiconductor element
TWI690628B (en) Semiconductor epitaxial wafer and its manufacturing method and manufacturing method of solid photographic element
TWI708279B (en) Method for manufacturing semiconductor epitaxial wafer
CN113454756B (en) Semiconductor epitaxial wafer and method for manufacturing the same
JP6289805B2 (en) Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP6278592B2 (en) Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP2017175145A (en) Semiconductor epitaxial wafer manufacturing method, semiconductor epitaxial wafer, and solid-state imaging element manufacturing method
JP2017123477A (en) Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid-state imaging device
JP2017183736A (en) Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2017175143A (en) Semiconductor epitaxial wafer manufacturing method, semiconductor epitaxial wafer, and solid-state imaging element manufacturing method
JP2019153648A (en) Manufacturing method of semiconductor epitaxial wafer
JP2020035922A (en) Method of manufacturing semiconductor epitaxial wafer and method of manufacturing semiconductor device
JP2017175144A (en) Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer, and solid-state imaging element manufacturing method