TW201931605A - 半導體裝置及cmos電晶體 - Google Patents
半導體裝置及cmos電晶體 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 229910000314 transition metal oxide Inorganic materials 0.000 claims abstract description 8
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 claims description 4
- JKQOBWVOAYFWKG-UHFFFAOYSA-N molybdenum trioxide Chemical compound O=[Mo](=O)=O JKQOBWVOAYFWKG-UHFFFAOYSA-N 0.000 claims description 4
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical group O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910000417 bismuth pentoxide Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 description 127
- 239000012212 insulator Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 9
- 230000008859 change Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 239000005300 metallic glass Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005555 metalworking Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
本發明係一種半導體裝置及CMOS電晶體,其課題為精確度佳地控制半導體裝置之臨界值電壓Vth之同時,降低臨界值電壓Vth之不均。
解決手段為半導體裝置(10)係具備:電極(11),和中間膜(12),和絕緣膜(13),和半導體(14)。電極(11)係由金屬所構成。絕緣膜(13)係設置於電極(11)與半導體(14)之間,由絕緣性之過渡金屬氧化物所構成。中間膜(12)係設置於電極(11)與絕緣膜(13)之間。另外,中間膜(12)之傳導帶之下端係較構成電極(11)之金屬的費米位準為低。
解決手段為半導體裝置(10)係具備:電極(11),和中間膜(12),和絕緣膜(13),和半導體(14)。電極(11)係由金屬所構成。絕緣膜(13)係設置於電極(11)與半導體(14)之間,由絕緣性之過渡金屬氧化物所構成。中間膜(12)係設置於電極(11)與絕緣膜(13)之間。另外,中間膜(12)之傳導帶之下端係較構成電極(11)之金屬的費米位準為低。
Description
本發明之種種面向及實施形態係有關半導體裝置及CMOS電晶體。
半導體元件之電晶體的典型的閘極電極材料之一的氮化鈦(TiN)之工作函數係具有對於結晶面方位而言之依存性,於(110)面與(111)面係有0.2eV的差。以TiN閘極電極被覆在微細之半導體電路所利用之3次元電晶體的FinFET的矽(Si)通道上之情況,因於各金屬結晶粒,工作函數不同而產生Si通道上之電位的局部性波動。此係成為於半導體元件間的特性(例如,臨界值電壓Vth的值)產生不均之原因。
為了解決此等,而檢討有經由非晶形金屬而形成閘極電極之情況。於可適用閘極電極之非晶形金屬的代表性材料,係知道有氮化鉭矽(TaSiN)。經由利用非晶形金屬於閘極電極而降低因工作函數的結晶面方位引起之臨界值電壓Vth的不均。
[先前技術文獻]
[非專利文獻]
[先前技術文獻]
[非專利文獻]
[非專利文獻1] T. Matsukawa, et al ”Influence of work function var iation in a metal gate on fluctuation of current-onset voltage for undoped-channel FinFETs” Extended Abstracts of the 2013 Internatio nal Conference on Solid State Devices and Materials, Fukuoka, 2013,pp740-741
[發明欲解決之課題]
此外,電晶體之臨界值電壓Vth係受到短通道效果(SCE:Short Channel Effect)、DIBL(Drain Induced Barrier Lowering)、Body Effect等之複數的要因之影響。但,使用於閘極電極之材料的工作函數係決定臨界值電壓Vth之主要的要因。例如,如圖1所示,微細化之電晶體的閘極電極所必要之工作函數的值係在p型電晶體中,可估計為4.9~5.1eV、而在n型電晶體中,可估計為4.3~4.5eV。電極之工作函數的不均係直接反映於電晶體之臨界值電壓Vth的不均。
臨界值電壓Vth之不均則對於元件特性帶來之影響為大,而可無視特性之影響的不均程度係例如,如圖2所示為10mV左右。在電晶體的製造處理中,臨界值電壓Vth係以往,經由不純物離子注入而被調整。但根據近年之電晶體的微細化,所摻雜之不純物濃度之統計性的不均則表面化,此等本身則成為臨界值電壓Vth之不均的原因。因此,有著避免對於電晶體的通道或殼體之不純物摻雜之傾向。因此,為了內置成為適於高輸出,低輸出,或輸出入等各種用途所設計的臨界值電壓Vth之電晶體,係必須在閘極電極中選擇不同之工作函數。
但,特別是p形電晶體所必要之高工作函數的金屬材料(例如,Pt等)係一般有著加工性差的問題。另外,例如,如圖3及圖4所示,亦可經由使複數的金屬融合而改變工作函數的值,但合金的工作函數的值係無加成性之故,經由複數之金屬的融合而將工作函數的值設為如設計值的值之情況係困難。因此,伴隨著半導體的微細化之進展,準備具有電路形成所必要之各種的臨界值電壓Vth之電晶體亦困難。
[為了解決課題之手段]
[為了解決課題之手段]
本發明之一面向係半導體裝置,其中,具備:電極,和半導體,和絕緣膜,和中間膜。電極係由金屬所構成。絕緣膜係設置於電極與半導體之間,由絕緣性之過渡金屬氧化物所構成。中間膜係設置於電極與絕緣膜之間。另外,中間膜之傳導帶之下端係較構成電極之金屬的費米位準為低。
[發明效果]
[發明效果]
若根據本發明之種種面向及實施形態,則可降低半導體裝置之臨界值電壓Vth之不均同時,可精確度佳地控制臨界值電壓Vth者。
例如,所揭示之半導體裝置係在1個實施形態中,具備:第1電極,和第1半導體,和第1絕緣膜,和中間膜。第1電極係由金屬所構成。第1絕緣膜係設置於第1電極與第1半導體之間,由絕緣性之過渡金屬氧化物所構成。中間膜係設置於第1電極與第1絕緣膜之間。另外,中間膜之傳導帶之下端係較構成第1電極之金屬的費米位準為低。
另外,所揭示之半導體裝置之1個的實施形態中,中間膜之厚度係亦可為1nm以下。
另外,在所揭示之半導體裝置之1個的實施形態中,構成第1絕緣膜之過渡金屬氧化物係亦可為氧化鉿(HfO2
)、二氧化鋯(ZrO2
)、氧化鋁(Al2
O3
)、氧化釔(Y2
O3
)、氧化銫(CeO2
),氧化鑭(La2
O3
),氧化釓(Gd2
O3
)、五氧化二鉭(Ta2
O5
)、五氧化二鈮(Nb2
O5
)、或此等複合氧化物,Silicate、或者層積膜。另外,中間膜係含有五氧化二釩(V2
O5
)或三氧化鉬(MoO3
)之至少任一亦可。
另外,所揭示之CMOS電晶體係在1個實施形態中,具備:作為閘極堆疊構造,具有第2電極,第2絕緣膜,及第2半導體之n型MOS電晶體,和作為閘極堆疊構造,含有上述之半導體裝置之p型MOS電晶體亦可。
於以下,對於所揭示之半導體裝置及CMOS電晶體的實施形態,依據圖面而詳細進行說明。又,並非經由本實施形態,限定所揭示之半導體裝置及CMOS電晶體者。
[量子井構造]
圖5係顯示經由量子井所致之擬似性的金屬電極形成之一例的概念圖。於量子井構造中,係形成有依存於量子井的尺寸之被量子化之次能帶構造。另外,量子井構造之費米能量係經由被電子佔有之次能帶的上端之能量而加以決定。
圖5係顯示經由量子井所致之擬似性的金屬電極形成之一例的概念圖。於量子井構造中,係形成有依存於量子井的尺寸之被量子化之次能帶構造。另外,量子井構造之費米能量係經由被電子佔有之次能帶的上端之能量而加以決定。
通常,量子井係例如,如圖5所示,作為以絕緣體而圍繞井部之金屬的IMI(Insulator Metal Insulator)構造而被形成。但若為具有較金屬的工作函數為大之電子親和力的絕緣體,例如,如圖6所示,經由MIM(Metal Insulator Metal)構造,可形成自發性地蓄積電子於井的擬似金屬構造者。圖6係顯示MIM構造及IMI構造之量子井的一例之模式圖。圖6(a)係顯示MIM構造之量子井的一例之模式圖,圖6(b)係顯示IMI構造之量子井的一例之模式圖。
作為半導體元件之電極材料所大量使用之金屬材料係例如,具有4.5eV前後之工作函數之構成為多。但MoO3
及V2
O5
等係例如,如圖7所示,顯示6.5eV前後之極大的電子親和力之絕緣體。圖7係顯示在MIM構造之量子井材料的候補之一例之圖。
經由組合MoO3
或V2
O5
之薄膜,和TiN等之金屬電極,鄰接之金屬電極則成為電子供給源,而絕緣膜之量子井中的次能帶係在熱平衡狀態中自然地電子佔有。並且,形成有具有MIM構造之量子井的擬似金屬電極。另外,作為擬似金屬電極而發揮機能之量子井構造係亦可經由成為電子供給源之金屬電極則僅位於單側之MII(Metal Insulator Insulator)構造而實現。MII構造之擬似金屬電極係可經由設為以電子親和力較MoO3
或V2
O5
等之材料為小之絕緣材料與金屬電極夾持MoO3
、V2
O5
等之層積構造而形成。
[半導體裝置10之構造]
圖8係顯示在本實施形態之半導體裝置10之一例之圖。圖8(a)係顯示在本實施形態之半導體裝置10的構造之一例。另外,圖8(b)係顯示在本實施形態之半導體裝置10之電極11,中間膜12,及絕緣膜13之工作函數的關係之一例。在本實施形態之半導體裝置10係例如,如圖8所示,具備:電極11,中間膜12,絕緣膜13,及半導體14。在本實施形態之半導體裝置10係MIS(Metal Insulator
Semiconductor)構造。
圖8係顯示在本實施形態之半導體裝置10之一例之圖。圖8(a)係顯示在本實施形態之半導體裝置10的構造之一例。另外,圖8(b)係顯示在本實施形態之半導體裝置10之電極11,中間膜12,及絕緣膜13之工作函數的關係之一例。在本實施形態之半導體裝置10係例如,如圖8所示,具備:電極11,中間膜12,絕緣膜13,及半導體14。在本實施形態之半導體裝置10係MIS(Metal Insulator
Semiconductor)構造。
電極11係例如由TiN或氮化鉭(TaN)等之金屬所構成。半導體14係例如,由Si等所構成。絕緣膜13係設置於電極11與半導體14之間,由絕緣性之過渡金屬氧化物所構成。中間膜12係設置於電極11與絕緣膜13之間。另外,例如,如圖8(b)所示,中間膜12之傳導帶的下端係位於自真空電位Vac至6.5eV之位置,而較構成電極11之金屬(例如,TiN或TaN)之費米位準(在圖8(b)的例中,自真空電位Vac至4.5eV之位置)為低。
在本實施形態中,絕緣膜13係HfO2
、ZrO2
、Al2
O3
、Y2
O3
、CeO2
、La2
O3
、Gd2
O3
、Ta2
O5
、Nb2
O5
、或此等複合氧化物、Silicate、或者層積膜。另外,中間膜12係包含V2
O5
或MoO3
之至少任一。
量子井構造係除了圖8(a)所示之經由薄膜的層積構造所致之構成以外,亦可為例如,如圖9所示,埋入粒狀之MoO3
或V2
O5
等之中間膜12於電極11之2次元量子井構造。圖9係顯示半導體裝置之其他例的圖。
另外,擬似金屬電極之工作函數係可經由鄰接於中間膜12之電極11的工作函數,及中間膜12之膜厚或量子井的口徑而調變者。圖10係顯示經由絕緣體之量子井徑所致的工作函數之調整之一例之圖。圖11係顯示絕緣體之量子井徑與費米位準之關係的一例之圖。
例如,如圖10(a)~(c),若將絕緣體之量子井小徑化,次能帶之能量則上升,而費米位準亦上升(工作函數係變小)。另外,在將絕緣體之量子井小徑化之過程,決定擬費米位準之上位的次能帶係依序遷移至下位的能帶,最終係落至基底狀態。即,量子井的深度係經由鄰接之金屬電極與MoO3
或V2
O5
等之絕緣體的電子親和力的差而決定,至位於金屬電極之量子井的上端之次能帶為止,經由來自鄰接之金屬電極的電子注入,被電子所佔有。並且,其能量係可經由MoO3
或V2
O5
等之絕緣體的膜厚或量子井徑而改變者。
另外,因伴隨能帶之遷移的非連續之費米能量Ef的變化所引起,量子井的擬費米位準係例如,如圖11所示,對於量子井的口徑而言振動性地進行變化。此係因依存於膜厚或量子井徑而被電子所佔有之次能帶狀態進行遷移之故。經由次能帶狀態之遷移,工作函數的值亦非連續地進行變化。
可經由量子井構造而調變的工作函數之範圍係依存於所組合之金屬電極的材料與量子井之尺寸及密度。圖12係顯示經由金屬電極之材料與量子井徑所致的工作函數之調變之一例之圖。圖12(a)係顯示絕緣體(V2
O5
)之量子井徑為4±0.2nm情況之工作函數的調變,而圖12(b)係顯示絕緣體(V2
O5
)之量子井徑為2±0.2nm情況之工作函數的調變,而圖12(c)係顯示絕緣體(V2
O5
)之量子井徑為1±0.2nm情況之工作函數的調變。例如,從圖12了解到,藉由與工作函數值為小之n型金屬(例如,釔(Y))組合而可得到廣範圍之工作函數。
另外,例如,如圖13所示,依存於中間膜12之膜厚而中間膜12之工作函數係振動性地進行變化。圖13係顯示作為電極11而使用TiN、作為中間膜12而使用V2
O5
、作為絕緣膜13而使用HfO2
情況之對於中間膜12之膜厚而言之量子井構造之工作函數的變化之一例之圖。工作函數的調變範圍係相較於經由量子井/qDot所致之超材料構造為窄。
另外,在中間膜12之膜厚為1nm以下之範圍中,次能帶中的電子則全部落在基底狀態之故,未有經由電極的材料所造成之不同,而可僅以中間膜12之膜厚,控制工作函數者。即,經由以1nm以下而形成量子井的尺寸,量子井中的次能帶係僅成為基底狀態之故,可避免經由成為工作函數的不均之原因的量子井之尺寸的變動而產生之次能帶狀態之遷移者。
另外,例如,如圖13所示,在中間膜12之膜厚為1nm以下之範圍中,對於膜厚的變化而言,工作函數則在5~6eV之廣範圍,單純地進行變化。因此,相較於中間膜12之膜厚則較1nm為厚之範圍,可加大經由中間膜12之膜厚的控制所致之工作函數之控制範圍(動態範圍)者。另外,在中間膜12之膜厚為1nm以下之範圍中,對於膜厚的變化而言,未看到工作函數之振動性的變化。因此,經由中間膜12之膜厚的控制,成為可精確度佳地控制半導體裝置10之工作函數者。
另外,例如,如圖14所示,經由將中間膜12之膜厚設為1nm以下,亦可抑制半導體裝置10之臨界值電壓Vth的不均者。圖14係顯示作為電極11而使用TiN、作為中間膜12而使用V2
O5
、作為絕緣膜13而使用HfO2
情況之對於中間膜12之膜厚而言之半導體裝置10的臨界值電壓Vth之變化之一例之圖。
另外,例如,經由ALD(Atomic Layer
Deposition)法,將V2 O5 等之中間膜12進行成膜,可精確度佳地控制中間膜12之膜厚。經由此,可縮小所成膜之實際的中間膜12之膜厚,和中間膜12之膜厚的設計目標值的差。
Deposition)法,將V2 O5 等之中間膜12進行成膜,可精確度佳地控制中間膜12之膜厚。經由此,可縮小所成膜之實際的中間膜12之膜厚,和中間膜12之膜厚的設計目標值的差。
如此,在本施形態中,經由僅控制V2
O5
等之中間膜12之膜厚,可控制半導體裝置10之工作函數者。並且,可經由ALD法等而將中間膜12之膜厚,呈成為接近於設計目標值的值地,精確度佳地進行控制之故,可將工作函數,呈成為接近於設計目標值的值地進行控制者。其結果,可將半導體裝置10之臨界值電壓Vth,呈成為接近於設計目標值的值地進行控制者。
在此,若MIS型電晶體之臨界值電壓Vth為低,電晶體的ON電流則增加,電晶體的動作速度則提升。但,另一方面,電晶體則作為OFF時之源極/汲極間的洩放電流則增加。
另外,若MIS型電晶體之臨界值電壓Vth為高,電晶體則作為OFF時之源極/汲極間的洩放電流則減少,但電晶體的ON電流亦減少,電晶體的動作速度則降低。
如此,電晶體的用途係代表性地係有著「高速・高消費電力」及及「低速・低消費電力」之2模式。因此,因應電晶體的用途,有必要最佳化臨界值電壓Vth。
在本實施形態中,採用例如圖8所示之閘極堆疊構造(電極11,中間膜12,絕緣膜13,及半導體14),經由調整中間膜12之膜厚,可最佳化半導體裝置10之臨界值電壓Vth者。
[洩放電流]
接著,對於中間膜12之膜厚與洩放電流進行實驗。圖15係顯示洩放電流之實驗結果的一例之圖。在圖15所示之實驗中,在圖8所示之半導體裝置10中,取代於半導體14,使用設置有電極11之樣本。另外,在實驗中,作為電極11之材料而使用TiN,作為中間膜12之材料而使用V2 O5 或WO3 ,作為絕緣膜13之材料而使用ZrO2 。另外,在實驗中,使用以1~1.5nm之膜厚的V2 O5 而形成中間膜12之樣本1,和以1nm以下之膜厚的V2 O5 而形成中間膜12之樣本2,和以1~1.5nm之膜厚的WO3 而形成中間膜12之樣本3,和以1nm以下之膜厚的WO3 而形成中間膜12之樣本4,和未設置有中間膜12之樣本5。在任一之樣本中,絕緣膜13之膜厚係均為6nm。
接著,對於中間膜12之膜厚與洩放電流進行實驗。圖15係顯示洩放電流之實驗結果的一例之圖。在圖15所示之實驗中,在圖8所示之半導體裝置10中,取代於半導體14,使用設置有電極11之樣本。另外,在實驗中,作為電極11之材料而使用TiN,作為中間膜12之材料而使用V2 O5 或WO3 ,作為絕緣膜13之材料而使用ZrO2 。另外,在實驗中,使用以1~1.5nm之膜厚的V2 O5 而形成中間膜12之樣本1,和以1nm以下之膜厚的V2 O5 而形成中間膜12之樣本2,和以1~1.5nm之膜厚的WO3 而形成中間膜12之樣本3,和以1nm以下之膜厚的WO3 而形成中間膜12之樣本4,和未設置有中間膜12之樣本5。在任一之樣本中,絕緣膜13之膜厚係均為6nm。
例如,如圖15所示,樣本2及4係洩放電流則較其他的樣本為低50%以上。樣本2及4係均具有1nm以下之膜厚的中間膜12之樣本。因此,經由將中間膜12之膜厚作為1nm以下,可降低半導體裝置10之洩放電流者。
在此,例如,在圖8(a)所示之構造的半導體裝置10中,於電極11與絕緣膜13之間,傳導帶之下端則經由使較構成電極11之金屬的費米位準為低之中間膜12中介存在,形成有量子井於電極11與絕緣膜13之間,含有中間膜12之電極11的表面上之工作函數則增加。並且,若工作函數增加,例如,如圖2所示,OFF時之半導體裝置10之洩放電流則減少。因此,經由將中間膜12之膜厚設為1nm以下,降低半導體裝置10之洩放電流。
又,在圖8所示之構造的半導體裝置10中,經由TiN而形成電極11之情況,於TiN之成膜係作為原料氣體而使用TiCl4
氣體及NH3
氣體情況為多。例如,未設置有中間膜12之情況,經由過渡金屬氧化物而形成之絕緣膜13係成為暴露於腐蝕性及還原性之環境者。因此,有於絕緣膜13產生損傷,絕緣性能劣化之情況。對此,在本實施形態中,在於絕緣膜13上層積中間膜12之後,於中間膜12上層積電極11。絕緣膜13係經由中間膜12而自腐蝕性及還原性的環境被保護。經由此,亦可抑制絕緣膜13之特性劣化者。
[其他]
例如,在上述之實施形態的半導體裝置10之構造則亦可適用於有CMOS電晶體的p型MOS電晶體的閘極堆疊構造。具體而言,經由作為閘極堆疊構造而具有含有經由p型的半導體而構成之半導體14之半導體裝置10之p型MOS電晶體,和作為閘極構造而具有通常的金屬電極,絕緣膜,及n型半導體之n型MOS電晶體,而構成CMOS電晶體亦可。
例如,在上述之實施形態的半導體裝置10之構造則亦可適用於有CMOS電晶體的p型MOS電晶體的閘極堆疊構造。具體而言,經由作為閘極堆疊構造而具有含有經由p型的半導體而構成之半導體14之半導體裝置10之p型MOS電晶體,和作為閘極構造而具有通常的金屬電極,絕緣膜,及n型半導體之n型MOS電晶體,而構成CMOS電晶體亦可。
另外,在上述之實施形態中,在MIS構造的半導體裝置10中,於電極11與絕緣膜13之間,設置有中間膜12,但揭示的技術係不限於此。例如,在圖6所例示之MIM構造中,於金屬電極與絕緣體之間,設置有中間膜12亦可。
10‧‧‧半導體裝置
11‧‧‧電極
12‧‧‧中間膜
13‧‧‧絕緣膜
14‧‧‧半導體
圖1係顯示各世代之High Performance邏輯電晶體所必要之閘極電極的工作函數之一例之圖。
圖2係顯示臨界值電壓Vth之不均則對電晶體特性帶來之影響的一例之圖。
圖3係說明各金屬材料之工作函數的圖。
圖4係顯示經由2元合金系所致的工作函數的值之調整結果的一例之圖。
圖5係顯示經由量子井所致之擬似性的金屬電極形成之一例的概念圖。
圖6係顯示MIM構造及IMI構造之量子井的一例之模式圖。
圖7係顯示在MIM構造之量子井材料的候補之一例之圖。
圖8係顯示在本實施形態之半導體裝置之一例之圖。
圖9係顯示半導體裝置之其他例的圖。
圖10係顯示經由絕緣體之量子井徑所致的工作函數之調整之一例之圖。
圖11係顯示絕緣體之量子井徑與費米位準之關係的一例之圖。
圖12係顯示經由金屬電極之材料與量子井徑所致的工作函數之調變之一例之圖。
圖13係顯示作為電極而使用TiN、作為中間膜而使用V2
O5
、作為絕緣膜而使用HfO2
情況之對於中間膜之膜厚而言之量子井構造之工作函數的變化之一例之圖。
圖14係顯示作為電極而使用TiN、作為中間膜而使用V2
O5
、作為絕緣膜而使用HfO2
情況之對於中間膜之膜厚而言之半導體裝置之臨界值電壓Vth的變化之一例之圖。
圖15係顯示洩放電流之實驗結果的一例之圖。
Claims (4)
- 一種半導體裝置,其特徵為具備:由金屬所成之第1電極, 和第1半導體, 和設置於前述第1電極與前述第1半導體之間,由絕緣性之過渡金屬氧化物所成之第1絕緣膜, 和設置於前述第1電極與前述第1絕緣膜之間的中間膜: 前述中間膜之傳導帶之下端係較構成前述第1電極之金屬的費米位準為低。
- 如申請專利範圍第1項記載之半導體裝置,其中,前述中間膜之厚度係1nm以下。
- 如申請專利範圍第1項或第2項記載之半導體裝置,其中,構成前述第1絕緣膜之過渡金屬氧化物係為氧化鉿(HfO2 )、二氧化鋯(ZrO2 )、氧化鋁(Al2 O3 )、氧化釔(Y2 O3 )、氧化銫(CeO2 ),氧化鑭(La2 O3 ),氧化釓(Gd2 O3 )、五氧化二鉭(Ta2 O5 )、五氧化二鈮(Nb2 O5 )、或此等複合氧化物,Silicate、或者層積膜, 前述中間膜係含有五氧化二釩(V2 O5 )或三氧化鉬(MoO3 )之至少任一者。
- 一種CMOS電晶體,其特徵為具備:作為閘極堆疊構造,具有第2電極,第2絕緣膜,及第2半導體之n型MOS電晶體, 和作為閘極堆疊構造,包含如申請專利範圍第1項至第3項任一項記載之半導體裝置的p型MOS電晶體者。
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JP4792716B2 (ja) * | 2004-07-06 | 2011-10-12 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JP4764030B2 (ja) * | 2005-03-03 | 2011-08-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7241691B2 (en) * | 2005-03-28 | 2007-07-10 | Freescale Semiconductor, Inc. | Conducting metal oxide with additive as p-MOS device electrode |
WO2009101824A1 (ja) * | 2008-02-13 | 2009-08-20 | Nec Corporation | Mis型電界効果トランジスタ及びその製造方法並び半導体装置及びその製造方法 |
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US9024299B2 (en) * | 2008-10-14 | 2015-05-05 | Imec | Method for fabricating a dual work function semiconductor device and the device made thereof |
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