TW201835980A - 後段介電質蝕刻用之選擇性沉積方法 - Google Patents

後段介電質蝕刻用之選擇性沉積方法 Download PDF

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TW201835980A
TW201835980A TW106144058A TW106144058A TW201835980A TW 201835980 A TW201835980 A TW 201835980A TW 106144058 A TW106144058 A TW 106144058A TW 106144058 A TW106144058 A TW 106144058A TW 201835980 A TW201835980 A TW 201835980A
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雅尼克 富赫皮耶
多尼 巴奈爾
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日商東京威力科創股份有限公司
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Abstract

本發明的實施例解決幾個與用於BEOL應用的介電材料之蝕刻相關的議題及問題。 根據一實施例，該方法包含：提供包含介電材料之圖案化的基板、將該基板曝露於氣相電漿以使介電材料的表面官能基化、將該基板曝露於與經官能基化之介電材料的表面反應的矽烷化試劑以形成介電膜、及依序重複該等曝露步驟至少一次以增加介電膜的厚度。根據一實施例，介電材料可為多孔低k材料，且介電膜將該多孔低k材料之表面上的孔洞密封。

Description

後段介電質蝕刻用之選擇性沉積方法
本發明係關於低k材料之乾蝕刻、及針對整合於製造互連線之積體電路（IC）製造製程之後段製程（BEOL）部分中之低k材料處理的領域。 [相關申請案的交互參照]
本申請案係關於且主張於2016年12月16日申請之美國臨時專利申請案序號第62/435,580號的優先權，其全部內容於此藉由參照納入本案揭示內容。
晶片設計技術的進步要求低k值介電材料整合在諸多BEOL層級中。因此，低k材料的搜尋已導致在介電材料中更多碳（C）及一些孔隙的併入。因此，在包含貫孔蝕刻、溝槽蝕刻、有機平坦化層（OPL）的剝離、及後蝕刻處理（PET）期間的乾蝕刻電漿處理期間，低k材料係越來越容易損壞。銅互連線的臨界尺寸（CD）係亦直接受低k材料之損壞量所影響。為了實現良好的可靠性，貫孔、溝槽、及貫孔與溝槽之間的間距之CD及輪廓控制在較小的尺寸處變得越來越關鍵。
本發明的實施例描述包含介電材料之基板的處理。根據一實施例，該方法包含：提供包含介電材料之圖案化的基板、將該基板曝露於氣相電漿以使介電材料的表面官能基化、將該基板曝露於與經官能基化之介電材料的表面反應的矽烷化試劑以在介電材料上形成介電膜、及依序重複該等曝露步驟至少一次以增加介電膜的厚度。
根據另一實施例，該方法包含：提供包含SiCOH層之圖案化的基板、將該基板曝露於基於O2 或基於CO2 的氣相電漿以使SiCOH層的表面官能基化、將該基板曝露於與經官能基化之SiCOH層的表面反應的矽烷化試劑以在SiCOH層上形成SiOx 膜、及依序重複該等曝露步驟至少一次以增加SiOx 膜的厚度。
根據另一實施例，該方法包含：提供包含多孔低k材料之圖案化的基板、將該基板曝露於基於O2 或基於CO2 的氣相電漿以使多孔低k材料的表面官能基化、將該基板曝露於與經官能基化之多孔低k材料的表面反應的矽烷化試劑以在介電材料上形成介電膜、及依序重複該等曝露步驟至少一次以增加介電膜的厚度。
本發明的實施例解決幾個與用於BEOL應用的介電材料之蝕刻相關的議題及問題，包含：a）如何減輕低k材料損壞；b）如何達成高貫孔倒角角度；c）如何密封多孔低k材料的孔洞；d）如何在蝕刻、濕清潔、及銅金屬化之後較佳地維持貫孔和溝槽的CD；e）如何獲得包含多層低k材料之堆疊的較直圖案輪廓（溝槽和貫孔）；及f）如何抑制低k材料與平坦化材料之間的交互作用。
本發明的實施例係關於處理介電材料的方法。根據一實施例，該方法提供介電材料之上的薄介電膜之選擇性沉積。根據一些實施例，介電膜可包含SiOx 、SiNx 、SiOx Ny 、或其組合，而介電材料可包含SiO2 、SiN、SiCN、及SiC、低k材料（例如SiCOH）、有機矽酸鹽玻璃（OSG）、或碳摻雜氧化物（CDO）。
該方法包含藉由電漿處理之介電材料之表面官能基化的步驟、及將經官能基化的表面曝露於矽烷化試劑的步驟。該兩步驟的製程導致在介電材料上薄介電膜的沉積，其中兩步驟的製程可重複至少一次以增加介電材料上之介電膜的厚度。一製程循環包含表面官能基化步驟及矽烷化步驟，而所沉積的介電膜之厚度係與製程循環的數目成比例。介電膜的化學組成可藉由改變表面官能基化的化學環境及矽烷化試劑而選擇及調整。在一些示例中，用於表面官能基化的化學環境可選自基於N2 、基於N2 /H2 、基於O2 、基於CO2 、基於COS、基於NH3 、基於H2 、及基於H2 O者。表面官能基化可例如包含-OH物種、-NH物種、及-SH物種。
根據一實施例，表面官能基化步驟可包含介電材料之表面的電漿氧化以形成具有反應性鍵結（例如具有Si-OH鍵的矽烷醇）之表面物種。電漿氧化係接著將介電材料曝露於矽烷化試劑（例如三甲基矽烷二甲胺（TMSDMA））的步驟。該製程循環可重複至少一次以在介電材料上沉積薄SiOx （x≤2）膜。實驗數據顯示所沉積的SiOx 膜之厚度係與製程循環的數目成正比。
圖1根據本發明之實施例示意性地顯示使介電材料的表面官能基化及使經官能基化的表面矽烷化的方法。一般而言，圖1中描繪之基本的矽烷化反應應用於任何矽烷化試劑。根據本發明的一些實施例，矽烷化試劑可選自二甲基矽烷二甲胺（DMSDMA）、三甲基矽烷二甲胺（TMSDMA）、雙（二甲胺基）二甲基矽烷（BDMADMS）、四甲基二矽氮烷（TMDS）、及其他烷基胺矽烷。矽烷化反應包含在基板溫度低於約200℃下，在步驟（1）中使矽烷化試劑（B）與介電材料（A）之表面上的親水性位置（例如-OH）熱力式地反應。在TMSDMA的情況下，矽烷化反應將SiMe3 基團與親水性位置鍵結以形成矽烷化的介電材料（C）及自矽烷化的介電材料（C）移除的HNMe2 反應副產物（D）。矽烷化的介電材料（C）可被稱為SiOx 膜。TMSDMA矽烷化反應可在將晶圓（基板）置放在加熱至180℃的基板支座上且在5托的氣體壓力下曝露於包含TMSDMA及N2 的氣體混合物之處理腔室中執行。
矽烷化試劑可具有化學式Rn SiX4-n ，其中R係烷基或官能基鏈，X係OR、NH2 、或NR2 ，且n=0~4。在一示例中，矽烷化試劑可為有機烷氧基矽烷試劑，諸如四乙氧基矽烷（Si(OEt)4 ，TEOS）。在另一示例中，矽烷化試劑可包含二甲基二甲氧基矽烷（DMDMOS）或二甲基二乙氧基矽烷（DMDEOS）。
仍參照圖1，根據本發明的實施例，製程循環包含藉由電漿處理（E）（例如包含O2 氣體或CO2 氣體的電漿氧化）之介電材料（C）（例如矽烷化的表面）之表面官能基化的步驟（2）。表面官能基化進一步形成被移除的反應副產物（G）。隨後的步驟（3）包含將官能基化的表面（F）曝露於矽烷化試劑（H）以形成SiOx 膜（I）及被移除的HNMe2 反應副產物（J）。表面官能基化的步驟形成對矽烷化試劑（H）呈反應性的介電材料表面（F）。步驟（2）及（3）的製程循環可重複至少一次以增加介電材料上之SiOx 膜的厚度。製程循環提供可能含碳及氫之薄SiOx 膜的選擇性生長。在圖1顯示的例子中，甲基基團（Me）包含碳及氫。
圖2根據本發明的實施例顯示作為製程循環的數目之函數的介電膜厚度。使用包含O2 電漿氧化及TMSDMA氣體曝露之交替步驟的製程循環將SiOx 膜沉積在具有毯覆的SiCOH膜於其上的晶圓上。執行5秒O2 電漿氧化而不對晶圓施加射頻（RF）偏壓功率。此電漿處理條件導致相對低之影響晶圓表面的離子能量。離子藉由具有等於電漿電位之電位的電漿鞘加速。SiOx 膜厚度係藉由橢圓偏光術測量。圖2顯示SiOx 膜厚度與上達至少20個製程循環之製程循環的數目成線性，且每製程循環沉積約1埃（Å）的SiOx 。因此，SiOx 膜厚度可由製程循環的數目直接控制。
不同的電漿氧化時間對SiOx 膜沉積速率的影響係使用O2 氣體及CO2 氣體研究。兩個不同的電漿氧化時間，即5秒和10秒的O2 及CO2 氣體電漿曝露係維持觀測10個製程循環。所有沉積的SiOx 膜之厚度係約1 nm，由此顯示介電材料表面的官能基化係在電漿處理的幾秒內輕易地達成。
用於BEOL介電質蝕刻之介電膜的選擇性沉積之示例
圖3A-3F根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法。在此實施例中，該方法藉由在低k材料上形成介電膜而有助於減輕低k材料損壞，其中當有機膜係自圖案化的基板剝離時，介電膜作為對抗碳減少的阻障。在圖3A中，圖案化的基板30包含蝕刻穿過有機平坦化層（OPL）312、圖案化的硬遮罩（HM）310、金屬硬遮罩308、介電硬遮罩306、SiCOH層304且停在蝕刻停止層302的貫孔303。SiCOH層304係具有介電常數（k）低於SiO2 之介電常數（k〜3.9）的低k層。根據一實施例，蝕刻停止層302可包含Si、C、H、及N或由Si、C、H、及N所組成。蝕刻停止層可由單一材料所組成，或者可包含具有不同組成的複數材料。
在藉由氣相蝕刻形成貫孔303之後，可執行基於氧的灰化製程以從圖案化的基板30移除CHFx 蝕刻產物及使介電材料的表面官能基化。表面官能基化在介電硬遮罩306、SiCOH層304、及蝕刻停止層302的表面上產生Si-OH表面終端305。如圖3B所描繪，基於氧的灰化製程亦移除OPL312之厚度的一部分。
之後，Si-OH表面終端305係藉由曝露於矽烷化試劑（例如TMSDMA）矽烷化以在貫孔303中的介電硬遮罩306、SiCOH層304、及蝕刻停止層302上形成SiOx 膜307（例如Si-O-SiMe3 ）。此在圖3C中示意性地顯示。
基於氧的電漿灰化製程可在SiOx 膜307上執行以使Si-OH表面終端再生。可形成基於氧的灰化及矽烷化之多個製程循環以增加貫孔303中SiOx 膜307的厚度且形成SiOx 膜309（圖3D）。各灰化步驟移除OPL 312的一部分，但SiOx 膜309保護貫孔303中介電硬遮罩306及SiCOH層304的表面免於碳減少。在圖3E中，OPL 312已被完全移除。
根據一實施例，圖3E中之圖案化的基板30可加以蝕刻以形成溝槽311且將貫孔303延伸穿過蝕刻停止層302至金屬線301。此在圖3F中示意性地顯示。SiOx 膜309之存在有助於較佳地保持貫孔303與溝槽311之間的角隅313，從而導致高的倒角角度。SiOx 膜309係比SiCOH層304緻密，且此導致在蝕刻製程期間SiOx 膜309比SiCOH層304低的蝕刻速率。為了比較，如示意性地顯示圖4中圖案化的基板40，不存在SiOx 膜309導致在貫孔303與溝槽311間的角隅315處之傾斜的倒角及低的倒角角度。此外，SiOx 膜309在溝槽蝕刻期間保護貫孔303中的介電表面免於碳減少。
圖9A及9B根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法。圖案化的基板90係類似於圖3A中之圖案化的基板30，但SiCOH層304已由複數介電層取代。該複數介電層可為低k層。在此示例中，SiCOH層304已由第一介電層316、蝕刻停止層318、及第二介電層320取代。第一介電層316及第二介電層320可具有不同的化學組成及密度，從而顯示不同的蝕刻行為。SiOx 膜309的形成可用以改善蝕刻進圖案化的基板90中之圖案（例如貫孔、溝槽）的輪廓，包含使較軟（較低密度）與較硬（較高密度）介電層間之弓形部（bowing）或底切最小化。
圖5A-5F根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法。該方法包含藉由氣相蝕刻在圖案化的基板50中形成貫孔303、移除OPL 312（圖5B）、將圖案化的基板50曝露於基於氧的灰化製程以在介電硬遮罩306、SiCOH層304、及蝕刻停止層302（圖5C）的表面上產生Si-OH表面終端305。Si-OH表面終端305係藉由曝露於矽烷化試劑矽烷化以在貫孔303中的介電硬遮罩306、SiCOH層304、及蝕刻停止層302上形成SiOx 膜307（圖5D）。可重複處理以形成SiOx 膜309（圖5E）。之後，可執行溝槽蝕刻製程以形成溝槽311及將貫孔303延伸穿過蝕刻停止層302至金屬線301（圖5F）。
圖6A-6E根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法。該方法包含執行圖案化的基板60之溝槽硬遮罩圖案化（圖6A）、執行溝槽蝕刻製程以形成溝槽311、及將圖案化的基板60曝露於基於氧的灰化製程以在介電硬遮罩306及SiCOH層304的表面上產生Si-OH表面終端305（圖6B）。Si-OH表面終端305係藉由曝露於矽烷化試劑矽烷化以在介電硬遮罩306及SiCOH層304上形成SiOx 膜307（圖6C）。可重複處理以形成SiOx 膜309（圖6D）。圖6D中之圖案化的基板60可藉由形成填充溝槽311的平坦化層314進一步處理（圖6E）。SiOx 膜309作為阻障層且抑制SiCOH層304與平坦化層314之間的交互作用。平坦化層314可為有機材料或可含有Si之含量。
圖7A-7D根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法。該方法包含執行圖案化的基板70之溝槽硬遮罩圖案化（圖7A）、執行貫孔蝕刻製程以形成貫孔303、執行溝槽蝕刻製程以形成溝槽311、及將圖案化的基板70曝露於基於氧的灰化製程以在介電硬遮罩306及SiCOH層304的表面上產生Si-OH表面終端305（圖7B）。Si-OH表面終端305係藉由曝露於矽烷化試劑矽烷化以在介電硬遮罩306及SiCOH層304上形成SiOx 膜307（圖7C）。可重複處理以形成SiOx 膜309（圖7D）。
多孔低k材料之孔洞密封的示例。
除了能夠藉由交替的表面官能基化及矽烷化在低k材料上沉積薄介電膜（例如SiOx ）之外，本發明的一些實施例可用以密封多孔低k材料的孔洞。
圖8A及8B根據本發明的實施例顯示薄SiOx 膜在多孔低k材料之金屬漂白上之影響的橫剖面TEM影像。圖8A顯示穿過包含金屬的阻障層進入多孔旋塗低k材料的Cu線漂白。阻障層及Cu線係沉積至低k材料中的凹入特徵部內。Cu金屬化製程由於低k材料的脆弱性及孔洞的相互連結性而導致Cu線漂白。在圖8B中，薄SiOx 膜係使用CO2 電漿處理及TMSDMA曝露的10個製程循環選擇性地沉積在低k材料上。此影像顯示薄SiOx 膜之存在能夠密封在表面處的孔洞並形成緻密的表面膜。此薄SiOx 膜最終係能夠耐受阻障金屬沉積及Cu填充製程，並提供良好界定的金屬及低k材料界面而沒有Cu線漂白。此外，圖8A與8B間的另一差異係與圖8B中較小的目標貫孔底部CD相比，圖8A中大的貫孔底部CD。此根據本發明的實施例顯示薄SiOx 膜的益處以減輕低k材料損壞。
根據一實施例，上述製程循環可在兩個不同處理腔室中執行，其中一處理腔室包含配置用於蝕刻介電材料（貫孔及溝槽圖案）的蝕刻腔室。藉由電漿處理（例如包含O2 氣體或CO2 氣體的電漿氧化）之介電材料的表面官能基化步驟亦可在蝕刻腔室中執行。矽烷化步驟可在可為在升高溫度下的另一處理腔室內執行以熱活化矽烷化反應。
根據另一實施例，製程循環可在配置用於執行蝕刻、表面官能基化、及矽烷化的單一製程腔室中執行。
已描述用於處理介電材料之方法的複數實施例。本發明實施例之以上描述已為了說明及描述的目的呈現。其係非意欲為詳盡的或將本發明限制於所揭示的確切形式。此描述及以下申請專利範圍包含僅用於描述性目的而非非被理解為限制性的術語。精於相關技術之人士可理解，根據上述教示，許多修改及變化是可能的。因此，本發明的範圍係非限於此詳細說明，而是由隨附申請專利範圍限定。
30‧‧‧圖案化的基板
40‧‧‧圖案化的基板
50‧‧‧圖案化的基板
60‧‧‧圖案化的基板
70‧‧‧圖案化的基板
90‧‧‧圖案化的基板
301‧‧‧金屬線
302‧‧‧蝕刻停止層
303‧‧‧貫孔
304‧‧‧SiCOH層
305‧‧‧Si-OH表面終端
306‧‧‧介電硬遮罩
307‧‧‧SiOx膜
308‧‧‧金屬硬遮罩
309‧‧‧SiOx膜
310‧‧‧圖案化的硬遮罩（HM）
311‧‧‧溝槽
312‧‧‧有機平坦化層（OPL）
313‧‧‧角隅
314‧‧‧平坦化層
315‧‧‧角隅
316‧‧‧第一介電層
318‧‧‧蝕刻停止層
320‧‧‧第二介電層
本發明更完整的理解及其中許多伴隨的優點，藉由參照下列詳細的描述與隨附圖示受到更佳理解，其中：
圖1根據本發明之實施例示意性地顯示使介電材料的表面官能基化及使經官能基化的表面矽烷化的方法；
圖2根據本發明的實施例顯示作為製程循環的數目之函數的介電膜厚度；
圖3A-3F根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法；
圖4示意性地顯示圖案化之基板的橫剖面圖；
圖5A-5F根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法；
圖6A-6E根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法；
圖7A-7D根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法；
圖8A及8B根據本發明的實施例顯示薄SiOx 膜在多孔低k材料之金屬漂白上之影響的橫剖面穿透電子顯微術（TEM）影像；及
圖9A及9B根據本發明的實施例透過橫剖面圖示意性地顯示處理圖案化之基板的方法。

Claims (20)

  1. 一種基板處理方法，包含： 提供包含介電材料之圖案化的一基板； 將該基板曝露於氣相電漿以使該介電材料的表面官能基化； 將該基板曝露於與經官能基化之該介電材料之該表面反應的矽烷化試劑以形成介電膜；及 依序重複該等曝露步驟至少一次以增加該介電膜的厚度。
  2. 如申請專利範圍第1項之基板處理方法，其中，該矽烷化試劑具有化學式Rn SiX4-n ，其中R係烷基或官能基鏈，X係OR、NH2 、或NR2 ，且n=0~4。
  3. 如申請專利範圍第1項之基板處理方法，其中，該介電材料之該表面包含貫孔、溝槽、或貫孔及溝槽兩者。
  4. 如申請專利範圍第1項之基板處理方法，其中，該介電材料包含低k材料、SiO2 、SiN、SiCN、SiC、SiCOH、有機矽酸鹽玻璃（OSG）、或碳摻雜氧化物（CDO）。
  5. 如申請專利範圍第1項之基板處理方法，其中，該氣相電漿係基於N2 、基於N2 /H2 、基於O2 、基於CO2 、基於COS、基於NH3 、基於H2 、或基於H2 O。
  6. 如申請專利範圍第1項之基板處理方法，其中，經官能基化之該介電材料之該表面包含-OH物種、-NH物種、或-SH物種。
  7. 如申請專利範圍第1項之基板處理方法，其中，該矽烷化試劑包含烷基胺矽烷。
  8. 如申請專利範圍第1項之基板處理方法，其中，該矽烷化試劑包含二甲基矽烷二甲胺（DMSDMA）、三甲基矽烷二甲胺（TMSDMA）、雙（二甲胺基）二甲基矽烷（BDMADMS）、或四甲基二矽氮烷（TMDS）。
  9. 如申請專利範圍第1項之基板處理方法，其中，該介電膜包含SiOx 、SiNx 、SiOx Ny 、或其組合。
  10. 如申請專利範圍第1項之基板處理方法，其中，該介電材料包含多孔低k材料，且該介電膜將經官能基化之該多孔低k材料之表面上的孔洞密封。
  11. 一種基板處理方法，包含： 提供包含SiCOH層之圖案化的一基板； 將該基板曝露於基於O2 或基於CO2 的氣相電漿以使該SiCOH層的表面官能基化； 將該基板曝露於與經官能基化之該SiCOH層之該表面反應的矽烷化試劑以形成SiOx 膜；及 依序重複該等曝露步驟至少一次以增加該SiOx 膜的厚度。
  12. 如申請專利範圍第11項之基板處理方法，其中，該矽烷化試劑具有化學式Rn SiX4-n ，其中R係烷基或官能基鏈，X係OR、NH2 、或NR2 ，且n=0~4。
  13. 如申請專利範圍第11項之基板處理方法，其中，該SiCOH層之該表面包含貫孔、溝槽、或貫孔及溝槽兩者。
  14. 如申請專利範圍第11項之基板處理方法，其中，經官能基化之該SiCOH層之該表面包含-OH物種。
  15. 如申請專利範圍第11項之基板處理方法，其中，該矽烷化試劑包含二甲基矽烷二甲胺（DMSDMA）、三甲基矽烷二甲胺（TMSDMA）、雙（二甲胺基）二甲基矽烷（BDMADMS）、或四甲基二矽氮烷（TMDS）。
  16. 一種基板處理方法，包含： 提供包含多孔低k材料之圖案化的一基板； 將該基板曝露於基於O2 或基於CO2 的氣相電漿以使該多孔低k材料的表面官能基化； 將該基板曝露於與經官能基化之該多孔低k材料之該表面反應的矽烷化試劑以形成介電膜；及 依序重複該等曝露步驟至少一次以增加該介電膜的厚度。
  17. 如申請專利範圍第16項之基板處理方法，其中，該矽烷化試劑具有化學式Rn SiX4-n ，其中R係烷基或官能基鏈，X係OR、NH2 、或NR2 ，且n=0~4。
  18. 如申請專利範圍第16項之基板處理方法，其中，該介電膜將經官能基化之該多孔低k材料之該表面上的孔洞密封。
  19. 如申請專利範圍第16項之基板處理方法，其中，該矽烷化試劑包含烷基胺矽烷。
  20. 如申請專利範圍第16項之基板處理方法，其中，該矽烷化試劑包含二甲基矽烷二甲胺（DMSDMA）、三甲基矽烷二甲胺（TMSDMA）、雙（二甲胺基）二甲基矽烷（BDMADMS）、或四甲基二矽氮烷（TMDS）。
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