JP5449189B2 - low−k誘電体の気相修復及び細孔シーリング - Google Patents
low−k誘電体の気相修復及び細孔シーリング Download PDFInfo
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- JP5449189B2 JP5449189B2 JP2010539431A JP2010539431A JP5449189B2 JP 5449189 B2 JP5449189 B2 JP 5449189B2 JP 2010539431 A JP2010539431 A JP 2010539431A JP 2010539431 A JP2010539431 A JP 2010539431A JP 5449189 B2 JP5449189 B2 JP 5449189B2
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- alkoxysilane
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02343—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a liquid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Description
実施例1
実施例2
実施例3
適用例1:半導体基板上に形成されたナノポーラスlow−k(低誘電率)誘電体の処理方法であって、前記low−k誘電体は、エッチング処理により形成された開口部であって、前記エッチング処理により形成された開口部の外表面上および連通孔の内表面上に、シラノール基を含むエッチングによる損傷領域を有する開口部を備え、前記方法は、(a)前記low−k誘電体を、前記エッチングによる損傷領域において気相触媒と前記シラノール基との間に水素結合を形成するのに有効な量の前記気相触媒に接触させて、触媒中間体を形成する工程と、これに続き、(b)前記low−k誘電体を、前記エッチングによる損傷領域において約50%以上のシラノール基と反応するのに有効な量のアルコキシシラン修復剤と接触させることにより、前記アルコキシシラン修復剤を前記触媒中間体と反応させる工程、及び/又は、(c)前記low−k誘電体を、前記連通孔内への被覆バリア層の拡散を防ぐのに有効な量のアルコシキシランシール剤と接触させることにより、前記アルコシキシランシール剤を前記触媒中間体と反応させる工程と、を備える、方法。
適用例2:適用例1に記載の方法であって、(i)前記触媒がルイス塩基性アミン又は有機酸であって、(ii)前記工程(c)の前に、前記工程(a)および前記工程(b)を最大で10回繰り返し、(iii)前記シール剤が、前記エッチング処理により形成された開口部の外表面上に、最大で厚さ2nmのアルコシキシラン膜を形成する、及び/又は、前記アルコキシシラン修復剤が約80から約125の原子質量単位を有し、前記アルコキシシランシール剤が約200から約400の原子質量単位を有する、方法。
適用例3:適用例1に記載の方法はさらに、前記工程(c)の前に前記工程(a)を繰り返す工程を備える、方法。
適用例4:適用例2に記載の方法であって、前記ルイス塩基性アミンが、アンモニウム(NH 3 )、メチルアミン(CH 3 NH 2 )、ジメチルアミン((CH 3 ) 2 NH)、若しくはトリメチルアミン(N(CH 3 ) 3 )であり、又は、前記有機酸が、酢酸、トリフルオロ酢酸、トリクロロ酢酸、若しくはクエン酸の水溶液である、方法。
適用例5:適用例2に記載の方法はさらに、前記工程(a)の後で前記工程(b)の前に、前記low−k誘電体から前記有機酸気相触媒を除去し、(i)前記有機酸気相触媒と(ii)前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤との間の気相反応を妨害する工程を備える、方法。
適用例6:適用例5に記載の方法であって、
前記アルコキシシラン修復剤が、メチルトリメトキシシラン(CH 3 −Si−(O−CH 3 ) 3 )、ジメトキシジメチルシラン((CH 3 ) 2 −Si−(OCH 3 ) 2 )、メトキシトリメチルシラン((CH 3 ) 3 −Si−OCH 3 )、又はn−プロピルトリメトキシシラン(CH 3 −CH 2 −CH 2 −Si−(OCH 3 ) 3 )であり、前記アルコキシシランシール剤が、ビス(ジメトキシメチル)シロキサン、ビス(メチルジメトキシシリルプロピル)−N−メチルアミン、ビス(トリエトシキシリル)エタン、1,2−ビス(トリメトキシシリル)ヘキサン、ビス(トリメトキシシリルプロピル)アミン、又はビス(3−(トリエトキシシリル)プロピル)ジスルフィドである、方法。
適用例7:適用例1に記載の方法であって、前記low−k誘電体を前記気相触媒に接触させる前記工程(a)は、前記半導体基板を処理チャンバ内に設置し、前記処理チャンバを排気する工程と、前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、前記触媒を、約20トールから約1500トールの範囲の圧力で、約10秒から約60秒の範囲の時間、前記チャンバに導入する工程と、前記チャンバを排気する工程と、を備える、方法。
適用例8:適用例7に記載の方法であって、前記第1の温度が約100℃から約200℃の範囲であり、前記圧力が約100トールから約760トールの範囲であり、前記時間が約20秒から約30秒の範囲である、方法。
適用例9:適用例7に記載の方法であって、前記low−k誘電体を前記気相修復剤に接触させる前記工程(b)及び/又は前記low−k誘電体を前記気相シール剤に接触させる前記工程(c)は、前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、前記アルコキシシラン修復剤又は前記アルコキシシランシール剤を、約20トールから約1500トールの範囲の圧力で、約10秒から約180秒の範囲の時間、前記チャンバに導入する工程と、前記チャンバを排気する工程と、を備える、方法。
適用例10:適用例9に記載の方法であって、前記第1の温度が約100℃から約200℃の範囲であり、前記圧力が約100トールから約760トールの範囲であり、前記時間が約20秒から約60秒の範囲である、方法。
適用例11:適用例9に記載の方法であって、前記low−k誘電体を前記気相修復剤に接触させる前記工程(b)及び/又は前記low−k誘電体を前記気相シール剤に接触させる前記工程(c)は、前記チャンバを排気する前に、前記半導体基板を約80℃から約300℃の範囲の第2の温度まで、約10秒から約180秒の範囲の追加の時間、加熱する工程と、前記チャンバを排気した後、前記半導体基板を前記第2の温度で、約10秒間から約180秒間保持する工程と、を備える、方法。
適用例12:適用例11に記載の方法であって、前記第2の温度が約150℃から約250℃の範囲であり、前記追加の時間が約20秒から約60秒の範囲である、方法。
適用例13:適用例7に記載の方法はさらに、(d)前記low−k誘電体を、前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤の水平ネットワークを形成するのに有効な量の有機酸気相触媒に接触させる工程と、(e)前記low−k誘電体を、前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤の水平ネットワークを形成するのに有効な温度まで加熱する工程と、を備える、方法。
適用例14:適用例13に記載の方法であって、前記low−k誘電体を、前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤の水平ネットワークを形成するのに有効な量の有機酸気相触媒に接触させる前記工程(d)は、前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、前記有機酸気相触媒を、約20トールから約1500トールの範囲の圧力で、約10秒から約60秒の範囲の時間、前記チャンバに導入する工程と、前記チャンバを排気する工程と、を備える、方法。
適用例15:適用例13に記載の方法であって、前記low−k誘電体を、前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤の水平ネットワークを形成するのに有効な温度まで加熱する前記工程(e)は、前記半導体基板を、前記チャンバ内で、約200℃から約300℃の範囲の温度まで、約60秒間から約180秒間加熱する工程、又は前記半導体基板を前記チャンバから取り出して、前記半導体基板をホットプレート上に置き、前記半導体基板を、約200℃から約300℃の範囲の温度まで、約60秒間から約180秒間加熱する工程、を備える、方法。
適用例16:半導体基板上に形成されたナノポーラスlow−k(低誘電率)誘電体の処理方法であって、前記low−k誘電体は、エッチング処理により形成された開口部であって、前記エッチング処理により形成された開口部の外表面上および連通孔の内表面上に、シラノール基を含むエッチングによる損傷領域を有する開口部を備え前記方法は、(a)前記low−k誘電体を、前記エッチングによる損傷領域において気相有機酸触媒と前記シラノール基との間に水素結合を形成するのに有効な量の前記気相有機酸触媒に接触させて、触媒中間体を形成する工程と、これに続き、(b)前記low−k誘電体を、前記エッチングによる損傷領域において約50%以上のシラノール基と反応するのに有効な量のアルコキシシラン修復剤と接触させることにより、前記アルコキシシラン修復剤を前記触媒中間体と反応させる工程、及び/又は、(c)前記low−k誘電体を、前記連通孔内への被覆バリア層の拡散を防ぐのに有効な量のアルコシキシランシール剤と接触させることにより、前記アルコシキシランシール剤を前記触媒中間体と反応させる工程と、を備える、方法。
適用例17:適用例16に記載の方法であって、前記有機酸が、酢酸、トリフルオロ酢酸、トリクロロ酢酸、又はクエン酸の水溶液である、方法。
適用例18:適用例16に記載の方法であって、前記アルコキシシラン修復剤が、メチルトリメトキシシラン(CH 3 −Si−(O−CH 3 ) 3 )、ジメトキシジメチルシラン((CH 3 ) 2 −Si−(OCH 3 ) 2 )、メトキシトリメチルシラン((CH 3 ) 3 −Si−OCH 3 )、又はn−プロピルトリメトキシシラン(CH 3 −CH 2 −CH 2 −Si−(OCH 3 ) 3 )であり、前記アルコキシシランシール剤が、ビス(ジメトキシメチル)シロキサン、ビス(メチルジメトキシシリルプロピル)−N−メチルアミン、ビス(トリエトシキシリル)エタン、1,2−ビス(トリメトキシシリル)ヘキサン、ビス(トリメトキシシリルプロピル)アミン、又はビス(3−(トリエトキシシリル)プロピル)ジスルフィドである、方法。
適用例19:適用例16に記載の方法であって、前記low−k誘電体を前記気相有機酸触媒に接触させる前記工程(a)は、前記半導体基板を処理チャンバ内に設置し、前記処理チャンバを排気する工程と、前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、前記気相有機酸触媒を、約20トールから約1500トールの範囲の圧力で、約10秒から約60秒の範囲の時間、前記チャンバに導入する工程と、
前記チャンバを排気する工程と、を備える、方法。
適用例20:適用例16に記載の方法は、さらに、(d)前記low−k誘電体を、前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤の水平ネットワークを形成するのに有効な量の有機酸気相触媒に接触させる工程と、(e)前記low−k誘電体を、前記アルコキシシラン修復剤及び/又は前記アルコキシシランシール剤の水平ネットワークを形成するのに有効な温度まで加熱する工程と、を備える、方法。
Claims (19)
- 半導体基板上に形成されたナノポーラスlow−k(低誘電率)誘電体の処理方法であって、
前記low−k誘電体は、エッチング処理により形成された開口部であって、前記エッチング処理により形成された開口部の外表面上および連通孔の内表面上に、シラノール基を含むエッチングによる損傷領域を有する開口部を備え、
前記方法は、
(a)前記low−k誘電体を、前記エッチングによる損傷領域において気相触媒と前記シラノール基との間に水素結合を形成するのに有効な量の前記気相触媒に接触させて、触媒中間体を形成する工程と、これに続き、
(b)前記low−k誘電体を、前記エッチングによる損傷領域において約50%以上のシラノール基と反応するのに有効な量のアルコキシシラン修復剤と接触させることにより、前記アルコキシシラン修復剤を前記触媒中間体と反応させる工程、及び、
(c)前記low−k誘電体を、前記連通孔内への被覆バリア層の拡散を防ぐのに有効な量のアルコシキシランシール剤と接触させることにより、前記アルコシキシランシール剤を前記触媒中間体と反応させる工程、
を備え、
(i)前記触媒がルイス塩基性アミン又は有機酸であって、
(ii)前記工程(c)の前に、前記工程(a)および前記工程(b)を最大で10回繰り返し、
(iii)前記シール剤は、前記エッチング処理により形成された開口部の外表面上に、最大で厚さ2nmのアルコシキシラン膜を形成するシール剤、及び、前記アルコキシシラン修復剤が約80から約125の原子質量単位を有し、前記アルコキシシランシール剤が約200から約400の原子質量単位を有するシール剤、の少なくともいずれか一方である、方法。 - 請求項1に記載の方法はさらに、前記工程(c)の前に前記工程(a)を繰り返す工程を備える、方法。
- 請求項1に記載の方法であって、
前記ルイス塩基性アミンが、アンモニウム(NH3)、メチルアミン(CH3NH2)、ジメチルアミン((CH3)2NH)、若しくはトリメチルアミン(N(CH3)3)であり、又は、前記有機酸が、酢酸、トリフルオロ酢酸、トリクロロ酢酸、若しくはクエン酸の水溶液である、方法。 - 請求項1に記載の方法はさらに、前記工程(a)の後で前記工程(b)の前に、前記low−k誘電体から前記有機酸気相触媒を除去し、(i)前記有機酸気相触媒と(ii)前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方との間の気相反応を妨害する工程を備える、方法。
- 請求項4に記載の方法であって、
前記アルコキシシラン修復剤が、メチルトリメトキシシラン(CH3−Si−(O−CH3)3)、ジメトキシジメチルシラン((CH3)2−Si−(OCH3)2)、メトキシトリメチルシラン((CH3)3−Si−OCH3)、又はn−プロピルトリメトキシシラン(CH3−CH2−CH2−Si−(OCH3)3)であり、前記アルコキシシランシール剤が、ビス(ジメトキシメチル)シロキサン、ビス(メチルジメトキシシリルプロピル)−N−メチルアミン、ビス(トリエトシキシリル)エタン、1,2−ビス(トリメトキシシリル)ヘキサン、ビス(トリメトキシシリルプロピル)アミン、又はビス(3−(トリエトキシシリル)プロピル)ジスルフィドである、方法。 - 請求項1に記載の方法であって、
前記low−k誘電体を前記気相触媒に接触させる前記工程(a)は、
前記半導体基板を処理チャンバ内に設置し、前記処理チャンバを排気する工程と、
前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、
前記触媒を、約20トールから約1500トールの範囲の圧力で、約10秒から約60秒の範囲の時間、前記チャンバに導入する工程と、
前記チャンバを排気する工程と、
を備える、方法。 - 請求項6に記載の方法であって、
前記第1の温度が約100℃から約200℃の範囲であり、前記圧力が約100トールから約760トールの範囲であり、前記時間が約20秒から約30秒の範囲である、方法。 - 請求項6に記載の方法であって、
前記low−k誘電体を前記気相修復剤に接触させる前記工程(b)及び前記low−k誘電体を前記気相シール剤に接触させる前記工程(c)の少なくともいずれか一方は、
前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、
前記アルコキシシラン修復剤又は前記アルコキシシランシール剤を、約20トールから約1500トールの範囲の圧力で、約10秒から約180秒の範囲の時間、前記チャンバに導入する工程と、
前記チャンバを排気する工程と、を備える、方法。 - 請求項8に記載の方法であって、
前記第1の温度が約100℃から約200℃の範囲であり、前記圧力が約100トールから約760トールの範囲であり、前記時間が約20秒から約60秒の範囲である、方法。 - 請求項8に記載の方法であって、
前記low−k誘電体を前記気相修復剤に接触させる前記工程(b)及び前記low−k誘電体を前記気相シール剤に接触させる前記工程(c)の少なくともいずれか一方は、
前記チャンバを排気する前に、前記半導体基板を約80℃から約300℃の範囲の第2の温度まで、約10秒から約180秒の範囲の追加の時間、加熱する工程と、
前記チャンバを排気した後、前記半導体基板を前記第2の温度で、約10秒間から約180秒間保持する工程と、を備える、
方法。 - 請求項10に記載の方法であって、
前記第2の温度が約150℃から約250℃の範囲であり、前記追加の時間が約20秒から約60秒の範囲である、方法。 - 請求項6に記載の方法はさらに、
(d)前記low−k誘電体を、前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方の水平ネットワークを形成するのに有効な量の有機酸気相触媒に接触させる工程と、
(e)前記low−k誘電体を、前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方の水平ネットワークを形成するのに有効な温度まで加熱する工程と、を備える、方法。 - 請求項12に記載の方法であって、
前記low−k誘電体を、前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方の水平ネットワークを形成するのに有効な量の有機酸気相触媒に接触させる前記工程(d)は、
前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、
前記有機酸気相触媒を、約20トールから約1500トールの範囲の圧力で、約10秒から約60秒の範囲の時間、前記チャンバに導入する工程と、
前記チャンバを排気する工程と、を備える、方法。 - 請求項12に記載の方法であって、
前記low−k誘電体を、前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方の水平ネットワークを形成するのに有効な温度まで加熱する前記工程(e)は、
前記半導体基板を、前記チャンバ内で、約200℃から約300℃の範囲の温度まで、約60秒間から約180秒間加熱する工程、又は
前記半導体基板を前記チャンバから取り出して、前記半導体基板をホットプレート上に置き、前記半導体基板を、約200℃から約300℃の範囲の温度まで、約60秒間から約180秒間加熱する工程、
を備える、方法。 - 半導体基板上に形成されたナノポーラスlow−k(低誘電率)誘電体の処理方法であって、前記low−k誘電体は、エッチング処理により形成された開口部であって、前記エッチング処理により形成された開口部の外表面上および連通孔の内表面上に、シラノール基を含むエッチングによる損傷領域を有する開口部を備え前記方法は、
(a)前記low−k誘電体を、前記エッチングによる損傷領域において気相有機酸触媒と前記シラノール基との間に水素結合を形成するのに有効な量の前記気相有機酸触媒に接触させて、触媒中間体を形成する工程と、これに続き、
(b)前記low−k誘電体を、前記エッチングによる損傷領域において約50%以上のシラノール基と反応するのに有効な量のアルコキシシラン修復剤と接触させることにより、前記アルコキシシラン修復剤を前記触媒中間体と反応させる工程、及び、
(c)前記low−k誘電体を、前記連通孔内への被覆バリア層の拡散を防ぐのに有効な量のアルコシキシランシール剤と接触させることにより、前記アルコシキシランシール剤を前記触媒中間体と反応させる工程、を備え、
(i)前記触媒がルイス塩基性アミン又は有機酸であって、
(ii)前記工程(c)の前に、前記工程(a)および前記工程(b)を最大で10回繰り返し、
(iii)前記シール剤は、前記エッチング処理により形成された開口部の外表面上に、最大で厚さ2nmのアルコシキシラン膜を形成するシール剤、及び前記アルコキシシラン修復剤が約80から約125の原子質量単位を有し、前記アルコキシシランシール剤が約200から約400の原子質量単位を有するシール剤、の少なくともいずれか一方である、方法。 - 請求項15に記載の方法であって、
前記有機酸が、酢酸、トリフルオロ酢酸、トリクロロ酢酸、又はクエン酸の水溶液である、方法。 - 請求項15に記載の方法であって、
前記アルコキシシラン修復剤が、メチルトリメトキシシラン(CH3−Si−(O−CH3)3)、ジメトキシジメチルシラン((CH3)2−Si−(OCH3)2)、メトキシトリメチルシラン((CH3)3−Si−OCH3)、又はn−プロピルトリメトキシシラン(CH3−CH2−CH2−Si−(OCH3)3)であり、前記アルコキシシランシール剤が、ビス(ジメトキシメチル)シロキサン、ビス(メチルジメトキシシリルプロピル)−N−メチルアミン、ビス(トリエトシキシリル)エタン、1,2−ビス(トリメトキシシリル)ヘキサン、ビス(トリメトキシシリルプロピル)アミン、又はビス(3−(トリエトキシシリル)プロピル)ジスルフィドである、方法。 - 請求項15に記載の方法であって、
前記low−k誘電体を前記気相有機酸触媒に接触させる前記工程(a)は、
前記半導体基板を処理チャンバ内に設置し、前記処理チャンバを排気する工程と、
前記半導体基板を約60℃から約275℃の範囲の第1の温度まで加熱する工程と、
前記気相有機酸触媒を、約20トールから約1500トールの範囲の圧力で、約10秒から約60秒の範囲の時間、前記チャンバに導入する工程と、
前記チャンバを排気する工程と、を備える、方法。 - 請求項15に記載の方法は、さらに、
(d)前記low−k誘電体を、前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方の水平ネットワークを形成するのに有効な量の有機酸気相触媒に接触させる工程と、
(e)前記low−k誘電体を、前記アルコキシシラン修復剤及び前記アルコキシシランシール剤の少なくともいずれか一方の水平ネットワークを形成するのに有効な温度まで加熱する工程と、を備える、方法。
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US6670022B1 (en) * | 1997-04-17 | 2003-12-30 | Honeywell International, Inc. | Nanoporous dielectric films with graded density and process for making such films |
US6455130B1 (en) * | 1997-04-17 | 2002-09-24 | Alliedsignal Inc. | Nanoporous dielectric films with graded density and process for making such films |
TW525268B (en) * | 1998-03-25 | 2003-03-21 | Honeywell Int Inc | Nanoporous dielectric films with graded density and process for making such films |
US6495479B1 (en) * | 2000-05-05 | 2002-12-17 | Honeywell International, Inc. | Simplified method to produce nanoporous silicon-based films |
US20030054115A1 (en) | 2001-09-14 | 2003-03-20 | Ralph Albano | Ultraviolet curing process for porous low-K materials |
AU2002357645A1 (en) | 2002-09-20 | 2004-04-08 | Honeywell International, Inc. | Interlayer adhesion promoter for low k materials |
US7553769B2 (en) * | 2003-10-10 | 2009-06-30 | Tokyo Electron Limited | Method for treating a dielectric film |
US7678712B2 (en) | 2005-03-22 | 2010-03-16 | Honeywell International, Inc. | Vapor phase treatment of dielectric materials |
US7807219B2 (en) * | 2006-06-27 | 2010-10-05 | Lam Research Corporation | Repairing and restoring strength of etch-damaged low-k dielectric materials |
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