TW201724447A - 薄型扇出式多晶片堆疊封裝構造及其製造方法 - Google Patents

薄型扇出式多晶片堆疊封裝構造及其製造方法 Download PDF

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TW201724447A
TW201724447A TW104143312A TW104143312A TW201724447A TW 201724447 A TW201724447 A TW 201724447A TW 104143312 A TW104143312 A TW 104143312A TW 104143312 A TW104143312 A TW 104143312A TW 201724447 A TW201724447 A TW 201724447A
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wafer
bumps
fan
flip chip
package structure
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TW104143312A
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TWI604591B (zh
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方立志
張家維
林國鼎
莊詠程
袁家祥
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力成科技股份有限公司
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Priority to TW104143312A priority Critical patent/TWI604591B/zh
Priority to US15/383,560 priority patent/US9761568B2/en
Publication of TW201724447A publication Critical patent/TW201724447A/zh
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Publication of TWI604591B publication Critical patent/TWI604591B/zh

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Abstract

揭示一種薄型扇出式多晶片堆疊封裝構造。晶片堆疊體主要由複數個晶片堆疊所組成，晶片之電極與其中一主動面不被晶片堆疊覆蓋。虛置覆晶之複數個柱狀凸塊接合至該未覆蓋主動面之電極。封膠體密封晶片堆疊體與柱狀凸塊，封膠體具有一平坦面，鄰近於未覆蓋主動面，以使虛置覆晶之主體被移除並且殘留之柱狀凸塊具有複數個接合面，共平面顯露於平坦面。而重配置線路結構形成於平坦面上並且包含之扇出線路連接至柱狀凸塊之接合面。因此，可以提高縱向導通元件之抗模流衝擊力，以有效降低沖線的風險。

Description

薄型扇出式多晶片堆疊封裝構造及其製造方法
本發明係有關於半導體晶片封裝領域，特別係有關於一種薄型扇出式多晶片堆疊封裝構造及其製造方法。
在習知的多晶片堆疊封裝構造中，複數個半導體晶片逐一往上堆疊在一基板上，並且該些晶片之主動面係朝上，並以打線形成之銲線電性連接該些晶片至該基板。然而，以此種方式形成的多晶片堆疊封裝構造之厚度包含了基板厚度與打線弧高而無法降低，並且特別在需要長銲線的場合，在形成封膠體時，容易發生沖線而產生短路等問題。
為了節省基板之厚度，有人提出將扇出式晶圓等級封裝技術運用在多晶片堆疊封裝構造中，相關專利前案可參見於PCT國際專利公開編號WO 2015/042886 A1「Method for interconnecting stacked semiconductor devices」。在一晶圓上堆疊晶片，以封膠體模封已堆疊好之多晶片，再以重配置線路結構取代習知的基板。而封膠體內必須製作電性連接晶片銲墊與重配置線路結構的縱向導通元件，例如模封導通孔(Through Mold Via,TMV)或是垂直銲線，模封導通孔係對封膠體鑽孔以連通到銲墊 再電鍍上孔內金屬層，由於鑽孔深度不一且鑽孔間距必須配合銲墊間距，故導致了生產良率的降低與封裝製程難度的提高。另，關於垂直銲線應用薄型扇出式多晶片堆疊封裝構造中，在模封時，垂直銲線的一端為懸浮，更容易發生沖線而導致垂直銲線的歪斜。
為了解決上述之問題，本發明之主要目的係在於提供一種薄型扇出式多晶片堆疊封裝構造及其製造方法，以已預先成型於虛置覆晶之柱狀凸塊來取代習知使用打線機以打線形成之銲線，以連接晶片銲墊與重配置線路結構。如此，可以提高縱向導通元件之抗模流衝擊力，以有效降低沖線的風險，不僅縱向導通元件可維持較好的垂直度，而且縱向導通元件的形狀與間距也可以得到良好的控制。
本發明之次一目的係在於提供一種薄型扇出式多晶片堆疊封裝構造及其製造方法，以已預先成型於虛置覆晶之柱狀凸塊來取代習知模封導通孔，以連接晶片銲墊與重配置線路結構。在製造上排除了鑽孔深度不一且鑽孔間距必須配合銲墊間距與高深寬比孔內難以電鍍的問題，故生產良率可以提高、封裝製程難度可以降低。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種薄型扇出式多晶片堆疊封裝構造，包含一晶片堆疊體、一第一虛置覆晶之複數個第一柱狀凸塊、一 封膠體以及一重配置線路結構。該晶片堆疊體主要係由複數個晶片堆疊所組成，每一晶片係具有一主動面以及複數個位於該主動面之電極，該些電極係不被該些晶片堆疊覆蓋，其中一主動面係亦不被該些晶片堆疊覆蓋。該第一虛置覆晶之該些第一柱狀凸塊係至少接合至上述未堆疊覆蓋之主動面之該些電極。該封膠體係密封該晶片堆疊體與該些第一柱狀凸塊，該封膠體係具有一平坦面，該平坦面係鄰近於上述未堆疊覆蓋之主動面，以使該第一虛置覆晶之主體被移除並且殘留之該些第一柱狀凸塊係具有複數個接合面，其係共平面顯露於該平坦面。該重配置線路結構係形成於該平坦面上，該重配置線路結構係包含複數個扇出線路，該些扇出線路係連接至該些第一柱狀凸塊之該些接合面。本發明另揭示上述薄型扇出式多晶片堆疊封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述薄型扇出式多晶片堆疊封裝構造中，該重配置線路結構係可更包含一第一保護層與一第二保護層，其中該第一保護層係可覆蓋於該平坦面，該些扇出線路係可形成於該第一保護層與該第二保護層之間。
在前述薄型扇出式多晶片堆疊封裝構造中，可另包含複數個外接端子，其係可接合於該重配置線路結構上，以電性連接該些扇出線路。
在前述薄型扇出式多晶片堆疊封裝構造中，該些晶 片係可為階梯式錯位堆疊，以不遮蓋該些電極，該些電極係可包含複數個銲墊。
在前述薄型扇出式多晶片堆疊封裝構造中，可另包含一犧牲間隔件，係介設於該平坦面與上述未堆疊覆蓋之主動面之間。
在前述薄型扇出式多晶片堆疊封裝構造中，該犧牲間隔件係可為一板材，其係可選自於虛晶片與金屬片之其中之一，並且該犧牲間隔件係可具有一共平面於該平坦面之研磨面，該第一保護層係更覆蓋於該研磨面。
在前述薄型扇出式多晶片堆疊封裝構造中，該些第一柱狀凸塊係可包含複數個導體柱，該些第一柱狀凸塊之整列間高度間隔差係可約為該些晶片之晶片貼附單位厚度。
在前述薄型扇出式多晶片堆疊封裝構造中，可另包含至少一第二虛置覆晶，係設有複數個第二柱狀凸塊，係可接合至其餘晶片之該些電極，而該第二虛置覆晶係具有複數個橫向貼附於其主體之導通路徑，以電性連接該些第二柱狀凸塊，並且該封膠體係更密封該第二虛置覆晶與該些第二柱狀凸塊。
藉由上述的技術手段，本發明可以達成薄型扇出式多晶片堆疊封裝構造中封膠體內縱向導通元件的結構改善，對於多晶片堆疊的銲墊與該重配置線路結構有更好的電性導通方式。相對於垂直銲線，垂直度較好且不會有線長過長造成的問題，降低了模封沖線(wire sweep)的風險。在一較佳變化例中，更可以 不需要增加虛置板(dummy plate)或額外打線的截線空間，也可以應用在寬I/O(wide I/O)規格的記憶體介面。
10‧‧‧暫時載板
20‧‧‧暫時載板
30‧‧‧載板
31‧‧‧載體平面
100‧‧‧薄型扇出式多晶片堆疊封裝構造
110‧‧‧晶片堆疊體
111‧‧‧晶片
112‧‧‧主動面
112A‧‧‧未堆疊覆蓋之主動面
113‧‧‧電極
114‧‧‧晶片貼附層
120‧‧‧第一虛置覆晶
120A‧‧‧接合面
121‧‧‧主體
122~129‧‧‧第一柱狀凸塊
130‧‧‧封膠體
131‧‧‧平坦面
140‧‧‧重配置線路結構
141‧‧‧扇出線路
142‧‧‧第一保護層
143‧‧‧第二保護層
150‧‧‧犧牲間隔件
151‧‧‧研磨面
160‧‧‧外接端子
170‧‧‧銲料
200‧‧‧薄型扇出式多晶片堆疊封裝構造
280‧‧‧第二虛置覆晶
281‧‧‧主體
282、283‧‧‧第二柱狀凸塊
284‧‧‧導通路徑
300‧‧‧多晶片堆疊封裝構造
310‧‧‧晶片堆疊體
311A、311B‧‧‧晶片
312‧‧‧主動面
313‧‧‧電極
314‧‧‧晶片貼附層
320‧‧‧虛置覆晶
321‧‧‧主體
322、323‧‧‧柱狀凸塊
322A、323A‧‧‧第一端部
322B、323B‧‧‧第二端部
324‧‧‧銲料
325‧‧‧間隔維持凸塊
326‧‧‧銲料
330‧‧‧封膠體
331‧‧‧被降低表面
第1圖：依據本發明之第一具體實施例，一種薄型扇出式多晶片堆疊封裝構造之截面示意圖。
第2A至2G圖：依據本發明之第一具體實施例，繪示在該薄型扇出式多晶片堆疊封裝構造之製造方法中各主要步驟之元件截面示意圖。
第3圖：依據本發明之第一具體實施例，繪示在對應第2B圖步驟中所使用的第一虛置覆晶之元件截面示意圖。
第4圖：依據本發明之第二具體實施例，另一種薄型扇出式多晶片堆疊封裝構造之截面示意圖。
第5A至5E圖：依據本發明之第二具體實施例，繪示在該薄型扇出式多晶片堆疊封裝構造之製造方法中各主要步驟之元件截面示意圖。
第6圖：依據本發明之第二具體實施例，繪示在對應第5B圖步驟中所使用的第二虛置覆晶之截面示意圖。
第7圖：依據本發明之第三具體實施例，一種多晶片堆疊封裝構造之截面示意圖。
第8A與8B圖：依據本發明之第三具體實施例，繪示在多晶片堆疊封裝構造之製造方法中安裝一虛置覆晶之前與之後之元件 截面示意圖。
以下將配合所附圖示詳細說明本發明之具體實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例，一種薄型扇出式多晶片堆疊封裝構造100舉例說明於第1圖之截面示意圖以及第2A至2G圖其製造方法中各主要步驟之元件截面示意圖，而第3圖係繪示在對應第2B圖步驟中所使用的第一虛置覆晶之元件截面示意圖。該薄型扇出式多晶片堆疊封裝構造100係包含一晶片堆疊體110、一第一虛置覆晶120之複數個第一柱狀凸塊122~129(如第2B與3圖所示)、一封膠體130以及一重配置線路結構140。
該晶片堆疊體110主要係由複數個晶片111堆疊所組成。該些晶片111係為具有記憶體等IC半導體元件。每一晶片111係具有一主動面112以及複數個位於該主動面112之電極113，該些電極113係不被該些晶片111堆疊覆蓋，該些主動面112之其中一主動面112A係亦不被該些晶片111堆疊覆蓋。該主動面112係為積體電路的形成表面，該些電極113係與該晶片111內部 積體電路的金屬內連線(未繪示)電性連接。該些晶片111之背面係可形成有一晶片貼附層114，用以黏接另一鄰近晶片111之主動面112，以構成該晶片堆疊體110。而一個晶片之厚度與一個晶片貼附層之厚度之總和係定義為「晶片貼附單位厚度」。而該些晶片111的堆疊方式可以是階梯堆疊、十字堆疊或塔型堆疊。在本實施例中，該些晶片111係可為階梯式錯位堆疊，以不遮蓋該些電極113，該些電極113係可包含複數個銲墊。當所有主動面112都朝向同一方向時，將會有一個主動面不被該些晶片111堆疊覆蓋，而上述未堆疊覆蓋之主動面係標示為112A。
請參閱第1圖並配合參閱第3圖，該第一虛置覆晶120之該第一柱狀凸塊122係至少接合至上述未堆疊覆蓋之主動面112A之該些電極113，而其餘的第一柱狀凸塊123~129係依序接合至對應晶片111之該些電極113。依據欲接合之晶片堆疊高度，該些第一柱狀凸塊122~129係可為等長亦可不等高。令該些第一柱狀凸塊122~129接合於對應電極113之介質係可為如錫銀(SnAg)材質之銲料170。該些第一柱狀凸塊122~129係可為整列等高、整行等差增高。該些第一柱狀凸塊122可代表第一列的凸塊、該第一柱狀凸塊123可代表第二列的凸塊，往下依序至該第一柱狀凸塊129可代表第八列的凸塊，每一列凸塊可對應至一個晶片111之電極113，同一列的凸塊可為等長，不同列之間的凸塊可為不等長。該些第一柱狀凸塊122~129之材質係可為銅或金等高導電率金屬，可利用電鍍、打線結球等方法形成。在本實施例中， 該些第一柱狀凸塊122~129係可包含複數個導體柱，該些第一柱狀凸塊122~129之整列間高度間隔差係可約為該些晶片111之晶片貼附單位厚度。
再請參閱第1圖，該封膠體130係密封該晶片堆疊體110與該些第一柱狀凸塊122~129。該封膠體130係為熱固型絕緣材料，如絕緣樹脂或模封環氧化合物。並且，該封膠體130係具有一平坦面131，該平坦面131係鄰近於上述未堆疊覆蓋之主動面112A，以使該第一虛置覆晶120之主體121被移除(如第2D與2E圖所示)並且殘留之該些第一柱狀凸塊122~129係具有複數個接合面120A，其係共平面顯露於該平坦面131。在此結構中，上述未堆疊覆蓋之主動面112A係不顯露於該平坦面131。該封膠體130之厚度係應不大於該晶片堆疊體110的堆疊高度之一點二倍，而為薄型封裝形態。
請參閱第1圖，該重配置線路結構140係形成於該平坦面131上，該重配置線路結構140係包含複數個扇出線路141，該些扇出線路141係連接至該些第一柱狀凸塊122~129之該些接合面120A。較佳但非必要地，該重配置線路結構140係可更包含一第一保護層142與一第二保護層143，其中該第一保護層142係可覆蓋於該平坦面131，該些扇出線路141係可形成於該第一保護層142與該第二保護層143之間。故該些扇出線路141可不需要直接形成於該平坦面131。該重配置線路結構140係不同於習知基板之線路層，是利用半導體沉積、電鍍與蝕刻設備予以製作。該些 扇出線路141之結構係可為多層式金屬層，例如鈦/銅/銅(Ti/Cu/Cu)、鈦/銅/銅/鎳/金(Ti/Cu/Cu/Ni/Au)等，其中第一銅層為較薄(約0.2微米)，由沉積形成；第二銅層為較厚(約3微米)，由電鍍形成。也就是說，該些扇出線路141係可包含接合層、晶種層、電鍍層之組合。該些扇出線路141之線路厚度係可控制在不大於10微米，約介於2~6微米。而該第一保護層142與該第二保護層143之結構係可為有機絕緣層，例如聚亞醯胺(PI)，該第一保護層142與該第二保護層143之個別厚度係可約為5微米。故該重配置線路結構140在厚度薄化程度與線路密集度可優於習知基板線路層，當保護層開設孔洞，高覆蓋率的沉積金屬層即可電性連接底層之重配置線路，不僅可以降低線路層的層數，也不需要製作基板鍍通孔之結構。
再請參閱第1圖，該薄型扇出式多晶片堆疊封裝構造100係可另包含複數個外接端子160，例如銲球，其係可接合於該重配置線路結構140上，以電性連接該些扇出線路141。
較佳但非必要地，請參閱第1圖，該薄型扇出式多晶片堆疊封裝構造100係可另包含一犧牲間隔件150，係介設於該平坦面131與上述未堆疊覆蓋之主動面112A之間。該犧牲間隔件150係可為一板材，其係可選自於虛晶片與金屬片之其中之一，並且該犧牲間隔件150係可具有一共平面於該平坦面131之研磨面151，該第一保護層142係更覆蓋於該研磨面151。該犧牲間隔件150之設置係有利於上述未堆疊覆蓋之主動面112A平行於該 封膠體130之該平坦面131並避免上述未堆疊覆蓋之主動面112A受到研磨損害。
第3圖係繪示在對應第2B圖步驟中所使用的第一虛置覆晶之元件截面示意圖。本發明所提供之第一虛置覆晶120係適用於一薄型扇出式多晶片堆疊封裝構造100中，該第一虛置覆晶120係包含一主體121以及複數個突出於該主體121之第一柱狀凸塊122~129，該主體121係選自於虛晶片與金屬片之其中之一，該些第一柱狀凸塊122~129之整列間高度間隔差係匹配於一個晶片貼附單位厚度。
因此，本發明提供一種薄型扇出式多晶片堆疊封裝構造，其中已預先成型於虛置覆晶之柱狀凸塊的間距與長度已預先決定，再以覆晶接合方式接合於不同堆疊高度之晶片銲墊，以作為晶片與重配置線路結構電性導通的媒介。而習知的打線方式形成的垂直銲線，需要額外的截線空間，而且所形成銲線的長度會或長或短且模封時為懸空，因此容易有沖線(wire sweep)的風險。
關於上述薄型扇出式多晶片堆疊封裝構造100之製造方法係配合第2A至2G圖說明如後。
首先，請參閱第2A圖，提供一晶片堆疊體110於一暫時載板10上，該晶片堆疊體110主要係由複數個晶片111堆疊所組成，每一晶片111係具有一主動面112以及複數個位於該主動面112之電極113，該些電極113係不被該些晶片111堆疊覆蓋，其中一主動面112A係亦不被該些晶片111堆疊覆蓋。以主動面112朝上 的方式作該些晶片111之堆疊組合，其中該些晶片111係為階梯式錯位堆疊，以不遮蓋該些電極113，該些電極113係包含複數個銲墊。該暫時載板10係可為一黏性膠帶，亦可為一黏性晶圓載片或是一黏性面板載體。當複數個晶片堆疊體110排列在該暫時載板10上，可模擬為一晶圓或一面板之晶片單元，藉以進行晶圓級或面板級封裝製程。
之後，請參閱第2B、2C與3圖，利用覆晶接合方式設置一第一虛置覆晶120於該晶片堆疊體110上，以使第一虛置覆晶120之該些第一柱狀凸塊122係至少接合至上述未堆疊覆蓋之主動面112A之該些電極113。該第一虛置覆晶120之其餘第一柱狀凸塊123~129係接合至對應晶片111之該些銲墊。接合介質係可為銲料170。該些第一柱狀凸塊122~129係包含複數個導體柱，該些第一柱狀凸塊122~129之整列間高度間隔差係匹配於該些晶片111之晶片貼附單位厚度。此外，如第2C圖所示，在提供該晶片堆疊體110之步驟之後與形成封膠體130之前，另包含：設置一犧牲間隔件150於上述未堆疊覆蓋之主動面112A上。該犧牲間隔件150係為一板材，其係選自於虛晶片與金屬片之其中之一。
之後，請參閱第2D圖，利用壓縮模封或是轉移模封方法形成一封膠體130於該暫時載板10上，該封膠體130係密封該晶片堆疊體110與該些第一柱狀凸塊122~129。在本步驟中，該封膠體130係可更密封該第一虛置覆晶120之主體121。
之後，請參閱第2E圖，研磨該封膠體130，使得該 封膠體130係具有一平坦面131，該平坦面131係鄰近於上述未堆疊覆蓋之主動面112A，以使該第一虛置覆晶120之主體121被移除並且殘留之該些第一柱狀凸塊122~129係具有複數個接合面120A，其係共平面顯露於該平坦面131。在本實施例中，在研磨該封膠體130之步驟之後，該犧牲間隔件150係具有一共平面於該平坦面131之研磨面151。
之後，請參閱第2F與2G圖，可形成一重配置線路結構140於該平坦面131上。如第1圖所示，該重配置線路結構140係包含複數個扇出線路141，該些扇出線路141係連接至該些第一柱狀凸塊122~129之該些接合面120A。該重配置線路結構140係更包含一第一保護層142與一第二保護層143。在第2F圖中，該第一保護層142係覆蓋於該平坦面131，並使其圖案化而顯露出該些接合面120A，該第一保護層142係可更覆蓋於該犧牲間隔件150之該研磨面151；在第2G圖中，該些扇出線路141係形成於該第一保護層142上並連接至該些接合面120A；以後再以該第二保護層143覆蓋該些扇出線路141。如第1圖所示，在完成該重配置線路結構140之後，可接合複數個外接端子160於該重配置線路結構140上，以電性連接該些扇出線路141。最後，經過單體化切割與移除該暫時載板10之步驟，可製作得到如第1圖所示之薄型扇出式多晶片堆疊封裝構造100。
依據本發明之第二具體實施例，另一種薄型扇出式多晶片堆疊封裝構造200舉例說明於第4圖之截面示意圖以及第5A 至5E圖其製造方法中各主要步驟之元件截面示意圖，而第6圖係繪示在對應第5B圖步驟中所使用的第二虛置覆晶之截面示意圖。其中第二具體實施例中與第一具體實施例相同功能的元件將沿用相同圖號。該薄型扇出式多晶片堆疊封裝構造200係包含一晶片堆疊體110、一第一虛置覆晶120之複數個第一柱狀凸塊122~129(如第5B圖所示)、一封膠體130以及一重配置線路結構140。在本實施例中，該薄型扇出式多晶片堆疊封裝構造200係可另包含至少一第二虛置覆晶280，係設有複數個第二柱狀凸塊282、283。
該晶片堆疊體110主要係由複數個晶片111堆疊所組成，每一晶片111係具有一主動面112以及複數個位於該主動面112之電極113，該些電極113係不被該些晶片111堆疊覆蓋，該些主動面112之其中一主動面112A係亦不被該些晶片111堆疊覆蓋。
請參閱第4圖，該第一虛置覆晶120之該第一柱狀凸塊122係至少接合至上述未堆疊覆蓋之主動面112A之該些電極113。該第二虛置覆晶280之該些第二柱狀凸塊282、283係接合至其餘對應晶片111之該些電極113。上述凸塊與電極113的接合介質係可為銲料170。較佳地，該第二虛置覆晶280係具有複數個橫向貼附於其主體281之導通路徑284(如第5C圖所示)，以電性連接該些第二柱狀凸塊282、283。該些第一柱狀凸塊122~129與該些第二柱狀凸塊282、283係可包含複數個導體柱，該些第二柱狀凸塊282、283之整列間高度間隔差係可約為該些晶片111之晶片貼附單位厚度。
再請參閱第4圖，該封膠體130係密封該晶片堆疊體110與該些第一柱狀凸塊122~129，該封膠體130係具有一平坦面131，該平坦面131係鄰近於上述未堆疊覆蓋之主動面112A，以使該第一虛置覆晶120之主體121被移除並且殘留之該些第一柱狀凸塊122~129係具有複數個接合面120A，其係共平面顯露於該平坦面131。並且，在本實施例中，該封膠體130係更密封該第二虛置覆晶280之主體281與該些第二柱狀凸塊282、283。
請參閱第4圖，該重配置線路結構140係形成於該平坦面131上，該重配置線路結構140係包含複數個扇出線路141，該些扇出線路141係連接至該些第一柱狀凸塊122~129之該些接合面120A。該重配置線路結構140係可更包含一第一保護層142與一第二保護層143，其中該第一保護層142係可覆蓋於該平坦面131，該些扇出線路141係可形成於該第一保護層142與該第二保護層143之間。此外，該薄型扇出式多晶片堆疊封裝構造200係可另包含複數個外接端子160，其係可接合於該重配置線路結構140上，以電性連接該些扇出線路141。
請再參閱第4圖，較佳地，該薄型扇出式多晶片堆疊封裝構造200係可另包含一犧牲間隔件150，係介設於該平坦面131與上述未堆疊覆蓋之主動面112A之間。該犧牲間隔件150係可為一板材，其係可選自於虛晶片與金屬片之其中之一，並且該犧牲間隔件150係可具有一共平面於該平坦面131之研磨面151，該第一保護層142係更覆蓋於該研磨面151。
第6圖係繪示在對應第5B圖步驟中所使用的第二虛置覆晶之元件截面示意圖。本發明提供之一第二虛置覆晶280係適用於一薄型扇出式多晶片堆疊封裝構造200中，該第二虛置覆晶280係包含一主體281以及複數個突出於該主體281之第二柱狀凸塊282、283，該主體281係選自於虛晶片與金屬片之其中之一，該些第二柱狀凸塊282、283之整列間高度間隔差係匹配於一個晶片貼附單位厚度。此外，該第二虛置覆晶280係可另包含複數個橫向貼附於該主體281之導通路徑284，以電性連接該些第二柱狀凸塊282、283。
關於上述薄型扇出式多晶片堆疊封裝構造200之製造方法配合第5A至5E圖係說明如後。
首先，請參閱第5A圖，以晶片取放方式提供一晶片堆疊體110於一暫時載板20上，該晶片堆疊體110主要係由複數個晶片111堆疊所組成，每一晶片111係具有一主動面112以及複數個位於該主動面112之電極113，該些電極113係不被該些晶片111堆疊覆蓋，其中一主動面112A係亦不被該些晶片111堆疊覆蓋。較佳地，在提供該晶片堆疊體110之步驟之後與形成一封膠體130之前，另包含：設置一犧牲間隔件150於上述未堆疊覆蓋之主動面112A上。該犧牲間隔件150係為一板材，其係選自於虛晶片與金屬片之其中之一
之後，請參閱第5B圖，以覆晶接合方式設置一第一虛置覆晶120與至少一第二虛置覆晶280於該晶片堆疊體110上， 以使第一虛置覆晶120之該第一柱狀凸塊122係接合至上述未堆疊覆蓋之主動面112A之該些電極113。該些第二柱狀凸塊282、283係接合至其餘晶片111之該些電極113。而該第二虛置覆晶280係具有複數個橫向貼附於其主體281之導通路徑284(如第6圖所示)，以電性連接該些第二柱狀凸塊282、283。
之後，請參閱第5C圖，以模封方式形成一封膠體130於該暫時載板20上，該封膠體130係密封該晶片堆疊體110、該第一虛置覆晶120、該些第一柱狀凸塊122~129、該第二虛置覆晶280以及該些第二柱狀凸塊282、283。該封膠體130係可更密封該犧牲間隔件150。
之後，請參閱第5D圖，研磨該封膠體130，使得該封膠體130係具有一平坦面131，該平坦面131係鄰近於上述未堆疊覆蓋之主動面112A，以使該第一虛置覆晶120之主體121被移除並且殘留之該些第一柱狀凸塊122係具有複數個接合面120A，其係共平面顯露於該平坦面131。在研磨該封膠體130之步驟之後，該犧牲間隔件150係具有一共平面於該平坦面131之研磨面151。
之後，請參閱第5E圖，形成一重配置線路結構140於該平坦面131上，該重配置線路結構140係包含複數個扇出線路141，該些扇出線路141係連接至該些第一柱狀凸塊122~129之該些接合面120A。該重配置線路結構140係更包含一第一保護層142與一第二保護層143，其中該第一保護層142係覆蓋於該平坦 面131，該些扇出線路141係形成於該第一保護層142與該第二保護層143之間。該第一保護層142係更覆蓋於該研磨面151。
在形成該重配置線路結構140之步驟之後，可另包含：接合複數個外接端子160於該重配置線路結構140上，以電性連接該些扇出線路141。
之後，移除該暫時載板20。經過單體化切割之後，可製造得到如第4圖所示之薄型扇出式多晶片堆疊封裝構造200。
因此，本發明提供另一種薄型扇出式多晶片堆疊封裝構造，其中該些第一柱狀凸塊122~129與該些第二柱狀凸塊282、283係已預先成型為所要的形狀與長度，作為晶片對重配置線路結構140以及晶片之間電性連接的媒介。不像傳統的打線方式，所形成弧形銲線的長度會較長，因此容易有沖線的風險。
依據本發明之第三具體實施例，一種多晶片堆疊封裝構造300舉例說明於第7圖之截面示意圖以及第8A至8B圖其製造方法中安裝一虛置覆晶之前與之後之元件截面示意圖，其中對應於第一具體實施例相同名稱與功能之元件以第一具體實施例的元件圖號表示，相同細部特徵不再贅述。一種多晶片堆疊封裝構造300係包含一晶片堆疊體310、一虛置覆晶320之複數個柱狀凸塊322、323以及一封膠體330。
請參閱第7圖，該晶片堆疊體310主要係由複數個晶片311A、311B堆疊所組成並位於一載體平面31上。該載體平面31係可由一載板30提供，而該載板30係可為一散熱片、一虛晶片 或一膠膜，在本實施例中，該載板30係為一金屬散熱片，該載板30在最終封裝產品中係依不同需求可為剝離或不剝離，若應用於3D封裝堆疊(POP)，該載板30應被剝離；若應用於高導熱型封裝，該載板30應不被剝離。每一晶片311A與311B係各具有一主動面312以及複數個位於該主動面312之電極313，該些電極313係不被該些晶片311A、311B堆疊覆蓋，該些電極313係依據所屬晶片311A、311B之不同而具有在該載體平面31上不同的設置高度。該些晶片311A與311B之間係可利用一晶片貼附層314黏接。
再請參閱第7圖，該虛置覆晶320之該些柱狀凸塊322、323係具有複數個第一端部322A、323A，該些第一端部322A、323A係以複數個銲料324接合至該些晶片311A、311B之該些電極313。該些柱狀凸塊322、323係可包含複數個導體柱，該些柱狀凸塊322、323之整列間高度間隔差(即該些柱狀凸塊323較長於該些柱狀凸塊322之高度)係可約為該些晶片311A、311B之晶片貼附單位厚度。在本實施例中，該晶片貼附單位厚度係為該晶片311A之厚度與該晶片貼附層314之厚度兩者總和。較佳地，該虛置覆晶320係可更包含複數個間隔維持凸塊325，其係利用銲料326接合至該載板30。
請參閱第7圖，該封膠體330係密封該晶片堆疊體310與該些柱狀凸塊322、323，該封膠體330係具有一被降低表面331，以使該虛置覆晶320之主體321被移除並且殘留之該些柱狀凸塊322、323係具有複數個第二端部322B、323B，其係顯露於 該被降低表面331，藉以構成雙向覆晶接合的封裝型態。
如第8A與8B圖所示，本發明所提供之虛置覆晶320係適用於一多晶片堆疊封裝構造300中，該虛置覆晶320係包含一主體321以及複數個突出於該主體321之柱狀凸塊322、323，該主體321係選自於虛晶片與金屬片之其中之一，該些柱狀凸塊322、323之整列間高度間隔差係匹配於一個晶片貼附單位厚度。
以上所揭露的僅為本發明較佳實施例而已，當然不能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
100‧‧‧薄型扇出式多晶片堆疊封裝構造
110‧‧‧晶片堆疊體
111‧‧‧晶片
112‧‧‧主動面
112A‧‧‧未堆疊覆蓋之主動面
113‧‧‧電極
114‧‧‧晶片貼附層
120A‧‧‧接合面
122~129‧‧‧第一柱狀凸塊
130‧‧‧封膠體
131‧‧‧平坦面
140‧‧‧重配置線路結構
141‧‧‧扇出線路
142‧‧‧第一保護層
143‧‧‧第二保護層
150‧‧‧犧牲間隔件
151‧‧‧研磨面
160‧‧‧外接端子
170‧‧‧銲料

Claims (21)

  1. 一種薄型扇出式多晶片堆疊封裝構造，包含：一晶片堆疊體，主要係由複數個晶片堆疊所組成，每一晶片係具有一主動面以及複數個位於該主動面之電極，該些電極係不被該些晶片堆疊覆蓋，其中一主動面係亦不被該些晶片堆疊覆蓋；一第一虛置覆晶之複數個第一柱狀凸塊，係至少接合至上述未堆疊覆蓋之主動面之該些電極；一封膠體，係密封該晶片堆疊體與該些第一柱狀凸塊，該封膠體係具有一平坦面，該平坦面係鄰近於上述未堆疊覆蓋之主動面，以使該第一虛置覆晶之主體被移除並且殘留之該些第一柱狀凸塊係具有複數個接合面，其係共平面顯露於該平坦面；以及一重配置線路結構，係形成於該平坦面上，該重配置線路結構係包含複數個扇出線路，該些扇出線路係連接至該些第一柱狀凸塊之該些接合面。
  2. 如申請專利範圍第1項所述之薄型扇出式多晶片堆疊封裝構造，其中該重配置線路結構係更包含一第一保護層與一第二保護層，其中該第一保護層係覆蓋於該平坦面，該些扇出線路係形成於該第一保護層與該第二保護層之間。
  3. 如申請專利範圍第2項所述之薄型扇出式多晶片堆疊封裝構造，另包含複數個外接端子，其係接合於該重配置線路結構 上，以電性連接該些扇出線路。
  4. 如申請專利範圍第1項所述之薄型扇出式多晶片堆疊封裝構造，其中該些晶片係為階梯式錯位堆疊，以不遮蓋該些電極，該些電極係包含複數個銲墊。
  5. 如申請專利範圍第2項所述之薄型扇出式多晶片堆疊封裝構造，另包含一犧牲間隔件，係介設於該平坦面與上述未堆疊覆蓋之主動面之間。
  6. 如申請專利範圍第5項所述之薄型扇出式多晶片堆疊封裝構造，其中該犧牲間隔件係為一板材，其係選自於虛晶片與金屬片之其中之一，並且該犧牲間隔件係具有一共平面於該平坦面之研磨面，該第一保護層係更覆蓋於該研磨面。
  7. 如申請專利範圍第1項所述之薄型扇出式多晶片堆疊封裝構造，其中該些第一柱狀凸塊係包含複數個導體柱，該些第一柱狀凸塊之整列間高度間隔差係約為該些晶片之晶片貼附單位厚度。
  8. 如申請專利範圍第1至7項任一項所述之薄型扇出式多晶片堆疊封裝構造，另包含至少一第二虛置覆晶，係設有複數個第二柱狀凸塊，係接合至其餘晶片之該些電極，而該第二虛置覆晶係具有複數個橫向貼附於其主體之導通路徑，以電性連接該些第二柱狀凸塊，並且該封膠體係更密封該第二虛置覆晶與該些第二柱狀凸塊。
  9. 一種薄型扇出式多晶片堆疊封裝構造之製造方法，包含： 提供一晶片堆疊體於一暫時載板上，該晶片堆疊體主要係由複數個晶片堆疊所組成，每一晶片係具有一主動面以及複數個位於該主動面之電極，該些電極係不被該些晶片堆疊覆蓋，其中一主動面係亦不被該些晶片堆疊覆蓋；設置一第一虛置覆晶於該晶片堆疊體上，以使第一虛置覆晶之複數個第一柱狀凸塊係至少接合至上述未堆疊覆蓋之主動面之該些電極；形成一封膠體於該暫時載板上，該封膠體係密封該晶片堆疊體與該些第一柱狀凸塊；研磨該封膠體，使得該封膠體係具有一平坦面，該平坦面係鄰近於上述未堆疊覆蓋之主動面，以使該第一虛置覆晶之主體被移除並且殘留之該些第一柱狀凸塊係具有複數個接合面，其係共平面顯露於該平坦面；形成一重配置線路結構於該平坦面上，該重配置線路結構係包含複數個扇出線路，該些扇出線路係連接至該些第一柱狀凸塊之該些接合面；以及移除該暫時載板。
  10. 如申請專利範圍第9項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，其中該重配置線路結構係更包含一第一保護層與一第二保護層，其中該第一保護層係覆蓋於該平坦面，該些扇出線路係形成於該第一保護層與該第二保護層之間。
  11. 如申請專利範圍第10項所述之薄型扇出式多晶片堆疊封裝 構造之製造方法，在形成該重配置線路結構之步驟之後，另包含：接合複數個外接端子於該重配置線路結構上，以電性連接該些扇出線路。
  12. 如申請專利範圍第9項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，其中該些晶片係為階梯式錯位堆疊，以不遮蓋該些電極，該些電極係包含複數個銲墊。
  13. 如申請專利範圍第9項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，在提供該晶片堆疊體之步驟之後與形成該封膠體之前，另包含：設置一犧牲間隔件於上述未堆疊覆蓋之主動面上。
  14. 如申請專利範圍第13項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，其中該犧牲間隔件係為一板材，其係選自於虛晶片與金屬片之其中之一，並且在研磨該封膠體之步驟之後，該犧牲間隔件係具有一共平面於該平坦面之研磨面，該第一保護層係更覆蓋於該研磨面。
  15. 如申請專利範圍第9項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，其中該些第一柱狀凸塊係包含複數個導體柱，該些第一柱狀凸塊之整列間高度間隔差係匹配於該些晶片之晶片貼附單位厚度。
  16. 如申請專利範圍第9至15項任一項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，在設置該第一虛置覆晶之步驟中，另包含：設置至少一第二虛置覆晶於該晶片堆疊體上， 該第二虛置覆晶係設有複數個第二柱狀凸塊，係接合至其餘晶片之該些電極，而該第二虛置覆晶係具有複數個橫向貼附於其主體之導通路徑，以電性連接該些第二柱狀凸塊，並且在形成該封膠體之步驟之後，該封膠體係更密封該第二虛置覆晶與該些第二柱狀凸塊。
  17. 一種多晶片堆疊封裝構造，包含：一晶片堆疊體，主要係由複數個晶片堆疊所組成並位於一載體平面上，每一晶片係具有一主動面以及複數個位於該主動面之電極，該些電極係不被該些晶片堆疊覆蓋，該些電極係依據所屬晶片之不同而具有在該載體平面上不同的設置高度；一虛置覆晶之複數個柱狀凸塊，該些柱狀凸塊係具有複數個第一端部，該些第一端部係以複數個銲料接合至該些晶片之該些電極；以及一封膠體，係密封該晶片堆疊體與該些柱狀凸塊，該封膠體係具有一被降低表面，以使該虛置覆晶之主體被移除並且殘留之該些柱狀凸塊係具有複數個第二端部，其係顯露於該被降低表面，藉以構成雙向覆晶接合的封裝型態。
  18. 如申請專利範圍第17項所述之多晶片堆疊封裝構造，其中該些柱狀凸塊係包含複數個導體柱，該些柱狀凸塊之整列間高度間隔差係約為該些晶片之晶片貼附單位厚度。
  19. 如申請專利範圍第17或18項所述之多晶片堆疊封裝構造， 另包含該虛置覆晶之複數個間隔維持凸塊，該些間隔維持凸塊係較長於該些柱狀凸塊且貫穿該封膠體。
  20. 一種虛置覆晶，適用於一多晶片堆疊封裝構造中，該虛置覆晶係包含一主體以及複數個突出於該主體之柱狀凸塊，該主體係選自於虛晶片與金屬片之其中之一，該些柱狀凸塊之整列間高度間隔差係匹配於一個晶片貼附單位厚度。
  21. 如申請專利範圍第20項所述之虛置覆晶，另包含複數個橫向貼附於該主體之導通路徑，以電性連接該些柱狀凸塊。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763550B (zh) * 2020-12-21 2022-05-01 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI797669B (zh) * 2021-02-25 2023-04-01 日商鎧俠股份有限公司 半導體裝置以及半導體裝置的製造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10090232B1 (en) 2017-11-13 2018-10-02 Macronix International Co., Ltd. Bumpless fan-out chip stacking structure and method for fabricating the same
WO2019132933A1 (en) * 2017-12-28 2019-07-04 Intel Corporation Multi-die, vertical-wire package-in-package apparatus, and methods of making same
US10923462B2 (en) 2018-05-01 2021-02-16 Western Digital Technologies, Inc. Bifurcated memory die module semiconductor device
US10522489B1 (en) 2018-06-28 2019-12-31 Western Digital Technologies, Inc. Manufacturing process for separating logic and memory array
US11075147B2 (en) 2019-07-08 2021-07-27 Texas Instruments Incorporated Stacked die semiconductor package
US11024604B2 (en) * 2019-08-10 2021-06-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11569203B2 (en) * 2020-02-04 2023-01-31 Micron Technology, Inc. Multi-height interconnect structures and associated systems and methods
JP2022002249A (ja) * 2020-06-19 2022-01-06 キオクシア株式会社 半導体装置およびその製造方法
US11450645B2 (en) * 2020-11-24 2022-09-20 Micron Technology, Inc. Semiconductor assemblies with hybrid fanouts and associated methods and systems
CN112992696A (zh) * 2021-05-06 2021-06-18 通富微电子股份有限公司 堆叠芯片的封装方法和封装结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US7592691B2 (en) * 2006-09-01 2009-09-22 Micron Technology, Inc. High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies
US8178978B2 (en) * 2008-03-12 2012-05-15 Vertical Circuits, Inc. Support mounted electrically interconnected die assembly
US8049339B2 (en) * 2008-11-24 2011-11-01 Powertech Technology Inc. Semiconductor package having isolated inner lead
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
KR20120035297A (ko) * 2010-10-05 2012-04-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9941207B2 (en) * 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763550B (zh) * 2020-12-21 2022-05-01 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI797669B (zh) * 2021-02-25 2023-04-01 日商鎧俠股份有限公司 半導體裝置以及半導體裝置的製造方法
US11854925B2 (en) 2021-02-25 2023-12-26 Kioxia Corporation Semiconductor device and method of manufacturing semiconductor device

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