TW201622017A - 微電子組件中使用下塡帶之技術及具耦接至貫穿基體通孔之空腔的微電子組件 - Google Patents

微電子組件中使用下塡帶之技術及具耦接至貫穿基體通孔之空腔的微電子組件 Download PDF

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Publication number
TW201622017A
TW201622017A TW104130617A TW104130617A TW201622017A TW 201622017 A TW201622017 A TW 201622017A TW 104130617 A TW104130617 A TW 104130617A TW 104130617 A TW104130617 A TW 104130617A TW 201622017 A TW201622017 A TW 201622017A
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Taiwan
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cavity
microelectronic
component
contact pad
substrate
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TW104130617A
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English (en)
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艾里克Ｓ 土佐
瑞吉許 卡特卡
亮 王
西普里恩Ｅ 尤左
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英凡薩斯公司
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Publication of TW201622017A publication Critical patent/TW201622017A/zh

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Abstract

一微電子組件具有容置於一空腔中並被下填帶覆蓋之一接觸墊。該空腔具有在該下填帶下方之一空隙。另一微電子組件之一凸出之接觸墊刺破該下填帶來該進入該空腔並結合於凹設的該接觸墊。該空隙有助於穿破該下填帶，因此減少殘留在該二接觸墊間的下填帶的量並改善接觸阻抗。本案亦提供了具有帶一空腔之一基體且具有延伸入該空腔內之一貫穿基體通孔的一微電子組件。本案亦提供了其他特徵。

Description

微電子組件中使用下填帶之技術及具耦接至貫穿基體通孔之空腔的 微電子組件
本發明係有關於微電子元件，特別是有關於組裝微電子元件。
微電子組件具有極小之電路，該等電路具有太小而無法藉人工用手操控之特性。此種組件的一些例子有半導體積體電路(圖1中之積體電路(IC)110)、互連基體(如120)、及其組合(圖1之組件122為組件110及120之組合)。基體120在不同的IC 110之間及/或在IC及其他微電子組件及其他電路之間提供相互連接。互連基體的例子有印刷電路板(PCB)及中介層；中介層是一種中介的互連基體，中介層的頂端及底端均附接有其他微電子組件。在圖1的例子中，兩個IC 110的接觸墊110C是附接於基體120的接觸墊120C。基體120具有將該等接觸墊120C以想要的樣式互連的互連線150。該等接觸墊110C與接觸墊120C的附接方式顯示於140；這些附接方式可以是焊接、黏合的或熱壓的附接(在熱壓的附接方式中，接觸墊是以不需要焊料、 黏合劑或任何其他結合劑的方式附接)。接觸墊110C也可以分開的線路來連接至120C，但分開的線路會非所欲地增加組裝的大小及連接的長度。較短的長度有利於減少功率的消耗及寄生電容及電感，以及增加操作速度。
每個IC 110及基體120可包括每平方英寸或每平方公分有上百或上千個接觸墊110C及120C之密集地封裝的電路。因此，該接觸墊及該連接部140必須要細小。然而，細小的連接部會容易因熱脹冷縮造成的壓力而破裂。為了加強連接部140，周圍空間填滿了下填膠(underfill,UF)130。下填膠130是一種將組件110膠合至組件120而因此能釋放連接部140上部分壓力的黏合劑。
在較古老但今日仍在使用的技術中，該下填膠130是在IC 110附接至基體120後再被引入；該下填膠是以液體形式被引入該IC周邊，並藉毛細力被拉引至IC的底面。然後該下填膠被固化為固體狀態。只能希望該下填膠不具空隙。然而，該毛細程序及後續的固化會花費許多時間，這會需要嚴格地要求該下填膠材料及該程序的條件，特別是若該IC 110是大型的。無空隙之毛細下填程序會是所需的程序。
另一選項是預施用下填膠，也就是在將IC 110附接至基體120之前施用下填膠。圖2A顯示液態(雖為黏滯但仍能流動)下填膠130預施用於IC 110或基體120上，並於IC被放置於該基體上時被擠壓的情況。在該下填程序前，接觸墊120C已與焊料140相”碰撞”。圖2B顯示該IC的接觸 墊110C及120C藉焊接140相接合。在這個階段，該(熔融)焊料回流來將該接觸墊110C結合至該接觸墊120C，且下填膠130被固化。
此程序需要嚴格的下填膠沈積控制：若該下填膠層太厚，那麼空隙(氣泡)就可能形成於該下填膠中。並且，非所欲地，任何過量的預施用之下填膠會從IC底下流出並可能影響鄰接的電路。
另一種類型的預施用之下填膠是非導電薄膜(non-conductive film,NCF)，以液體形式被施用至IC 110(如於圖3A中)或基體120，並於組件110、120彼此附接之前被部分固化。或者，NCF能以乾的(固體)形式被施用，例如藉熱滾筒施用；熱會使得NCF於施用期間輕微的流動並覆蓋IC 110而不產生空隙。
在圖3B的例子中，具有NCF 130之IC 110被附接至基體120。此一程序是在高溫及足夠壓力(以力F繪示)下進行來軟化NCF 130，藉此該接觸墊110C及120C會穿刺該NCF並結合在一起(例如藉由熱壓或藉焊料，未圖示；該焊料可在其被NCF覆蓋前形成於接觸墊110C上)。
此程序中的一個主要挑戰是提供低接觸阻抗，也就是使接觸墊110C及120C之接合處350有低電阻。由於NCF是介電質，而接合區域350很小，即使微量的NCF殘餘在區域350中皆可大幅降低電導性。若該IC具有上百或上千的接觸墊110C，即使單一個不良連接(介於一單一對接觸墊110C及120C)就可能使該組裝變得不能運作。因 此，所提出者是如何安排NFC使得該接觸墊110C在該IC 130附接至基體120(如於圖3C中)前能被曝露。見美國核准前專利早期公開號2011/0237028(Hamazaki等人，2011年9月29日)，及美國專利號6,916,684(Stepniak等人，2005年7月12日)。
本節總結了此發明的一些特點。其他特點會在後續部分中被描述。此發明是由附加的請求項所定義，其以參照的方式併入本節。
本發明的一些實施例不需要如圖3C中之接觸墊一般曝露出來。然而，NCF及接觸墊是被設計為在組件與組件間之附接時有較可靠的NCF穿刺。更特別的是，在一些實施例中，其中一接觸墊凸出，而其他接觸墊則容置於一空腔中而呈凹陷。舉例而言，於圖4A中，接觸墊110C凸出，而接觸墊120C是容置於基體120中的一空腔410中而呈凹陷(圖式不必然按比例，誇大的部分係用以闡明相關技術特徵)。更進一步，NCF 130是一乾帶或一乾層及液體層的組合，使得該NCF不必填滿該空腔410即可覆蓋該空腔410。該空腔具有在NCF帶底下的一空隙410V。當該IC 110被放置在組件120(圖4B)上，該NCF被凸出的接觸墊110C(由於有施力F)推進該空隙410V。結果，該NCF延伸出來，在該接觸墊110C底下變得較薄。該NCF在抵達該接觸墊120C之前可能會破裂或至少部分被該接觸墊110C穿刺。即使NCF在此階段尚未破裂，較薄的NCF使得兩接觸 墊較易穿刺該NCF並可靠地結合在一起(圖4C)。
既然該NCF穿刺因該空隙而更可靠，可以降低該力F以減少損壞組件110及120的風險。更進一步，可以較不精確地設置該力F，也就可容許其在一較大的範圍中變化，卻仍能提供可靠的接觸墊結合。
在其他實施例中，該NCF帶是於該組件附接前預製樣式的(例如藉雷射、沖壓、光蝕刻或其他技術)。
在一些實施例中，在該接觸墊結合後，在結合溫度或更低溫時施用真空或壓力(力F)會使得該NCF層的一部位填充該空腔410並提供如圖4C中的一平坦的表面。
在接觸墊110C附接至120C之前，該空腔可以部分被焊料或黏合劑填充，留下介於該焊料或黏合劑與該NCF之間的空隙410V。該空隙容許該焊料或黏合劑在附接期間膨脹，以及也提供了該軟化的NCF膨脹及在附接期間於升高的溫度下流入該空腔的空間。因此，該空腔容許對許多參數寬鬆的控制，像是該接觸墊及該空腔的尺寸；NCF厚度；製造及後續操作期間的溫度；及包括該NCF及該焊料或黏合劑之多種材料的組成。
本發明的許多層面相關於凸出至空腔內之貫穿基體通孔(TSV)；舉例而言，該呈凹陷之接觸墊120C可由凸出至該空腔內的一TSV來提供。該空腔可被部分地填充焊料或黏合劑。
本發明不以上述特徵或優點為限，僅以附加之請求項來界定。
110、110.1、110.2、110.3、110.4‧‧‧積體電路(IC)/組件
110C、110C.1、110C.2、110C.3、120C、120C.1、120C.2、120C.3、920C‧‧‧接觸墊
120‧‧‧基體/互連基體/組件
122‧‧‧組件
130、130A、130B‧‧‧下填膠/非導電薄膜(NCF)(帶)
140‧‧‧連接部/焊料/焊接
150‧‧‧互連線/電路
350‧‧‧接合處/接合區域
410、410.1、410.2‧‧‧空腔
410V、410V.1、410V.2‧‧‧空隙
610‧‧‧焊料/黏合劑
710、810‧‧‧洞
720‧‧‧印模
804‧‧‧真空台
820‧‧‧真空幫浦
910‧‧‧基體
914‧‧‧(盲)洞
920‧‧‧導體/通孔
1104、1110、1120‧‧‧介電質/介電層
1150‧‧‧電路層
1210、1218‧‧‧遮罩
1214‧‧‧種子(層)
F‧‧‧力
圖1、2A、2B、3A、3B、3C是根據先前技術之微電子組件在不同製造階段的垂直截面圖；圖4A、4B、4C、5、6A、6B、7A是根據本發明的一些實施例之微電子組件在不同製造階段的垂直截面圖；圖7B是根據本發明的一些實施例之一微電子組件的俯視圖；及圖8、9A、9B、10A、10B、11、12A、12B、12C、12D、13A、13B、13C、13D、13E、13F、14A、14B、15、16是根據本發明的一些實施例之微電子組件在不同製造階段的垂直截面圖。
本節中描述的實施例是說明而非限制本發明。本發明是由附加的請求項所定義。
以下所述之組件110、120及其他微電子組件可為任何微電子組件，除非文字特別指明，不必然為一IC或一互連基體。舉例而言，組件110及120其一或兩者均可為多IC之一組裝及/或互連基體。該詞彙「IC」及「基體」是用以說明而非限制該發明。
如圖4A中所示，接觸墊110C可被連接至組件110中的電路150。電路150可包括導線(可能包括用來提供位在該組件頂端之一接觸墊(未示出)之延伸貫穿組件110之通孔)、電晶體、電阻、電容、電感、及/或其他電路組 件。相似地，接觸墊120C可被連接至組件120中如此的電路(未示出)。電路150在後續之一些或全部圖式中被省略。
該詞彙「頂」及「底」是為了易於描述；該等組件及其他元件在製造或後續操作期間可被上下翻轉或是轉至任何角度。
更進一步，接觸墊110C、120C之任一者可為凸出，而另一接觸墊則呈凹陷。
適合的NCF帶材包括聚合物帶，包括介電有機聚合物，有可能具填料。一個例子是具有矽填料之半固化(B-階段)環氧樹脂。適合的材料描述於前述美國核准前專利早期公開號2011/0237028(Hamazaki等人，2011年9月29日)，及美國專利號6,916,684(Stepniak等人，2005年7月12日)。
更進一步，該NCF帶可為一多層結構，具有以上述材料製成之一或多層，並可能具額外的固體或非固體層。
該接觸墊材料可如同先前技術。該接觸墊可包括焊料或導體或異向性黏合劑之外層，或者其可以不需焊料或黏合劑的方式結合在一起，例如以熱壓之方式。所提到之該焊料或黏合劑，有時候如在以下討論中被描述為分離的多個層，但有時候被指為該接觸墊的一部分。
焊料或黏合劑可在組件至組件之附接前被預先沈積在接觸墊110C上。或者，或是除此之外，該焊料或黏合劑可在NFC 130施用於組件120上之前或是在NCF施用後 (舉例來說，若是該NCF帶是在組件附接前預製樣式者)預先沈積在接觸墊120C上。
在一些實施例中，圖4C之操作(組件110及120之接合)由低溫開始，此時該NCF帶130較容易破裂(該NCF破壞強度較低)。當該接觸墊110C深入該空腔410內部時，溫度增加；在此時該NCF帶可能已經破裂而該兩接觸墊已在定位或幾乎在定位，在該位置其可結合在一起(藉熱壓、焊接(未圖示)、導電或異向性黏合劑(未圖示)，或一些其他手段)。舉例而言，當該接觸墊110C是深入該空腔，該二接觸墊可碰觸或幾乎碰觸彼此，或者其可碰觸或幾乎碰觸結合劑如焊料或黏合劑。在此階段增加溫度可能軟化該NCF(視該NCF的材料而定)並因此有益於自該接觸墊間移除任何殘餘的NCF。增加的溫度也可能是結合該接觸墊之所需。
此外，增加的溫度可能導致至少部分NCF流動並填滿空腔410；在一些實施例中可能會冀望填滿該空腔以消除可能會留在該空腔內部並腐蝕該等接觸墊的空氣或其他氣體。然而，有可能冀望不要完全填滿該空腔，以便在將該等接觸墊110C附接至120C或於其他高溫操作時所進行的焊料回流期間，焊料或其他材料有熱膨脹的空間。
如圖5中所示，在一些實施例中，該凸出的接觸墊110C即便在該NCF帶接觸該呈凹陷的接觸墊120C時仍未穿破該NCF帶。或者，該NCF帶可能會不完全破裂，有一些NCF殘留物留在接觸墊之間。當NCF被壓在該呈凹陷的 接觸墊120C時，需要類似於圖3B地進行額外的NCF殘留物清除工作。然而，由於有空腔410V，該NCF帶被拉伸以及變得細薄而因此較容易穿破；因此NCF殘留物清除工作會更完全。
如圖6A中所示，在施用NCF帶130前可將焊料或黏合劑610沈積至該空腔410內。焊料或黏合劑610可以將該空腔填充至高於該接觸墊120C的高度，但不完全填滿該空腔，保留一空隙410V在該NCF帶下方。即便接觸墊110C未抵達該接觸墊120C，只要該接觸墊110C抵達該焊料或黏合劑610，接觸墊110C及120C之間就能達成可靠的結合(圖6B)。因此，此一架構對於接觸墊110C之尺寸、空腔410之深度、焊料或黏合劑610之用量、及附接期間所施之壓縮力F的變化具耐受性。在該等組件110、120具有多個接觸墊110C、120C(有可能上百或上千個)於同一次附接操作中結合在一起的情況下，會特別冀望此耐受性，尤其是在難以確保接觸墊及空腔尺寸的高度一致性以及每一空腔中的焊料或黏合劑用量的高度一致性的情況下。注意到以參照的方式併入本文之美國專利號7,049,170(Savastiouk等人，2006年5月23日)討論了此種耐受性的重要性。
如上所提到的，NCF帶130可以是預製樣式的；圖7A、7B顯示了洞710在該組件至組件的附接前形成於NCF 130中空腔410的位置。圖7B是一在組件120上之預製樣式之NCF的俯視圖，而7A顯示沿圖7B之一垂直面A-A之該組件120的垂直截面。該等洞710可以沖壓(例如使用鋼 或聚合物(如PDMS)做成的印模720)、或以雷射、或光刻、或以其他方式做成。一些光刻的實施例使用感光NCF 130，或具一頂感光層之多層NCF。感光下填材料的例子有某些類型的有機聚合物如可自杜邦、富士軟片及其他製造商取得之聚醯亞胺及苯環丁烯(benzocyclobutene,BCB)為底的聚合物。或者，可以在NCF 130頂端使用分離的光阻層，並可於NCF製成樣式後且該組件至組件之附接前移除。
該等洞710在橫向尺度上(在俯視圖中)可以小於該空腔410或接觸墊120C或110C。在組件附接期間，凸出的接觸墊110C擴大了該等洞，有利於可靠的接觸結合。因此，在結合期間該NCF帶的拉伸量可以較小。因此，該空腔深度可以被減低(該空腔深度、或相當於空隙410V的深度，界定了該NCF帶的最大應變)。較淺的空腔可以較快的且更可靠地被形成。並且，能容許接觸墊110C具較短的凸出量，因而可在機械上更強，使得可靠度及製造產率被改善。
此外，能減少該壓縮力F，且對於該力F的變化、該空腔深度、及可能有其他參數(如NCF組成)有更多的耐受性。
NCF帶130可於其施用至組件120之前預製樣式。在圖8，NCF帶130被放置於具有配合該等空腔410位置之洞810的真空台804。真空幫浦820在洞810下產生真空。NCF帶在每個洞810處被穿破，來形成對應的洞710。 該NCF可藉著真空力及/或印模(諸如圖7A中顯示之720)而被穿破。如果想要，NCF帶130可包括在底部的一襯墊，以容許該NCF帶在該預製樣式程序後能容易地由該真空台分離。如圖7A，該被製出樣式的NCF帶接著被放置於組件120上。
還可使用其他方法來在施用該NCF至組件120前將NCF 130預製樣式。舉例來說，該NCF可藉雷射或光刻來預製樣式。
上述技術相容於晶圓級下填技術(wafer level underfill,WUF或WLUF)。更特別的是，在已知方法中，多IC或堆疊IC被加工於單一晶圓或一疊晶圓，然後該一或該疊晶圓被切塊以分離該IC或IC堆疊。在已知WUF方法中，NCF被施用於一晶圓頂部並與該晶圓一起被切塊；切塊形成個別的IC，每個IC頂部已經有NCF。見美國核准前專利早期公開號2009/0108472(Feger等人，2009年4月30日)及「Underfilling in the era of high density/3D interconnect：a closer look」，I Micronews，2012年1月3日，兩者均以參照方式併入本文。
根據本發明的一些實施例，在WUF方法中NCF帶130被施用於一晶圓上(若是一疊晶圓，則在最頂端的晶圓上)，而NCF帶130與該一或該疊晶圓一起被切塊；切塊形成個別的組件120，每個組件頂部已經有NCF帶。NCF可在施用至該一或該疊晶圓之前或之後預製樣式(如圖7A或8中)，可在切塊之前或之後。
圖9A及9B描繪了相同組件可以有凸出的、呈凹陷的、及其他類型的接觸墊。圖9A描繪了組件110及120附接在一起之前的情況；圖9B描繪了該等組件附接後的情況。組件110具有一凸出的接觸墊110C.1、在空腔410.2中的一呈凹陷的接觸墊110C.2、及另一接觸墊110C.3。組件120具有各別配合之接觸墊120C.1(容置於空腔410.1而呈凹陷)、120C.2(凸出)、及120C.3。NCF帶130A已被施用至組件110來覆蓋該空腔410.2，留下一空隙410V.2於該空腔中。NCF 130A未覆蓋接觸墊110C.1及110C.3。組件120具有NCF帶130B，覆蓋該空腔410.1，留下一空隙410V.1於該空腔中。NCF 130B未覆蓋接觸墊120C.2及120C.3。在組件附接期間(圖9B)，接觸墊110C.1穿刺NCF帶130B，且接觸墊120C.2穿刺NCF帶130A，來結合至該對應接觸墊120C.1及110C.2。在其他實施例中接觸墊110C.3及/或120C.3在附接前可被個別的下填帶130A或130B覆蓋，並可如先前技術中藉置換該下填料來接合在一起。上述特徵的其他組合也是有可能的。
凸出及凹陷接觸墊可藉許多技術形成，包括先前技術中的技術。舉例而言，欲形成一凸出的接觸墊，可先形成一任一幾何形狀的接觸墊，然後用一凸出的焊料塊或銅柱或某種其他類型的凸出導體來增大該接觸墊。在一些實施例中，凸出的接觸墊形成了銅柱(例如藉使用適合的遮罩電鍍一銅層)；或形成了結合至組件的線路。示例的凸出之線路為BVA線路，其被描述於以參照方式併入本 文之出自美國加州聖荷西市Invensas Corporation之InvensasTM High Performance BVA PoP package for Mobile Systems，2013年5月；亦見以參照方式併入本文之美國專利號8,618,659，Sato等人，2013年12月31日公告；以及以參照方式併入本文之美國核准前專利早期公開號2014/0036454，Caskey等人，2014年2月6日。另一種可能的技術是，在形成一接觸墊之前，在該接觸墊的位置形成一凸出的介電塊(例如一聚合塊，未圖示)，然後形成一導線疊加在該塊上如此使得該接觸墊蓋過該塊；該導線由該接觸墊延伸出來以將該接觸墊連接至其他電路如圖4A中的150；見美國專利號6,322,903，Siniaguine等人，公告日2001年11月27日，並以參照方式併入本文。或者，該塊可具有做成於其中之一洞來延伸至電路150，而該接觸墊可填充該洞並在該洞中連接至電路150。這些只是無窮盡的例子中的其中一些。
凸出的接觸墊也可使用相關於貫穿基體通孔(through-substrate vias,TSV)之技術來形成；見前述之美國專利號7,049,170。在一示例之實施例中，一基體910(圖10a)被加工以包括填入導體920之盲洞914。洞914被稱之為「盲」是因為它們沒有穿過基體910。導電之通孔920可被連接至形成於該基體中或其上的其他電路(未圖示，諸如圖4A中之150)。該基體可為矽、玻璃、或其他材料。然後該基體從底部被薄化(圖10B)，可能是藉由覆面蝕刻(blanket etch)完成。通孔920變成外露而凸出於底面，形成 如920C所示之該凸出之接觸墊。如想要，可於底部形成其他的電路。
凸出之接觸墊可具有尖端以利穿破NCF 130。舉例來說，圓錐形或錐狀的形體可被提供，如於圖11中之接觸墊110C。這樣的形體可藉適合的光刻來形成，例如藉圖形反轉光阻或其他技術；例如見美國核准前專利早期公開號2013/0270699(Kuo等人，2013年10月17日)，其以參照方式併入本文)。在TSV的變化中，這樣的形體可藉洞914的合適造型來形成。
呈凹陷的接觸墊也可藉已知的技術來形成，例如，形成任一幾何形狀的接觸墊，然後形成在該接觸墊上的一介電層(可能是具遍佈該組件之平坦頂面的一介電質)，並利用光刻對該介電層製作樣式來形成曝露該接觸墊之一空腔410。在一些實施例中(例如4B中的接觸墊120C)，該呈凹陷的接觸墊凸出該空腔底部。該凸出的構造可藉上述技術形成；舉例來說，該呈凹陷的接觸墊可先形成為一凸出的接觸墊；然後可沈積一介電層來覆蓋該凸出之接觸墊；然後在該介電質內蝕刻一空腔來曝露該接觸墊的頂面及側壁；現在該接觸墊即容置於該空腔內而呈凹陷，但自該空腔底部凸出。
呈凹陷的接觸墊也可藉TSV技術做成。舉例而言(圖12A)，「盲」的通孔920可以如圖10A中的方式形成；簡化起見只顯示一通孔，但可同時或依序形成任何數量的通孔。在此例中，該等洞914的內壁形成一層1104並將該 基體910與通孔920分開；層1104被標示介電質(例如用來將該等通孔920與該基體及/或彼此間電性絕緣)；或者，或是除此之外，層1104在導體920被電鍍的情況下可作為一屏蔽層、或種子層，及/且可用於其他目的。層1104在一些實施例中被省略。
然後，基體910可在不顯露該「盲」的通孔920的情況下隨意地藉覆面蝕刻從底部進行薄化。然後，(見圖12B)該基體之底面的遮罩蝕刻產生了圍繞通孔920底端之空腔410。介電質1120(圖12C)被沈積於該結構的底面以於隨後的步驟保護該基體910以及使其電性絕緣。一開始，介電層1104、1120是於底部覆蓋該通孔920，但其已被以光刻製作樣式來曝露該通孔920於底部，如圖12C所示。其他層1150(圖12D)，整體顯示為一電路層，可被形成於底部上以將導體920連接至合適的電路以及形成其他電路。在圖12D中，該層1150覆蓋該底部上之該通孔920但在該通孔920下方具有一露出之導電面並作為該呈凹陷之接觸墊920C。或者，或是除此之外，在空腔410中的層1150的一些其他部分及/或通孔920可作為一呈凹陷之接觸墊。
然後NCF(未圖示)可被施用至該底面並以上述任一種技術加工。
一呈凹陷的接觸墊也可被形成於通孔920的頂部。一示例之流程顯示於圖13A-13E。空腔410(圖13A)以一遮罩蝕刻處理蝕刻於基體910頂部。(「頂」及「底」等 詞是為了易於描述；該基體或其他元件在製造或後續操作期間可被上下翻轉或是轉至任何角度。)然後一遮罩1210(圖13B)被形成來界定該洞914，該等洞被蝕刻於空腔底部。該等洞如所示是「盲」(未貫通)的，或者可以穿過基體120。遮罩1210被移除，而基體910的頂面被介電質1110(圖13C)及種子層1214覆蓋，還可能有一屏蔽層(未圖示)在種子層下方。這些層依所欲被製出樣式；這些層覆蓋洞914的表面。一遮罩1218(圖13D)被形成來覆蓋該結構，但曝露出該洞914。導體920，例如銅，被電鍍於該等洞914內壁或填入其中。
該遮罩1218被移除(圖13E)。該介電質1110及種子1214的曝露部位可被移除或依所欲製作樣式。在顯示的實施例中，種子1214被移除但該介電質1110被留在原位；介電質1110可覆蓋空腔410的表面。該呈凹陷的接觸墊即由導體920的頂面提供。或者(圖3F)，一電路層1150可被形成於頂端來將導體920連接至其他元件及如圖12D中來提供其他電路元件；在此情況下，該呈凹陷的接觸墊可由該電路層疊加在該導電體920上的部位提供。後續處理可如上述。舉例而言，NCF帶可被形成於頂端。如想要，基體120可於底部被薄化來轉化導體920為一TSV並於底部提供一呈凹陷或凸出之接觸墊。舉例而言，一凸出的接觸墊可以如圖10B中的覆面蝕刻來提供。所產生之結構顯示於圖14A；介電質1110於通孔920底部藉覆面或遮罩蝕刻被移除。如想要，一電路層1150(圖14B)可被形成於底部來將 該TSV 920連接至其他電路元件及如於圖12D中來提供其他電路元件；在此情況下，該凸出的接觸墊可由該電路層疊加於該TSV 920上的部位提供。
在圖13F之結構之底部上的一呈凹陷的接觸墊可由圖12B-12D的流程提供；所產生的結構顯示於圖15。
如圖16中所描繪，上述該TSV技術可被用來減少包括一堆疊晶粒(諸如晶粒110.1至110.4)之一微電子組件的高度；該堆疊中間的每一晶粒110均有連接至上方晶粒之TSV 920及下方晶粒的另一TSV 920的一TSV 920。該堆疊之TSV 920形成一垂直的可被每一晶粒之電路連接的線路。此種堆疊的範例有混合記憶體立方(hybrid memory cubes)(見美國核准前專利早期公開號2012/0276733，Saeki等人，2012年11月1日，以參照方式併入本文)；路由電路(routing circuits)(美國核准前專利早期公開號2014/0111269，Huang等人，2014年4月24日，以參照方式併入本文)；及可能的其他類型。圖16顯示四個晶粒110.1至110.4，其中晶粒110.4尚未附接至該堆疊的底部。只有一TSV的線路被顯示，由四個晶粒之四個TSV所組成。每一晶粒的TSV 920具有圖14之結構，也就是具有在頂端之一呈凹陷的接觸墊920C及在底端之一凸出之接觸墊920C。每一晶粒(除了110.1)的頂端接觸墊結合至該疊加其上之晶粒的底端接觸墊來形成該線路。在該堆疊中可存在任意數量的晶粒。只有一TSV線路被顯示，但可存在任意數量的TSV線路(例如可存在一TSV線路陣列)。該TSV線路 的底端接觸墊(在底端晶粒中)可被連接至一印刷電路板(PCB)或某其他基體(未圖示)。該頂端晶粒可以有或沒有在該TSV線路頂端的接觸墊。
若想要，晶粒110.4可在其由底部進行薄化前被附接至該堆疊的底部，也就是在圖13F的階段(當其通孔920仍為一「盲」的通孔時)；該晶粒可在該附接後由底部進行薄化。每一晶粒(除了頂端的晶粒)均可在附接後被薄化。見美國專利號6,322,903(Siniaguine等人，2001年11月21日)，以參照方式併入本文。
本發明不以上述實施例為限。其他實施例及變化被涵蓋在本發明的範圍之內，如附加的請求項所界定。
110‧‧‧積體電路(IC)
110C‧‧‧接觸墊
120‧‧‧基體
120C‧‧‧接觸墊
130‧‧‧非導電薄膜(NCF)帶
410‧‧‧空腔
F‧‧‧力

Claims (18)

  1. 一種製造方法，包含：獲得一第一微電子組件，其包含一或多個第一空腔，及對每一第一空腔有容置於該第一空腔中的至少一第一接觸墊，而該第一空腔包含在該第一接觸墊上方的一空隙；及將一下填帶附接至該第一微電子組件，該下填帶至少部分地覆蓋每一第一空腔的空隙。
  2. 如請求項1之方法，其中，該下填帶完全地覆蓋至少一第一空腔。
  3. 如請求項1之方法，還包含將一第二微電子組件附接至該第一微電子組件，讓該下填帶位在該第一及第二微電子組件之間，其中，該第二微電子組件包含一或多個凸出之第二接觸墊，且在附接該第二微電子組件期間，每一第二接觸墊穿過該下填帶進入一個別的第一空腔並結合於一個別的第一接觸墊。
  4. 如請求項3之方法，其中，在該附接期間，至少一第二接觸墊產生或擴大該下填帶的一洞，同時該空腔具有在該第二接觸墊及該下填帶下方的一空隙區域。
  5. 如請求項3之方法，其中，在該附接期間，至少一第二接觸墊將該下填帶推入該個別的第一空腔之空隙，並拉伸在該個別的第一空腔之空隙內的該下填帶。
  6. 如請求項3之方法，其中，各該第一及第二微電子組件 包含一基體及一或多個貫穿基體通孔(TSV)，每一貫穿基體通孔是穿過該基體的導電通孔；其中，每一凸出的第二接觸墊由在該第二微電子組件中之個別的TSV或由該第二微電子組件之疊加在該個別的TSV上之電路元件所提供；及其中，每一第一接觸墊是由在該第一微電子組件中之一個別的TSV或由該第一電子組件之疊加在該個別的TSV上之電路元件所提供。
  7. 如請求項3之方法，其中，該第二微電子組件包含位於與該一或多個凸出之第二接觸墊相對之一側的一或多個第一空腔，且對於每一第一空腔，該第二微電子組件包含容置於該第一空腔內之至少一第一接觸墊，該第一空腔包含在該第一接觸墊上方的一空隙；其中，該方法還包含：將一下填帶附接至該第二微電子組件，該下填帶至少部分覆蓋著在該第二微電子組件之每一第一空腔中的該空隙；獲得一第三微電子組件，其包含一或多個凸出的第二接觸墊；將該第三微電子組件附接至該第二微電子組件，其中，在附接該第三微電子組件期間，該第三微電子組件的每一第二接觸墊穿過該下填帶進入該第二微電子組件之一個別的第一空腔並結合於該第二微電子組件之一個別的第一接觸墊，該下填帶至少部分覆蓋該第二微 電子組件之每一第一空腔中之該空隙。
  8. 如請求項1之方法，其中，至少一第一空腔包含部分填充該第一空腔之可熔材料，該第一空腔之空隙包含位於該可熔材料正上方以及該下填帶正下方的一區域。
  9. 如請求項8之方法，其中，該可熔材料是於附接該下填帶之前設置於該第一空腔內。
  10. 一種結構，包含：一微電子組件，包含一第一表面，該第一表面具一或多個第一空腔、及對於每一第一空腔之容置於該第一空腔內之至少一第一接觸墊；及一下填帶，附接至該第一表面，該下填帶至少部分覆蓋每一第一空腔，但實體上不接觸任何第一接觸墊。
  11. 如請求項10之結構，其中，每一第一空腔具有在該下填帶下方的一空隙。
  12. 如請求項11之結構，其中，該下填帶完全地覆蓋每一第一空腔。
  13. 一種結構，其係由請求項1之方法形成者。
  14. 如請求項13之結構，還包含附接至該第一微電子組件之一第二微電子組件，讓該下填帶設置在該第一及第二微電子組件之間，其中該第二微電子組件包含一或多個凸出之第二接觸墊，每一第二接觸墊穿過該下填帶延伸入一個別的第一空腔並結合於一個別的第一接觸墊。
  15. 如請求項14之結構，其中，各該第一及第二微電子組件包含一基體及一或多個貫穿基體通孔(TSV)，每一貫穿 基體通孔是穿過該基體的導電通孔；其中，每一凸出的第二接觸墊是在該第二微電子組件中之一個別的TSV或是該第二微電子組件之疊加在該個別的TSV上之電路元件的一區域；及其中，每一第一接觸墊是在該第一微電子組件中之一個別的TSV或該第一微電子組件之疊加在該個別的TSV上之電路元件的一區域。
  16. 如請求項14之結構，其中，該第一及第二微電子組件是多個至少有三個之微電子組件M1、M2、…、Mn的一部分，其中每一者包含一基體及一或多個貫穿基體通孔(TSV)，每一貫穿基體通孔是穿過該基體的導電通孔；其中，該第一微電子組件是組件M2至Mn的其中一者，而該第二微電子組件是M1至Mn-1的其中一者；其中每一微電子組件M2至Mn包含一或多個第一空腔，及對每一第一空腔有容置於該第一空腔中的至少一第一接觸墊，該第一空腔包含在該第一接觸墊上方的一空隙；其中每一微電子組件M1至Mn-1包含一或多個凸出之第二接觸墊；其中之方法包含將每一組件Mi(i=1至n-1)附接至組件Mi+1，讓該組件Mi+1上之該下填帶處於該組件Mi及Mi+1之間，其中，在附接期間該組件Mi+1的每一第二接觸墊穿過在該組件Mi上之下填帶進入該組件Mi之一個別的第一空腔，並結合於組件Mi+1之一個別的第一 接觸墊。
  17. 一種結構，包含：一基體，包含一第一表面及一第二表面，並包含一或多個貫穿基體通孔(TSV)，每一貫穿基體通孔是穿過該基體的導電通孔；其中，該基體包含在該第一及第二表面其中至少一者中的一空腔，該空腔並耦接至延伸入該空腔的至少一TSV，該空腔被組配為局部地容納焊料以供將該TSV附接至另一微電子組件的一凸出之接觸墊。
  18. 如請求項17之結構，其中，該基體包含一半導體或玻璃材料，而該空腔延伸入該半導體或玻璃材料內。
TW104130617A 2014-09-16 2015-09-16 微電子組件中使用下塡帶之技術及具耦接至貫穿基體通孔之空腔的微電子組件 TW201622017A (zh)

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