TW201528363A - Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device - Google Patents

Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device Download PDF

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TW201528363A
TW201528363A TW103138234A TW103138234A TW201528363A TW 201528363 A TW201528363 A TW 201528363A TW 103138234 A TW103138234 A TW 103138234A TW 103138234 A TW103138234 A TW 103138234A TW 201528363 A TW201528363 A TW 201528363A
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wafer
etching
semiconductor
semiconductor substrate
region
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TW103138234A
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TWI671812B (en
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Yusaku Asano
Kazuhito Higuchi
Taizo Tomioka
Tomohiro Iguchi
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Toshiba Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Dicing (AREA)
  • Weting (AREA)

Abstract

A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.

Description

半導體晶片之製造方法、半導體晶片及半導體裝置 Semiconductor wafer manufacturing method, semiconductor wafer and semiconductor device

本申請案係以於2013年11月13日提出申請之日本專利申請案第2013-235470號為基礎並主張其優先權之權益，該申請案之全文以引用之方式併入本文中。 The present application is based on Japanese Patent Application No. 2013-235470, filed on Jan.

本發明之實施形態係關於一種半導體晶片之製造方法、半導體晶片及半導體裝置。 Embodiments of the present invention relate to a method of fabricating a semiconductor wafer, a semiconductor wafer, and a semiconductor device.

於將半導體基板單片化為晶片時，通常使用藉由旋轉之刀片機械地切斷晶圓之刀片切割。於刀片切割中，在半導體基板依序形成複數個切割溝槽，而將半導體基板單片化為晶片。因此，刀片切割存在如下問題：若縮小晶片尺寸而使切割溝槽之數量(線數)增多，則切割時間會與線數成比例地變長。 When singulating a semiconductor substrate into a wafer, blade cutting by mechanically cutting the wafer by a rotating blade is generally used. In the blade dicing, a plurality of dicing trenches are sequentially formed on the semiconductor substrate, and the semiconductor substrate is singulated into a wafer. Therefore, the blade cutting has a problem that if the number of the cutting grooves (the number of lines) is increased by reducing the size of the wafer, the cutting time becomes longer in proportion to the number of lines.

又，藉由刀片切割而獲得之晶片之角部為直角，耐衝擊性較低。而且，刀片切割因於晶片之端部產生微細之缺損(破裂)，故而藉此所獲得之晶片之抗彎強度較低。 Further, the corner portion of the wafer obtained by the blade cutting is a right angle, and the impact resistance is low. Moreover, the blade cutting causes a fine defect (fracture) due to the end portion of the wafer, and thus the obtained wafer has a low bending strength.

且說，近年來，提出有藉由化學作用於單晶基板形成高縱橫比之較深之孔的想法。 Furthermore, in recent years, there has been proposed an idea of forming a deep hole having a high aspect ratio by chemical action on a single crystal substrate.

本發明所欲解決之問題在於提供一種能以較高之生產性製造半導體晶片之方法。 The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor wafer with high productivity.

根據實施形態，半導體晶片之製造方法包括如下步驟：於半導體基板上形成分別包含保護膜之複數個蝕刻掩膜，而劃定上述半導體基板中之被上述複數個蝕刻掩膜保護之複數個第1區域、及上述半導體基板中之露出之區域即第2區域；以及藉由化學性蝕刻處理將上述第2區域各向異性地去除，而形成分別具有至少一部分位於與上述蝕刻掩膜之端面為同一面內之側壁、及到達至上述半導體基板之背面之底部的複數個溝槽，藉此，將上述半導體基板單片化為與上述複數個第1區域對應之複數個晶片本體。 According to an embodiment, a method of manufacturing a semiconductor wafer includes the steps of: forming a plurality of etching masks each including a protective film on a semiconductor substrate, and defining a plurality of first ones of the semiconductor substrates protected by the plurality of etching masks a region and a second region which is an exposed region of the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process to form at least a portion of each of the end faces of the etching mask A plurality of trenches in the in-plane and a plurality of trenches reaching the bottom of the back surface of the semiconductor substrate, thereby singulating the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions.

藉由上述構成，可提供一種能以較高之生產性製造半導體晶片之方法。 With the above configuration, a method of manufacturing a semiconductor wafer with high productivity can be provided.

10‧‧‧半導體基板 10‧‧‧Semiconductor substrate

10'‧‧‧晶片本體 10'‧‧‧ Chip Ontology

12‧‧‧元件區域 12‧‧‧Component area

14‧‧‧蝕刻掩膜 14‧‧‧ etching mask

15‧‧‧絕緣膜 15‧‧‧Insulation film

16‧‧‧保護膜 16‧‧‧Protective film

18‧‧‧露出區域 18‧‧‧ exposed area

18'‧‧‧露出區域 18'‧‧‧ exposed area

20‧‧‧切割片材 20‧‧‧Cut sheet

22‧‧‧貴金屬觸媒 22‧‧‧ precious metal catalyst

22a‧‧‧Ag粒子 22a‧‧‧Ag particles

24‧‧‧分離溝槽 24‧‧‧Separation trench

24a‧‧‧深溝槽 24a‧‧‧deep trench

26‧‧‧針狀殘留 26‧‧‧ needle residue

28‧‧‧半導體晶片 28‧‧‧Semiconductor wafer

28'‧‧‧半導體晶片 28'‧‧‧Semiconductor wafer

29‧‧‧側面 29‧‧‧ side

30‧‧‧蝕刻液 30‧‧‧etching solution

31‧‧‧側面 31‧‧‧ side

32‧‧‧蝕刻痕 32‧‧‧ etching marks

34‧‧‧接合材料 34‧‧‧Material materials

35‧‧‧基板 35‧‧‧Substrate

36‧‧‧焊料 36‧‧‧ solder

40‧‧‧半導體裝置 40‧‧‧Semiconductor device

41a‧‧‧引線框架 41a‧‧‧ lead frame

41b‧‧‧引線框架 41b‧‧‧ lead frame

43‧‧‧接合材料 43‧‧‧Material materials

45‧‧‧Al線 45‧‧‧Al line

47a‧‧‧模塑樹脂 47a‧‧‧Molding resin

47b‧‧‧模塑樹脂 47b‧‧‧ molding resin

51‧‧‧電極墊 51‧‧‧electrode pads

52‧‧‧電極保護層 52‧‧‧Electrode protective layer

54‧‧‧絕緣層 54‧‧‧Insulation

55‧‧‧配線層 55‧‧‧Wiring layer

57‧‧‧金屬觸媒膜 57‧‧‧Metal catalytic membrane

57'‧‧‧金屬觸媒膜 57'‧‧‧Metal catalytic film

58‧‧‧抗蝕圖案 58‧‧‧resist pattern

59‧‧‧半導體晶片 59‧‧‧Semiconductor wafer

70‧‧‧金屬化層 70‧‧‧metallization

72‧‧‧基板研磨裝置 72‧‧‧Substrate grinding device

A‧‧‧區域 A‧‧‧ area

B‧‧‧區域 B‧‧‧Area

C1‧‧‧角部 C1‧‧‧ corner

C2‧‧‧角部 C2‧‧‧ corner

圖1係形成有蝕刻掩膜之半導體基板之俯視圖。 1 is a plan view of a semiconductor substrate on which an etch mask is formed.

圖2係表示圖1所示之半導體基板之一部分之剖視圖。 Fig. 2 is a cross-sectional view showing a portion of the semiconductor substrate shown in Fig. 1.

圖3A係表示蝕刻掩膜之形狀之一例之平面圖。 Fig. 3A is a plan view showing an example of the shape of an etching mask.

圖3B係表示蝕刻掩膜之形狀之另一例之平面圖。 Fig. 3B is a plan view showing another example of the shape of the etching mask.

圖3C係表示蝕刻掩膜之形狀之又一例之平面圖。 Fig. 3C is a plan view showing still another example of the shape of the etching mask.

圖3D係表示蝕刻掩膜之形狀之又一例之平面圖。 Fig. 3D is a plan view showing still another example of the shape of the etching mask.

圖3E係表示蝕刻掩膜之形狀之又一例之平面圖。 Fig. 3E is a plan view showing still another example of the shape of the etching mask.

圖4係表示繼圖2之步驟之後之步驟的剖視圖。 Figure 4 is a cross-sectional view showing the steps following the steps of Figure 2.

圖5係配置有貴金屬觸媒之半導體基板之俯視圖。 Fig. 5 is a plan view of a semiconductor substrate on which a noble metal catalyst is disposed.

圖6係表示配置於露出區域之貴金屬觸媒之圖。 Fig. 6 is a view showing a noble metal catalyst disposed in an exposed region.

圖7係Ag奈米粒子觸媒之掃描式電子顯微鏡(SEM)照片。 Figure 7 is a scanning electron microscope (SEM) photograph of an Ag nanoparticle catalyst.

圖8係表示置換鍍敷之結果之SEM照片。 Fig. 8 is a SEM photograph showing the results of displacement plating.

圖9係表示繼圖4之步驟之後之步驟的剖視圖。 Figure 9 is a cross-sectional view showing the steps following the step of Figure 4.

圖10係形成有深溝槽之半導體基板之俯視圖。 Figure 10 is a plan view of a semiconductor substrate on which deep trenches are formed.

圖11係蝕刻處理後之矽基板之剖面SEM照片。 Fig. 11 is a cross-sectional SEM photograph of a ruthenium substrate after etching treatment.

圖12係表示繼圖9之步驟之後之步驟的剖視圖。 Figure 12 is a cross-sectional view showing the steps following the step of Figure 9.

圖13係產生有針狀殘留之半導體基板之俯視圖。 Fig. 13 is a plan view showing a semiconductor substrate in which needle-like residual is generated.

圖14係表示經單片化所得之半導體晶片之一例之立體圖。 Fig. 14 is a perspective view showing an example of a semiconductor wafer obtained by singulation.

圖15A係表示一實施形態之半導體晶片之製造方法之一步驟的剖視圖。 Fig. 15A is a cross-sectional view showing a step of a method of manufacturing a semiconductor wafer according to an embodiment.

圖15B係表示繼圖15A之步驟之後之步驟的剖視圖。 Figure 15B is a cross-sectional view showing the steps following the step of Figure 15A.

圖15C係表示繼圖15B之步驟之後之步驟的剖視圖。 Figure 15C is a cross-sectional view showing the steps following the step of Figure 15B.

圖15D係表示繼圖15C之步驟之後之步驟的剖視圖。 Figure 15D is a cross-sectional view showing the steps following the step of Figure 15C.

圖15E係表示繼圖15D之步驟之後之步驟的剖視圖。 Figure 15E is a cross-sectional view showing the steps following the step of Figure 15D.

圖16係表示經單片化所得之半導體晶片群之俯視圖。 Figure 16 is a plan view showing a semiconductor wafer group obtained by singulation.

圖17A係概略性地表示蝕刻痕之一例之立體圖。 Fig. 17A is a perspective view schematically showing an example of an etching mark.

圖17B係概略性地表示蝕刻痕之另一例之立體圖。 Fig. 17B is a perspective view schematically showing another example of the etching mark.

圖17C係概略性地表示蝕刻痕之又一例之立體圖。 Fig. 17C is a perspective view schematically showing still another example of the etching mark.

圖18係一實施形態之半導體裝置之剖視圖。 Figure 18 is a cross-sectional view showing a semiconductor device of an embodiment.

圖19係另一實施形態之半導體裝置之剖視圖。 Figure 19 is a cross-sectional view showing a semiconductor device of another embodiment.

圖20係又一實施形態之半導體裝置之剖視圖。 Figure 20 is a cross-sectional view showing a semiconductor device according to still another embodiment.

圖21A係表示包含電極墊之晶片本體之一例之放大剖視圖。 Fig. 21A is an enlarged cross-sectional view showing an example of a wafer body including an electrode pad.

圖21B係表示利用電極保護層被覆電極墊之晶片本體之一例之放大剖視圖。 Fig. 21B is an enlarged cross-sectional view showing an example of a wafer body in which an electrode pad is covered by an electrode protective layer.

圖22係表示晶片本體之絕緣膜等之放大剖視圖。 Fig. 22 is an enlarged cross-sectional view showing an insulating film or the like of the wafer main body.

圖23A係表示另一實施形態之半導體晶片之製造方法之步驟的剖視圖。 Fig. 23A is a cross-sectional view showing the steps of a method of manufacturing a semiconductor wafer according to another embodiment.

圖23B係表示繼圖23A之步驟之後之步驟的剖視圖。 Figure 23B is a cross-sectional view showing the steps following the step of Figure 23A.

圖23C係表示繼圖23B之步驟之後之步驟的剖視圖。 Figure 23C is a cross-sectional view showing the steps following the step of Figure 23B.

圖24A係表示另一實施形態之半導體晶片之製造方法之一步驟的剖視圖。 Fig. 24A is a cross-sectional view showing a step of a method of manufacturing a semiconductor wafer according to another embodiment.

圖24B係表示圖24A之步驟之俯視圖。 Figure 24B is a plan view showing the steps of Figure 24A.

圖25A係表示繼圖24A之步驟之後之步驟的剖視圖。 Figure 25A is a cross-sectional view showing the steps following the step of Figure 24A.

圖25B係表示圖25A之步驟之俯視圖。 Figure 25B is a plan view showing the steps of Figure 25A.

圖26A係表示繼圖25A之步驟之後之步驟的剖視圖。 Figure 26A is a cross-sectional view showing the steps following the step of Figure 25A.

圖26B係表示圖26A之步驟之俯視圖。 Figure 26B is a plan view showing the steps of Figure 26A.

圖27A係表示繼圖26A之步驟之後之步驟的剖視圖。 Figure 27A is a cross-sectional view showing the steps following the step of Figure 26A.

圖27B係表示圖27A之步驟之俯視圖。 Figure 27B is a plan view showing the steps of Figure 27A.

圖28A係表示繼圖27A之步驟之後之步驟的剖視圖。 Figure 28A is a cross-sectional view showing the steps following the step of Figure 27A.

圖28B係表示圖28A之步驟之俯視圖。 Figure 28B is a plan view showing the steps of Figure 28A.

圖29A係表示繼圖28A之步驟之後之步驟的剖視圖。 Figure 29A is a cross-sectional view showing the steps following the step of Figure 28A.

圖29B係表示圖29A之步驟之俯視圖。 Figure 29B is a plan view showing the steps of Figure 29A.

圖30係表示半導體基板之另一例之剖視圖。 Fig. 30 is a cross-sectional view showing another example of the semiconductor substrate.

圖31A係表示另一實施形態之方法之一步驟之剖視圖。 Figure 31A is a cross-sectional view showing a step of a method of another embodiment.

圖31B係表示繼圖31A之步驟之後之步驟的剖視圖。 Figure 31B is a cross-sectional view showing the steps following the step of Figure 31A.

以下，參照圖式對本發明之實施形態進行說明。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

圖1係用於一實施形態之方法之半導體基板之俯視圖。圖2表示圖1之半導體裝置之局部剖視圖。 1 is a plan view of a semiconductor substrate used in a method of one embodiment. 2 is a partial cross-sectional view of the semiconductor device of FIG. 1.

如圖示般，於半導體基板10設置有分別包含大於等於1個半導體元件之複數個元件區域12。該等元件區域12係相互隔開地排列。各元件區域12係藉由利用蝕刻掩膜14覆蓋而被保護。 As shown in the figure, a plurality of element regions 12 each including one or more semiconductor elements are provided on the semiconductor substrate 10. The element regions 12 are arranged spaced apart from one another. Each of the element regions 12 is protected by being covered with an etching mask 14.

元件區域12所包含之半導體元件例如為電晶體、二極體、發光二極體或半導體雷射。元件區域12可進而包含電容器或配線等。 The semiconductor component included in the element region 12 is, for example, a transistor, a diode, a light emitting diode or a semiconductor laser. The component region 12 may further include a capacitor or wiring or the like.

相鄰之元件區域12間之區域為半導體基板10之表面露出之露出區域18。如隨後所說明般，於該露出區域18配置貴金屬觸媒。於本實施形態中，實施使用貴金屬觸媒與蝕刻液之化學性蝕刻處理將半導體 基板10之露出區域18去除，藉此獲得經單片化所得之半導體晶片。 The area between the adjacent element regions 12 is the exposed area 18 where the surface of the semiconductor substrate 10 is exposed. A noble metal catalyst is disposed in the exposed region 18 as will be described later. In this embodiment, a semiconductor etching process using a noble metal catalyst and an etching solution is performed to carry out the semiconductor The exposed regions 18 of the substrate 10 are removed, thereby obtaining a singulated semiconductor wafer.

於圖2所示之例中，蝕刻掩膜14係由絕緣膜15與保護膜16之積層構造構成。絕緣膜雖可稱為保護膜之一種，但藉由設置絕緣膜15，可確實地保護元件區域12之電極墊(未圖示)。視情形亦可由絕緣膜及保護膜中之任一者構成蝕刻掩膜14。 In the example shown in FIG. 2, the etching mask 14 is composed of a laminated structure of the insulating film 15 and the protective film 16. Although the insulating film may be referred to as a protective film, the electrode pad (not shown) of the element region 12 can be reliably protected by providing the insulating film 15. The etching mask 14 may be formed of any one of an insulating film and a protective film as the case may be.

再者，較佳為於半導體基板10之背面預先黏貼用以保持經單片化所得之晶片之切割片材20。 Further, it is preferable that the cut sheet 20 for holding the wafer obtained by singulation is adhered to the back surface of the semiconductor substrate 10 in advance.

半導體基板10係可藉由貴金屬觸媒之效果而選擇性地進行蝕刻者，例如，可由選自Si、Ge、III-V族半導體即含有III族元素與V元素之化合物之半導體(例如GaAs、GaN等)、及SiC等之材料構成。再者，此處使用之用語「族」係短週期型週期表之「族」。 The semiconductor substrate 10 can be selectively etched by the effect of a noble metal catalyst, for example, a semiconductor (for example, GaAs, which is selected from the group consisting of Si, Ge, and III-V semiconductors, that is, a compound containing a group III element and a V element). GaN or the like, and materials such as SiC. Furthermore, the term "family" as used herein is a "family" of a short-period periodic table.

半導體基板10之厚度並無特別限定，只要根據作為目標之半導體晶片之尺寸適當決定即可。半導體基板10之厚度可設為例如50μm至500μm之範圍。雜質向半導體基板10之摻雜量亦同樣地並無特別限定，只要適當決定即可。半導體基板10之主面亦可相對於半導體之任一結晶面平行。 The thickness of the semiconductor substrate 10 is not particularly limited, and may be appropriately determined depending on the size of the target semiconductor wafer. The thickness of the semiconductor substrate 10 can be set, for example, in the range of 50 μm to 500 μm. The doping amount of the impurity to the semiconductor substrate 10 is also not particularly limited as long as it is appropriately determined. The main surface of the semiconductor substrate 10 may be parallel to any crystal plane of the semiconductor.

蝕刻掩膜14係以覆蓋元件區域12之方式選擇性地形成於半導體基板10之上表面之複數個區域。各蝕刻掩膜14之上表面形狀並不限定於矩形狀，可設為如圖3A至圖3E所示之各種形狀。 The etching mask 14 is selectively formed in a plurality of regions on the upper surface of the semiconductor substrate 10 so as to cover the element region 12. The shape of the upper surface of each etching mask 14 is not limited to a rectangular shape, and may be various shapes as shown in FIGS. 3A to 3E.

於如圖3A所示般將蝕刻掩膜14形成為具有圓形狀角部之情形時，於經單片化所得之晶片中，角部亦成為圓形狀。換言之，蝕刻掩膜14及半導體晶片之此種上表面形狀為不具有構成輪廓之直線(線段)彼此相接之部分之形狀、即構成輪廓之線段相互分離之形狀。藉由將角部設為圓形狀，可提高晶片之機械強度。 When the etching mask 14 is formed to have a rounded corner portion as shown in FIG. 3A, the corner portion also has a circular shape in the wafer obtained by singulation. In other words, the shape of the upper surface of the etching mask 14 and the semiconductor wafer is such that the shape of the portion where the straight lines (line segments) constituting the contour are in contact with each other, that is, the line segments constituting the contour are separated from each other. By setting the corners to a circular shape, the mechanical strength of the wafer can be improved.

蝕刻掩膜14之上表面亦可為具有大於等於5條邊之多邊形。例如，於圖3B所示之例中，蝕刻掩膜14分別具有六邊形之上表面，且 配置成蜂巢狀。於蝕刻掩膜具有此種上表面形狀之情形時，可獲得上表面為具有大於等於5條邊之多邊形的半導體晶片。多邊形之各內角大於90°之半導體晶片與多邊形之各內角為90°之半導體晶片相比，具有較高之機械強度。 The upper surface of the etching mask 14 may also be a polygon having five or more sides. For example, in the example shown in FIG. 3B, the etching masks 14 each have a hexagonal upper surface, and Configured in a honeycomb shape. In the case where the etching mask has such an upper surface shape, a semiconductor wafer whose upper surface is a polygon having five or more sides is obtained. A semiconductor wafer having a polygonal internal angle greater than 90° has a higher mechanical strength than a semiconductor wafer having a 90° internal angle of a polygon.

蝕刻掩膜14亦可具有如圖3C所示之圓形之上表面。於蝕刻掩膜具有此種上表面形狀之情形時，可獲得上表面為圓形之半導體晶片。上表面為圓形之半導體晶片具有與上表面為具有圓形狀角部之矩形之半導體晶片同等以上的機械強度。 The etch mask 14 can also have a circular upper surface as shown in Figure 3C. In the case where the etching mask has such an upper surface shape, a semiconductor wafer having a circular upper surface can be obtained. A semiconductor wafer having a circular upper surface has a mechanical strength equal to or higher than a rectangular semiconductor wafer having a rounded corner portion on its upper surface.

於半導體晶片之上表面形狀具有旋轉對稱性之情形時，無法僅基於半導體晶片之上表面形狀進行其方位對準。如圖3E所示般，若將蝕刻掩膜14之上表面設為不具有旋轉對稱性之形狀，則可獲得上表面不具有旋轉對稱性之形狀之半導體晶片。此種半導體晶片例如可僅基於上表面形狀進行其方位對準。再者，不具有旋轉對稱性之形狀並無特別限制，例如可列舉大於等於1個角部之形狀與其他角部之形狀不同之形狀、或設置有缺口之形狀。 In the case where the surface shape of the semiconductor wafer has rotational symmetry, it is not possible to perform its azimuthal alignment based only on the shape of the surface above the semiconductor wafer. As shown in FIG. 3E, if the upper surface of the etching mask 14 is a shape having no rotational symmetry, a semiconductor wafer having a shape in which the upper surface does not have rotational symmetry can be obtained. Such a semiconductor wafer can be aligned, for example, based only on the shape of the upper surface. Further, the shape having no rotational symmetry is not particularly limited, and examples thereof include a shape having a shape equal to or larger than one corner portion and a shape different from the shape of the other corner portions, or a shape having a notch.

形成於半導體基板上之蝕刻掩膜無需全部為相同之形狀。亦可將蝕刻掩膜14形成為例如圖3D所示般之不同形狀之圖案。 The etching mask formed on the semiconductor substrate need not all be the same shape. The etching mask 14 can also be formed into a pattern of different shapes such as shown in FIG. 3D.

於使用任一形狀之蝕刻掩膜之情形時，半導體晶片均以具有大致忠實地反映該掩膜之上表面形狀之上表面形狀之方式被單片化。 Where a etch mask of any shape is used, the semiconductor wafer is singulated in a manner that substantially faithfully reflects the shape of the surface above the shape of the surface above the mask.

作為絕緣膜15之材料，只要為可抑制貴金屬觸媒向半導體基板附著者則並無特別限定，使用有機及無機之任一種絕緣材料均可。作為有機之絕緣材料，例如可列舉聚醯亞胺、氟樹脂、酚樹脂、及環氧樹脂等有機樹脂。作為無機之絕緣材料，例如可列舉氧化膜及氮化膜等。絕緣膜15無需一定另外形成於元件區域12上。亦可將構成元件區域12之絕緣膜之一部分用作絕緣膜15。 The material of the insulating film 15 is not particularly limited as long as it can suppress adhesion of the noble metal catalyst to the semiconductor substrate, and any of an organic and inorganic insulating material can be used. Examples of the organic insulating material include organic resins such as polyimine, fluororesin, phenol resin, and epoxy resin. Examples of the inorganic insulating material include an oxide film and a nitride film. The insulating film 15 need not necessarily be additionally formed on the element region 12. A portion of the insulating film constituting the element region 12 can also be used as the insulating film 15.

再者，於使用如有機樹脂般具有衝擊吸收性之材料作為絕緣膜 之情形時，可將該絕緣膜作為永久膜而殘置於最終製品。若將殘留之絕緣膜用作單片化晶片之衝擊吸收膜，則成為單片化晶片之上表面完全被衝擊吸收膜覆蓋之構造，故而可提高晶片之機械強度。 Furthermore, a material having impact absorption such as an organic resin is used as an insulating film. In this case, the insulating film can be left as a permanent film and left in the final product. When the residual insulating film is used as the impact absorbing film of the singulated wafer, the surface of the singulated wafer is completely covered by the impact absorbing film, so that the mechanical strength of the wafer can be improved.

作為保護膜16之材料，只要為不會被蝕刻液侵蝕者則並無特別限定。例如，可使用聚醯亞胺、氟樹脂、酚樹脂、及環氧樹脂等有機樹脂、或Au、Ag及Pt等貴金屬形成保護膜16。 The material of the protective film 16 is not particularly limited as long as it is not corroded by the etching liquid. For example, the protective film 16 can be formed using an organic resin such as polyimide, fluororesin, phenol resin, or epoxy resin, or a noble metal such as Au, Ag, or Pt.

露出區域18係用於半導體晶片之單片化，相當於所謂之切割線。該露出區域18之寬度並無特別限定，例如為1μm至200μm之範圍。 The exposed region 18 is used for singulation of a semiconductor wafer, and corresponds to a so-called dicing line. The width of the exposed region 18 is not particularly limited and is, for example, in the range of 1 μm to 200 μm.

於露出區域18，如圖4所示般配置貴金屬觸媒22。此處，蝕刻掩膜14作為防止貴金屬觸媒22附著於露出區域18以外之部位之掩膜而發揮作用。於圖5中表示於露出區域18配置有貴金屬觸媒22之半導體基板10之俯視圖。 In the exposed region 18, the noble metal catalyst 22 is disposed as shown in FIG. Here, the etching mask 14 functions as a mask for preventing the noble metal catalyst 22 from adhering to a portion other than the exposed region 18. FIG. 5 is a plan view showing the semiconductor substrate 10 in which the noble metal catalyst 22 is disposed in the exposed region 18.

貴金屬觸媒22使與該貴金屬觸媒接觸之半導體基板10之氧化反應活化。可將具有使該氧化反應活化之效果之任意之貴金屬用作貴金屬觸媒22。貴金屬觸媒22之材料可選自例如Au、Ag、Pt、及Pd等。 The noble metal catalyst 22 activates the oxidation reaction of the semiconductor substrate 10 in contact with the noble metal catalyst. Any noble metal having an effect of activating the oxidation reaction can be used as the noble metal catalyst 22. The material of the noble metal catalyst 22 may be selected from, for example, Au, Ag, Pt, and Pd.

貴金屬觸媒22可呈例如粒狀配置。粒狀之貴金屬觸媒由於在蝕刻中亦穩定，故而較佳。作為粒狀觸媒之形狀，可列舉球狀、棒狀、及板狀等。於球狀之情形時，由於半導體基板之蝕刻進行之方向接近於垂直，故而較佳。粒狀觸媒之粒徑並無特別限定，可設為例如數十nm至數百nm之範圍。再者，為了容易地進行蝕刻後之晶片分割，粒狀觸媒較佳為高密度地或呈多層配置。 The noble metal catalyst 22 may be disposed, for example, in a granular form. The granular noble metal catalyst is preferred because it is also stable during etching. Examples of the shape of the granular catalyst include a spherical shape, a rod shape, and a plate shape. In the case of a spherical shape, it is preferable since the direction in which the etching of the semiconductor substrate proceeds is close to vertical. The particle diameter of the particulate catalyst is not particularly limited, and may be, for example, in the range of several tens of nm to several hundreds of nm. Further, in order to facilitate wafer division after etching, the particulate catalyst is preferably arranged in a high density or in a plurality of layers.

於圖6中，表示表現於露出區域18配置有粒狀之貴金屬觸媒22之半導體基板10之上表面之一部分的模式圖。 FIG. 6 is a schematic view showing a portion of the upper surface of the semiconductor substrate 10 in which the granular noble metal catalyst 22 is disposed in the exposed region 18.

貴金屬觸媒可藉由例如電解鍍敷、還原鍍敷、及置換鍍敷等方法，而配置於半導體基板10之露出區域18。又，亦可使用包含貴金屬 粒子之分散液之塗佈、蒸鍍、濺鍍等。於該等方法中，於使用置換鍍敷之情形時，可於相當於切割線之露出區域18均勻地直接形成粒狀之貴金屬觸媒。 The noble metal catalyst can be disposed in the exposed region 18 of the semiconductor substrate 10 by, for example, electrolytic plating, reduction plating, or displacement plating. Also, it can also be used with precious metals Coating, vapor deposition, sputtering, etc. of the dispersion of particles. In such a method, in the case of using displacement plating, a granular noble metal catalyst can be uniformly formed directly in the exposed region 18 corresponding to the dicing line.

於藉由置換鍍敷配置粒狀之貴金屬觸媒時，可使用例如硝酸銀溶液。以下，對該製程之一例進行說明。作為置換鍍敷液，可使用例如硝酸銀溶液、氫氟酸及水之混合液。氫氟酸具有去除半導體基板表面之自然氧化膜之作用。 When a granular noble metal catalyst is disposed by displacement plating, for example, a silver nitrate solution can be used. Hereinafter, an example of the process will be described. As the displacement plating solution, for example, a silver nitrate solution, a mixture of hydrofluoric acid and water can be used. Hydrofluoric acid has the function of removing the natural oxide film on the surface of the semiconductor substrate.

置換鍍敷液中之硝酸銀濃度較佳為0.001mol/L至0.1mol/L之範圍，更佳為0.005至0.01mol/L之範圍。置換鍍敷液中之氟化氫濃度較佳為1mol/L至6.5mol/L之範圍。 The silver nitrate concentration in the displacement plating solution is preferably in the range of 0.001 mol/L to 0.1 mol/L, more preferably in the range of 0.005 to 0.01 mol/L. The concentration of hydrogen fluoride in the displacement plating solution is preferably in the range of 1 mol/L to 6.5 mol/L.

藉由將特定之區域被蝕刻掩膜選擇性地保護之半導體基板10浸漬於如上所述之置換鍍敷液中1至5分鐘左右，可僅於半導體基板10之露出區域18選擇性地使作為粒狀之貴金屬觸媒22之Ag奈米粒子析出。再者，置換鍍敷液之溫度並無特別限定，只要適當設定為例如25℃、35℃等即可。 The semiconductor substrate 10 selectively protected by the etching mask in a specific region is immersed in the replacement plating solution as described above for about 1 to 5 minutes, and can be selectively used only in the exposed region 18 of the semiconductor substrate 10 The Ag nanoparticle of the granular noble metal catalyst 22 is precipitated. In addition, the temperature of the replacement plating solution is not particularly limited, and may be appropriately set to, for example, 25° C., 35° C., or the like.

於圖7中，表示藉由置換鍍敷而於矽基板上形成有Ag奈米粒子群之樣品之SEM圖像。此處，將特定之區域被蝕刻掩膜保護之單晶矽基板浸漬於25℃之置換鍍敷液中3分鐘，從而於單晶矽基板之露出區域形成Ag奈米粒子。 FIG. 7 shows an SEM image of a sample in which Ag nanoparticles are formed on a tantalum substrate by displacement plating. Here, the single crystal germanium substrate protected by the etching mask in a specific region was immersed in a displacement plating solution at 25 ° C for 3 minutes to form Ag nanoparticles in the exposed region of the single crystal germanium substrate.

作為蝕刻掩膜，使用包含聚醯亞胺膜之絕緣膜，作為置換鍍敷液，使用包含0.005mol/L之硝酸銀與5.0mol/L之氟化氫之水溶液。於圖7之SEM圖像中，相當於粒狀之貴金屬觸媒22之Ag奈米粒子22a係表示為白色區域。該等Ag奈米粒子22之粒徑為100nm左右。 As the etching mask, an insulating film containing a polyimide film was used, and as the displacement plating solution, an aqueous solution containing 0.005 mol/L of silver nitrate and 5.0 mol/L of hydrogen fluoride was used. In the SEM image of Fig. 7, the Ag nanoparticle 22a corresponding to the granular noble metal catalyst 22 is shown as a white region. The particle size of the Ag nanoparticles 22 is about 100 nm.

Ag奈米粒子22之粒徑可藉由例如變更浸漬時間或置換鍍敷液之濃度而控制。Ag奈米粒子之粒徑較佳為數十至數百nm左右。經確認若形成有具有此種範圍之粒徑之Ag奈米粒子，則於浸漬於蝕刻液 時，半導體基板之蝕刻良好地進行。 The particle size of the Ag nanoparticles 22 can be controlled, for example, by changing the immersion time or the concentration of the displacement plating solution. The particle diameter of the Ag nanoparticle is preferably from several tens to several hundreds of nm. It has been confirmed that if Ag nanoparticles having a particle diameter of such a range are formed, they are immersed in an etchant. At the time, the etching of the semiconductor substrate proceeds satisfactorily.

再者，未必單晶矽基板之露出區域之整個表面皆由Ag奈米粒子完全地覆蓋。於圖7之SEM圖像之一部分，將半導體基板10之表面之一部分表示為黑色區域。 Furthermore, the entire surface of the exposed region of the single crystal germanium substrate is not completely covered by the Ag nanoparticles. One of the surfaces of the semiconductor substrate 10 is shown as a black region in one of the SEM images of FIG.

此處，將使Si基板浸漬於組成不同之各種置換鍍敷液中1分鐘所得之結果之一例彙總於圖8中。置換鍍敷液中之硝酸銀溶液之濃度係設為0.001至0.05mol/L，氟化氫之濃度係設為3.5至6.5mol/L，且置換鍍敷液之溫度為25℃。 Here, an example of the result obtained by immersing the Si substrate in various replacement plating solutions having different compositions for one minute is summarized in FIG. The concentration of the silver nitrate solution in the displacement plating solution was set to 0.001 to 0.05 mol/L, the concentration of hydrogen fluoride was set to 3.5 to 6.5 mol/L, and the temperature of the displacement plating solution was 25 °C.

無論置換鍍敷液中之氟化氫之濃度為3.5至6.5mol/L之範圍內之何值，於硝酸銀之濃度大於等於0.03mol/L之情形時，Ag之結晶均呈樹狀成長，於硝酸銀之濃度為0.005至0.01mol/L之情形時，均可確認粒徑為10至100nm左右之Ag奈米粒子之形成。為了獲得所需粒徑之Ag奈米粒子，只要適當設定置換鍍敷液之組成及溫度、浸漬時間等而進行置換鍍敷即可。 Regardless of the value of the concentration of hydrogen fluoride in the displacement plating solution of 3.5 to 6.5 mol/L, when the concentration of silver nitrate is 0.03 mol/L or more, the crystal of Ag grows in a tree shape, and it is grown in silver nitrate. When the concentration is from 0.005 to 0.01 mol/L, the formation of Ag nanoparticles having a particle diameter of about 10 to 100 nm can be confirmed. In order to obtain Ag nanoparticles having a desired particle diameter, displacement plating may be performed by appropriately setting the composition, temperature, immersion time, and the like of the displacement plating solution.

將配置有貴金屬觸媒22之半導體基板如圖9所示般浸漬於蝕刻液30中。作為蝕刻液30，使用包含氫氟酸與氧化劑之混合液。藉由貴金屬觸媒22之作用，僅於與貴金屬觸媒22接觸之部位(露出區域18)半導體基板10發生氧化。可藉由氫氟酸將半導體基板10之已氧化之區域溶解去除，而僅選擇性地蝕刻與粒狀之貴金屬觸媒22接觸之部位。即，露出區域18之蝕刻係各向異性地進行。 The semiconductor substrate on which the noble metal catalyst 22 is disposed is immersed in the etching liquid 30 as shown in FIG. As the etching solution 30, a mixed solution containing hydrofluoric acid and an oxidizing agent is used. By the action of the noble metal catalyst 22, the semiconductor substrate 10 is oxidized only at the portion (exposed region 18) in contact with the noble metal catalyst 22. The oxidized region of the semiconductor substrate 10 can be dissolved and removed by hydrofluoric acid, and only the portion in contact with the granular noble metal catalyst 22 can be selectively etched. That is, the etching of the exposed region 18 is performed anisotropically.

於半導體基板10被選擇性地溶解去除時，貴金屬觸媒22自身不發生變化，隨著蝕刻之進行而向半導體基板10之下方移動，並於此處再次進行蝕刻。因此，於使半導體基板10浸漬於蝕刻液30之情形時，蝕刻係相對於半導體基板10之表面沿垂直方向進行而形成複數個溝槽或孔。於本實施形態中，將以此方式形成之溝槽或孔稱為深溝槽24a。於圖10中，表示於露出區域18形成有深溝槽24a之半導體基板10 之俯視圖。雖未清晰地表示，但於半導體基板10，在露出區域18形成有多個深溝槽24a。 When the semiconductor substrate 10 is selectively dissolved and removed, the noble metal catalyst 22 does not change itself, and moves to the lower side of the semiconductor substrate 10 as the etching progresses, and is etched again here. Therefore, when the semiconductor substrate 10 is immersed in the etching liquid 30, the etching system is formed in the vertical direction with respect to the surface of the semiconductor substrate 10 to form a plurality of grooves or holes. In the present embodiment, the grooves or holes formed in this manner are referred to as deep grooves 24a. In FIG. 10, the semiconductor substrate 10 in which the deep trench 24a is formed in the exposed region 18 is shown. Top view. Although not clearly shown, in the semiconductor substrate 10, a plurality of deep trenches 24a are formed in the exposed region 18.

形成深溝槽24a之區域可與圖7所示之Ag奈米粒子22a存在之區域(白色區域)對應。於圖7中之不存在Ag奈米粒子22a之區域(黑色區域)中，半導體基板10之蝕刻不進行。隨後對此進行說明。 The region where the deep trench 24a is formed may correspond to a region (white region) where the Ag nanoparticle 22a shown in Fig. 7 exists. In the region (black region) where the Ag nanoparticles 22a are not present in Fig. 7, the etching of the semiconductor substrate 10 is not performed. This will be explained later.

作為蝕刻液，可使用包含氫氟酸與氧化劑之混合液。氧化劑可選自過氧化氫、硝酸、AgNO3、KAuCl4、HAuCl4、K2PtCl6、H2PtCl6、Fe(NO3)3、Ni(NO3)2、Mg(NO3)2、Na2S2O8、K2S2O8、KMnO4、及K2Cr2O7等。就不產生有害之副產物，亦不產生元件區域之污染之方面而言，作為氧化劑較佳為過氧化氫。再者，亦可使用氟氣與氧化性氣體之混合氣體代替蝕刻液，藉由乾式製程推進蝕刻。 As the etching liquid, a mixed liquid containing hydrofluoric acid and an oxidizing agent can be used. The oxidizing agent may be selected from the group consisting of hydrogen peroxide, nitric acid, AgNO 3 , KAuCl 4 , HAuCl 4 , K 2 PtCl 6 , H 2 PtCl 6 , Fe(NO 3 ) 3 , Ni(NO 3 ) 2 , Mg(NO 3 ) 2 , Na 2 S 2 O 8 , K 2 S 2 O 8 , KMnO 4 , and K 2 Cr 2 O 7 . Hydrogen peroxide is preferred as the oxidizing agent in terms of not producing harmful by-products or causing contamination of the element region. Further, instead of the etching liquid, a mixed gas of a fluorine gas and an oxidizing gas may be used, and the etching may be advanced by a dry process.

蝕刻液中之氟化氫及氧化劑之濃度並無特別限定。例如可使用氟化氫濃度為5mol/L至15mol/L、過氧化氫濃度為0.3mol/L至5mol/L之水溶液。 The concentration of the hydrogen fluoride and the oxidizing agent in the etching solution is not particularly limited. For example, an aqueous solution having a hydrogen fluoride concentration of 5 mol/L to 15 mol/L and a hydrogen peroxide concentration of 0.3 mol/L to 5 mol/L can be used.

為了更確實地蝕刻半導體基板10之露出區域18，期望使用與基板之材質對應之氧化劑。例如，作為氧化劑，於Ge基板之情形時較佳為AgNO3等Ag系鹽，於SiC基板之情形時較佳為K2S2O8。於含有GaAs及GaN等III-V族半導體之基板或Si基板之情形時，作為氧化劑較佳為過氧化氫。其中，於使用Si基板之情形時，蝕刻尤其良好地進行。 In order to more reliably etch the exposed region 18 of the semiconductor substrate 10, it is desirable to use an oxidizing agent corresponding to the material of the substrate. For example, in the case of a Ge substrate, an Ag-based salt such as AgNO 3 is preferable as the oxidizing agent, and in the case of a SiC substrate, K 2 S 2 O 8 is preferable. In the case of a substrate containing a III-V semiconductor such as GaAs or GaN or a Si substrate, hydrogen peroxide is preferred as the oxidizing agent. Among them, in the case of using a Si substrate, the etching proceeds particularly well.

於圖11中，表示浸漬於蝕刻液後之單晶矽基板之剖面SEM圖像之一例。於單晶矽基板之露出區域，如圖7之SEM圖像所示般形成有複數個Ag奈米粒子。圖11之SEM圖像係將此種單晶矽基板浸漬於氟化氫濃度為10mol/L、過氧化氫濃度為1mol/L之水溶液中10分鐘所得之結果。 Fig. 11 shows an example of a cross-sectional SEM image of a single crystal germanium substrate immersed in an etching solution. In the exposed region of the single crystal germanium substrate, a plurality of Ag nanoparticles are formed as shown in the SEM image of FIG. The SEM image of Fig. 11 was obtained by immersing the single crystal germanium substrate in an aqueous solution having a hydrogen fluoride concentration of 10 mol/L and a hydrogen peroxide concentration of 1 mol/L for 10 minutes.

於圖11之SEM圖像中，區域A係被蝕刻掩膜保護之部分，區域B 係相當於配置有複數個Ag奈米粒子作為貴金屬觸媒之露出區域。於區域B，將複數個深溝槽表示為黑色區域。可知根據本實施形態，可於相當於蝕刻掩膜圖案之開口部之矽基板之露出區域形成複數個深溝槽。由於藉由所謂之自對準形成，故而位於相對於由蝕刻掩膜保護之區域A最近之位置的深溝槽可於與蝕刻掩膜之端面為同一面內具有側壁。 In the SEM image of FIG. 11, the region A is the portion protected by the etching mask, and the region B It is equivalent to an exposed area in which a plurality of Ag nano particles are arranged as a noble metal catalyst. In region B, a plurality of deep trenches are represented as black regions. According to the present embodiment, it is understood that a plurality of deep trenches can be formed in the exposed region of the germanium substrate corresponding to the opening portion of the etching mask pattern. Since the so-called self-alignment is formed, the deep trench located at the position closest to the region A protected by the etching mask may have sidewalls in the same plane as the end surface of the etching mask.

推進蝕刻，如圖12所示般使深溝槽24a到達至半導體基板10之背面。藉由預先將粒狀之貴金屬觸媒22高密度地配置於半導體基板10上之露出區域18，從而形成於該露出區域18之深溝槽24a之密度亦變高。藉由使複數個深溝槽24a相互連接而構成晶片分割溝槽24，於蝕刻完成之時點，半導體基板10被單片化為分別包含元件區域12之複數個晶片本體10'。再者，此處，將包含晶片本體10'與蝕刻掩膜14之構造28稱為晶片或半導體晶片。 The etching is advanced, and the deep trench 24a is reached to the back surface of the semiconductor substrate 10 as shown in FIG. By placing the granular noble metal catalyst 22 at a high density on the exposed region 18 on the semiconductor substrate 10 in advance, the density of the deep trenches 24a formed in the exposed regions 18 is also increased. The wafer dividing trenches 24 are formed by connecting a plurality of deep trenches 24a to each other. When the etching is completed, the semiconductor substrate 10 is singulated into a plurality of wafer bodies 10' each including the element regions 12. Further, here, the structure 28 including the wafer body 10' and the etching mask 14 is referred to as a wafer or a semiconductor wafer.

如圖12所示般，於經單片化所得之晶片本體10'之間且係相當於粒狀之貴金屬觸媒22之間隙之部位，產生有針狀殘留26。於圖13中，表示產生有針狀殘留26之半導體基板10之俯視圖。亦可於該時點完成單片化製程，拾取各晶片28而使用。該方法於可簡單地獲得經單片化所得之半導體晶片之方面有利。 As shown in Fig. 12, a needle-like residue 26 is formed in a portion of the wafer body 10' obtained by singulation and corresponding to the gap between the granular noble metal catalysts 22. FIG. 13 is a plan view showing the semiconductor substrate 10 in which the needle-like residue 26 is generated. The singulation process can also be completed at this point in time, and each wafer 28 can be picked up and used. This method is advantageous in that it is possible to easily obtain a semiconductor wafer obtained by singulation.

於單片化之後，若有需要，則亦可化學性地去除粒狀之貴金屬觸媒22。貴金屬觸媒22可藉由使用溶解液之濕式蝕刻而去除。作為溶解液，可使用能夠不侵蝕半導體基板10、絕緣膜15及保護膜16而去除貴金屬觸媒膜之任意之液體。具體而言，作為溶解液，可列舉鹵素溶液、鹵化銨溶液、硝酸、及王水等。 After singulation, the particulate noble metal catalyst 22 can also be chemically removed if necessary. The noble metal catalyst 22 can be removed by wet etching using a solution. As the solution, any liquid which can remove the noble metal catalyst film without eroding the semiconductor substrate 10, the insulating film 15, and the protective film 16 can be used. Specifically, examples of the solution include a halogen solution, an ammonium halide solution, nitric acid, and aqua regia.

於單片化之後，亦可視需要去除保護膜16。可應用利用稀釋劑所進行之溶解去除或利用O2電漿所進行之去除等，而去除保護膜16。 After singulation, the protective film 16 may also be removed as needed. The protective film 16 can be removed by dissolution removal by a diluent or removal by O 2 plasma or the like.

若有需要，則亦可去除絕緣膜15。對於絕緣膜15之去除方法， 可應用利用稀釋劑所進行之溶解去除、及利用各種電漿所進行之去除等。 The insulating film 15 can also be removed if necessary. For the removal method of the insulating film 15, Dissolution removal by a diluent, removal by various plasmas, and the like can be applied.

又，若有需要，則亦可蝕刻去除針狀殘留26。於已去除針狀殘留26之情形時，可減少於拾取半導體晶片28時針狀殘留作為灰塵附著於晶片之虞。 Further, if necessary, the needle-like residue 26 can be removed by etching. When the acicular residue 26 has been removed, it is possible to reduce the occurrence of needle-like residue as dust adheres to the wafer when the semiconductor wafer 28 is picked up.

針狀殘留26可藉由能夠蝕刻半導體基板材料之任意之蝕刻方法而去除。例如於矽基板之情形時，使用濕式蝕刻法及乾式蝕刻法之任一者均可。濕式蝕刻法中之蝕刻液可選自例如氫氟酸、硝酸及乙酸之混合液、氫氧化四甲基銨(TMAH，Tetramethyl Ammonium Hydroxide)、及KOH等。作為乾式蝕刻法，可列舉例如使用SF6、CF4、C2F6、C3F8、CClF2、CCl4、PCl3、CBrF3等氣體之電漿蝕刻。 The acicular residue 26 can be removed by any etching method capable of etching the semiconductor substrate material. For example, in the case of a tantalum substrate, either a wet etching method or a dry etching method can be used. The etching solution in the wet etching method may be selected, for example, from hydrofluoric acid, a mixed solution of nitric acid and acetic acid, tetramethylammonium hydroxide (TMAH, Tetramethyl Ammonium Hydroxide), and KOH. Examples of the dry etching method include plasma etching using a gas such as SF 6 , CF 4 , C 2 F 6 , C 3 F 8 , CClF 2 , CCl 4 , PCl 3 , or CBrF 3 .

於圖14中，表示一實施形態之半導體晶片28之立體圖。如圖示般，於一實施形態之半導體晶片28中，晶片本體10'之形成有元件區域之面係由被用作蝕刻掩膜之一部分之絕緣膜(未圖示)與被用作蝕刻掩膜之另一部分之保護膜16之積層體覆蓋。該保護膜16之端面至少局部地與晶片本體10'之側面為同一面。晶片本體10'之平面形狀、具體而言為上表面之輪廓可與保護膜16向包含該上表面之平面之正投影之輪廓至少部分一致。若採用該構造，則晶片本體10'之上表面中之自保護膜16露出之區域大幅度地減少。因此，可提高晶片之機械強度。保護膜16亦可覆蓋晶片本體10'之上表面全域。於該情形時，強度更進一步提高。 In Fig. 14, a perspective view of a semiconductor wafer 28 of an embodiment is shown. As shown, in the semiconductor wafer 28 of one embodiment, the surface of the wafer body 10' on which the element region is formed is an insulating film (not shown) used as a part of the etching mask and is used as an etching mask. The laminate of the protective film 16 of another portion of the film is covered. The end surface of the protective film 16 is at least partially flush with the side surface of the wafer body 10'. The planar shape of the wafer body 10', and in particular the contour of the upper surface, may at least partially coincide with the contour of the orthographic projection of the protective film 16 to the plane containing the upper surface. According to this configuration, the area exposed from the protective film 16 in the upper surface of the wafer main body 10' is greatly reduced. Therefore, the mechanical strength of the wafer can be improved. The protective film 16 may also cover the entire surface of the upper surface of the wafer body 10'. In this case, the strength is further increased.

於保護膜16為耐衝擊性較高之材料之情形時，保護膜16抑制因外部衝擊或拾取裝置之接觸而導致之晶片缺損之效果更進一步變大。作為耐衝擊性較高之材料，例如可列舉聚醯亞胺、氟樹脂、酚樹脂、及環氧樹脂等有機樹脂。 In the case where the protective film 16 is a material having high impact resistance, the effect of the protective film 16 on suppressing wafer defects due to external impact or contact of the pickup device is further increased. Examples of the material having high impact resistance include organic resins such as polyimine, fluororesin, phenol resin, and epoxy resin.

而且，如圖14所示般，該半導體晶片28之上表面之角部C1由於 為圓形狀，故而可提高耐衝擊性。於下表面，角部C2亦為圓形狀，故而本實施形態之半導體晶片28之抗彎強度不會降低。藉此，亦可大幅度地抑制因外部衝擊或晶片拾取裝置之接觸所導致之晶片之缺損。 Moreover, as shown in FIG. 14, the corner portion C1 of the upper surface of the semiconductor wafer 28 is It has a round shape and thus can improve impact resistance. On the lower surface, the corner portion C2 is also rounded, so that the bending strength of the semiconductor wafer 28 of the present embodiment does not decrease. Thereby, the defect of the wafer due to external impact or contact of the wafer pick-up device can be greatly suppressed.

本實施形態中之半導體晶片28係藉由使用化學性蝕刻處理之單片化而獲得者，因此，側面未受到物理性損傷。該方法使半導體晶片之動作之可靠性提高。 The semiconductor wafer 28 in the present embodiment is obtained by singulation using a chemical etching treatment, and therefore the side surface is not physically damaged. This method improves the reliability of the operation of the semiconductor wafer.

將使用絕緣膜作為蝕刻掩膜、且配置粒狀之貴金屬觸媒而將半導體基板單片化為半導體晶片之製程匯總於圖15A至圖15E。再者，此處省略保護膜16。 A process of singulating a semiconductor substrate into a semiconductor wafer using an insulating film as an etching mask and arranging a granular noble metal catalyst is summarized in FIGS. 15A to 15E. Furthermore, the protective film 16 is omitted here.

如圖15A所示般，於形成有複數個元件區域12之半導體基板10中，元件區域12係由作為蝕刻掩膜之絕緣膜15保護。蝕刻掩膜係於半導體基板10劃定為由蝕刻掩膜保護之區域與露出之區域即露出區域18。再者，於半導體基板10之背面設置有切割片材20。 As shown in FIG. 15A, in the semiconductor substrate 10 in which a plurality of element regions 12 are formed, the element region 12 is protected by an insulating film 15 as an etching mask. The etch mask is applied to the region of the semiconductor substrate 10 that is defined by the etch mask and the exposed region, that is, the exposed region 18. Further, a dicing sheet 20 is provided on the back surface of the semiconductor substrate 10.

於半導體基板10之露出區域18，如圖15B所示般配置粒狀之貴金屬觸媒22。半導體基板10係如圖15C所示般浸漬於蝕刻液30中。蝕刻於半導體基板10之露出區域18進行，而於露出區域18之各者形成複數個深溝槽24a。因形成複數個深溝槽24a，而於被蝕刻之區域產生針狀殘留。 In the exposed region 18 of the semiconductor substrate 10, a granular noble metal catalyst 22 is disposed as shown in Fig. 15B. The semiconductor substrate 10 is immersed in the etching liquid 30 as shown in FIG. 15C. The etching is performed on the exposed region 18 of the semiconductor substrate 10, and a plurality of deep trenches 24a are formed in each of the exposed regions 18. Due to the formation of a plurality of deep trenches 24a, needle-like residues are generated in the etched regions.

於蝕刻進行至半導體基板10之背面之後，如圖15D所示般，於與露出區域18對應之區域存在針狀殘留26。將切割片材20上之針狀殘留26及貴金屬觸媒22去除，而獲得如圖15E所示之半導體晶片28'。此處，半導體晶片28'包含晶片本體10'與絕緣膜15。於半導體晶片28'之間，如圖16之俯視圖所示般切割片材20露出。 After the etching proceeds to the back surface of the semiconductor substrate 10, as shown in FIG. 15D, there is a needle-like residue 26 in a region corresponding to the exposed region 18. The needle-like residue 26 on the dicing sheet 20 and the noble metal catalyst 22 are removed to obtain a semiconductor wafer 28' as shown in Fig. 15E. Here, the semiconductor wafer 28' includes the wafer body 10' and the insulating film 15. Between the semiconductor wafers 28', the cut sheet 20 is exposed as shown in the top view of FIG.

於圖15E所示之晶片本體10'之側面29，因位於蝕刻掩膜附近之粒狀之貴金屬觸媒22而引起以沿晶片本體10'之周向連續之方式形成有自上表面朝向下表面方向各自延伸之蝕刻痕。蝕刻痕係反映所使用之 粒狀之貴金屬觸媒22之大小或形狀的凹部或凸部，多數情況下形成為縱條紋，但亦存在形成為沿斜方向延伸之凹部或凸部之情形。形成蝕刻痕之凹部或凸部之寬度雖依存於粒狀之貴金屬觸媒之粒徑，但通常為10至100nm左右，尤其為10至50nm左右。 The side surface 29 of the wafer body 10' shown in FIG. 15E is formed from the upper surface toward the lower surface in a circumferential direction along the wafer body 10' due to the granular noble metal catalyst 22 located in the vicinity of the etching mask. The etch marks that extend in each direction. Etching traces reflect the use The concave portion or the convex portion of the size or shape of the granular noble metal catalyst 22 is often formed as a vertical stripe, but there is also a case where a concave portion or a convex portion extending in the oblique direction is formed. The width of the concave portion or the convex portion forming the etching mark depends on the particle diameter of the granular noble metal catalyst, but is usually about 10 to 100 nm, particularly about 10 to 50 nm.

將晶片本體10'之側面29之蝕刻痕之一例示於圖17A之模式圖。如圖示般，於側面29形成有奈米級之蝕刻痕32。蝕刻痕由於為奈米級之凹部或凸部，故而即便存在於晶片本體10'之側面29，亦不會發揮任何不利之作用。再者，根據蝕刻條件，蝕刻痕32亦存在並非縱條紋狀，而如圖17B所示般形成為形狀或配置不規則之凹部或凸部之情形。 One of the etching marks of the side surface 29 of the wafer body 10' is exemplified in the schematic view of Fig. 17A. As shown, a nano-scale etch mark 32 is formed on the side surface 29. Since the etching mark is a concave portion or a convex portion of the nano-scale, even if it exists on the side surface 29 of the wafer main body 10', it does not exert any adverse effect. Further, depending on the etching conditions, the etching marks 32 are also not formed in a vertical stripe shape, but are formed into a shape or an irregular concave portion or a convex portion as shown in FIG. 17B.

以下，對形成蝕刻痕32之製程及機制進行說明。 Hereinafter, the process and mechanism for forming the etching marks 32 will be described.

於在露出區域18形成有粒狀之貴金屬觸媒22之情形時，如圖6所示般，貴金屬觸媒22所占之區域之形狀並非與露出區域18之形狀完全一致，而具有與粒形狀對應之凹凸。若於精確之條件、例如氫氟酸10mol/L、過氧化氫2mol/L之條件下進行蝕刻，則蝕刻僅於極其靠近貴金屬觸媒22之附近發生。因此，於晶片本體10'之側壁，形成反映貴金屬觸媒22之粒形狀且自上表面朝向下表面方向各自延伸之蝕刻痕32。另一方面，若於蝕刻液之氧化劑濃度較高之條件、例如氫氟酸2.5mol/L、過氧化氫8mol/L之條件下進行蝕刻，則貴金屬觸媒22所影響之範圍會擴大。因此，蝕刻痕32已經不反映貴金屬觸媒22之粒形狀，而形成為不規則之凹凸形狀。 In the case where the granular noble metal catalyst 22 is formed in the exposed region 18, as shown in FIG. 6, the shape of the region occupied by the noble metal catalyst 22 does not completely coincide with the shape of the exposed region 18, but has a shape with the grain. Corresponding bumps. If the etching is performed under precise conditions, for example, hydrofluoric acid 10 mol/L and hydrogen peroxide 2 mol/L, the etching occurs only in the vicinity of the noble metal catalyst 22. Therefore, on the side wall of the wafer body 10', etching marks 32 reflecting the grain shape of the noble metal catalyst 22 and extending from the upper surface toward the lower surface direction are formed. On the other hand, if the etching is performed under the conditions of a high oxidizing agent concentration of the etching solution, for example, hydrofluoric acid of 2.5 mol/L and hydrogen peroxide of 8 mol/L, the range affected by the noble metal catalyst 22 is enlarged. Therefore, the etching mark 32 does not reflect the grain shape of the noble metal catalyst 22, but is formed into an irregular concavo-convex shape.

於藉由電漿蝕刻實施單片化之情形時，如圖17C所示般，因電漿處理中之切換動作，而導致於晶片本體10'之側面29形成相對於器件形成面平行之橫溝槽。具有此種構造之半導體晶片與本實施形態之半導體晶片不同。 When singulation is performed by plasma etching, as shown in FIG. 17C, the side surface 29 of the wafer body 10' forms a lateral groove parallel to the device formation surface due to the switching operation in the plasma processing. groove. The semiconductor wafer having such a structure is different from the semiconductor wafer of the present embodiment.

於側面29具有蝕刻痕之半導體晶片28'可如圖18所示般經由接合 材料34而固定於基板35上。再者，接合材料34例如為接著劑、黏著薄膜、或各向異性導電膜。又，基板35例如為電路基板或***式基板(interposer)。 The semiconductor wafer 28' having etch marks on the side 29 can be bonded via the bonding as shown in FIG. The material 34 is fixed to the substrate 35. Further, the bonding material 34 is, for example, an adhesive, an adhesive film, or an anisotropic conductive film. Moreover, the substrate 35 is, for example, a circuit board or an interposer.

於側面29具有蝕刻痕之構造與於側面29不具有蝕刻痕之構造相比表面積較大。因此，半導體晶片28'自該側面29之散熱效率較高。尤其是對於光半導體晶片或功率器件等而言，晶片之散熱性於保障晶片之正常動作方面為重要之特性。再者，於圖18中，於半導體晶片之上表面露出有電極墊51。隨後對電極墊進行說明。 The configuration having the etch marks on the side faces 29 is larger than the configuration in which the side faces 29 have no etch marks. Therefore, the heat dissipation efficiency of the semiconductor wafer 28' from the side surface 29 is high. Especially for optical semiconductor wafers or power devices, etc., the heat dissipation of the wafer is an important feature in securing the normal operation of the wafer. Further, in Fig. 18, an electrode pad 51 is exposed on the upper surface of the semiconductor wafer. The electrode pads are then described.

即便於如圖19所示般在基板35與半導體晶片28'之間配置有焊料36等接合構件之情形時，亦會發揮側面29之蝕刻痕之效果。於該情形時，剩餘焊料可藉由毛細管現象而於側面29上朝上方移動。藉此，使以基板35作為基準之晶片28'之高度降低，並且該高度之偏差亦得以抑制。又，可擴大焊料36之容許塗佈量限度，從而步驟管理變得容易。進而，於採用該構造之情形時，由於側面29與熱導率較高之焊料36接觸，故而亦可期待散熱量之增加。本效果於代替焊料36而使用底部填充劑作為接合構件之情形時亦相同。 In other words, when the bonding member such as the solder 36 is disposed between the substrate 35 and the semiconductor wafer 28' as shown in FIG. 19, the effect of etching the side surface 29 is also exhibited. In this case, the remaining solder can move upward on the side surface 29 by capillary action. Thereby, the height of the wafer 28' with the substrate 35 as a reference is lowered, and the deviation of the height is also suppressed. Moreover, the allowable coating amount limit of the solder 36 can be enlarged, and the step management becomes easy. Further, in the case of adopting this configuration, since the side surface 29 is in contact with the solder 36 having a high thermal conductivity, an increase in the amount of heat radiation can be expected. This effect is also the same when the underfill is used as the bonding member instead of the solder 36.

於將於側面29具有蝕刻痕之半導體晶片28'配置於引線框架上並進行樹脂模塑之情形時，可獲得如圖20所示之半導體裝置40。於圖示之半導體裝置40中，於引線框架41a上經由接合材料43而配置有半導體晶片28'。該半導體晶片28'係如上所述之於側面29具有奈米級之蝕刻痕者，且藉由Al線45而與引線框架41b電性連接。其等係除了引線框架41b之外部連接用端部以外，藉由模塑樹脂47a及47b密封。 When the semiconductor wafer 28' having the etching marks on the side surface 29 is disposed on the lead frame and resin-molded, a semiconductor device 40 as shown in FIG. 20 can be obtained. In the semiconductor device 40 shown in the drawing, the semiconductor wafer 28' is disposed on the lead frame 41a via the bonding material 43. The semiconductor wafer 28' has a nano-scale etching trace on the side surface 29 as described above, and is electrically connected to the lead frame 41b by the Al line 45. These are sealed by molding resins 47a and 47b except for the end portions for external connection of the lead frame 41b.

由於在半導體晶片28'之側面29形成有奈米級之蝕刻痕，故而可於半導體晶片28'與模塑樹脂47b之間發揮投錨效應(anchor effect)，而提高密接性。因此，即便為例如氟系樹脂等通常與晶片之密接性較弱之材料，亦可用作模塑樹脂，從而可擴大模塑材料選定之選項。 Since a nano-scale etching mark is formed on the side surface 29 of the semiconductor wafer 28', an anchor effect can be exerted between the semiconductor wafer 28' and the molding resin 47b, and the adhesion can be improved. Therefore, even a material which is generally weak in adhesion to a wafer, such as a fluorine-based resin, can be used as a molding resin, and the option of selecting a molding material can be expanded.

再者，即便於藉由保護膜16保護晶片本體10'之情形時，亦存在為了與外部電性連接而如圖21A所示般使電極墊51露出之情況。電極墊51通常含有鋁，故而對含有氫氟酸與氧化劑之蝕刻液之耐受性較弱。可藉由如圖21B所示般設置電極保護層52，而保護電極墊51不受蝕刻液侵蝕。 Further, even when the wafer body 10' is protected by the protective film 16, there is a case where the electrode pad 51 is exposed as shown in Fig. 21A in order to electrically connect to the outside. The electrode pad 51 usually contains aluminum, so that it is less resistant to an etchant containing hydrofluoric acid and an oxidizing agent. The electrode pad 52 can be protected from etching by the etching solution by providing the electrode protective layer 52 as shown in Fig. 21B.

電極保護層52可使用對蝕刻液具有耐受性之任意材料而形成，使用金屬及有機材料之任一者均可。於使用例如Ni/Au等金屬形成電極保護層52之情形時，即便電極保護層52殘存於電極墊51上亦不會於後續步驟中產生問題。使用樹脂而形成之電極保護層52只要於蝕刻處理後藉由適當之方法去除即可。 The electrode protective layer 52 can be formed using any material that is resistant to the etching liquid, and any of a metal and an organic material can be used. When the electrode protective layer 52 is formed using a metal such as Ni/Au, even if the electrode protective layer 52 remains on the electrode pad 51, no problem occurs in the subsequent steps. The electrode protective layer 52 formed using a resin may be removed by an appropriate method after the etching treatment.

此處，參照圖22，對保護元件區域之保護膜等之尺寸進行說明。形成元件區域之半導體基板10之厚度通常為數百μm左右，元件區域所包含之複數個絕緣膜54及配線55之厚度為數十至數百nm左右。配線55之線與間隙分別為數十至數百nm左右之寬度。再者，絕緣膜54通常含有SiN等。 Here, the size of the protective film or the like of the protective element region will be described with reference to Fig. 22 . The thickness of the semiconductor substrate 10 forming the element region is usually about several hundred μm, and the thickness of the plurality of insulating films 54 and wirings 55 included in the element region is about several tens to several hundreds nm. The line and the gap of the wiring 55 are each a width of several tens to several hundreds of nm. Further, the insulating film 54 usually contains SiN or the like.

保護元件區域之保護膜16之線與間隙分別為數十至數百μm左右之寬度。考慮到存在於半導體基板10之最表面之凹凸，該保護膜16係以數μm至數十μm左右之厚度形成。 The line and the gap of the protective film 16 in the protective element region are each a width of several tens to several hundreds of μm. The protective film 16 is formed to have a thickness of about several μm to several tens of μm in consideration of irregularities existing on the outermost surface of the semiconductor substrate 10.

如參照圖22所說明般，保護元件區域12之保護膜16之厚度為數μm至數十μm左右，相對於此，元件區域12中之絕緣膜54之厚度為數十至數百nm左右。由於元件區域12中之絕緣膜54極薄，故而於將該絕緣膜54用作蝕刻掩膜之情形時，可形成微細之露出區域。參照圖23，對該製程進行說明。 As described with reference to Fig. 22, the thickness of the protective film 16 of the protective element region 12 is about several μm to several tens of μm, whereas the thickness of the insulating film 54 in the element region 12 is about several tens to several hundreds nm. Since the insulating film 54 in the element region 12 is extremely thin, when the insulating film 54 is used as an etching mask, a fine exposed region can be formed. The process will be described with reference to FIG. 23.

如圖23A所示般，於在背面配置有切割片材20之半導體基板10形成有複數個元件區域12，且於各元件區域12上依序積層絕緣膜54及保護膜16。於鄰接之元件區域12之間，存在半導體基板10露出之露出區 域18'。如上所述般絕緣膜54之厚度為數十至數百nm左右，故而露出區域18'之寬度亦可微細地設為數十至數百nm左右。 As shown in FIG. 23A, a plurality of element regions 12 are formed on the semiconductor substrate 10 on which the dicing sheet 20 is disposed on the back surface, and the insulating film 54 and the protective film 16 are sequentially laminated on the respective element regions 12. Between the adjacent element regions 12, there is an exposed area where the semiconductor substrate 10 is exposed. Domain 18'. As described above, the thickness of the insulating film 54 is about several tens to several hundreds of nm. Therefore, the width of the exposed region 18' can be finely set to about several tens to several hundreds of nm.

如圖23B所示般，於露出區域18'配置貴金屬觸媒22。此時，藉由採用如上所述之置換鍍敷法，可避開絕緣膜54上及保護膜16上，而僅於露出區域18'上選擇性地配置貴金屬觸媒22。 As shown in Fig. 23B, the noble metal catalyst 22 is disposed in the exposed region 18'. At this time, by using the displacement plating method as described above, the noble metal catalyst 22 can be selectively disposed only on the exposed region 18' while avoiding the insulating film 54 and the protective film 16.

將選擇性地於露出區域18'配置有貴金屬觸媒22之半導體基板10浸漬於如上所述之蝕刻液中。藉此，選擇性地去除半導體基板之露出區域18'。其結果，形成如圖23C所示之晶片分割溝槽24，而將半導體基板10單片化為晶片本體。 The semiconductor substrate 10 in which the noble metal catalyst 22 is selectively disposed in the exposed region 18' is immersed in the etching liquid as described above. Thereby, the exposed region 18' of the semiconductor substrate is selectively removed. As a result, the wafer dividing trench 24 as shown in FIG. 23C is formed, and the semiconductor substrate 10 is singulated into a wafer body.

根據該方法，由於被用作露出切割線之露出區域18'之寬度相當於絕緣膜54間之間隔，故而理論上可將切割線之寬度設為數十至數百nm左右。於切割線變細而有效之晶片面積增加之方面，該情況較為有利。 According to this method, since the width of the exposed region 18' used as the exposed dicing line corresponds to the interval between the insulating films 54, the width of the dicing line can theoretically be set to about several tens to several hundreds of nm. This is advantageous in terms of an increase in the area of the wafer where the cutting line is thin and effective.

配置於半導體基板之露出區域之貴金屬觸媒並不限定於粒狀，亦可為膜狀。以下，對將膜狀之貴金屬觸媒形成於半導體基板之露出區域而進行單片化之方法進行說明。 The noble metal catalyst disposed in the exposed region of the semiconductor substrate is not limited to a granular shape, and may be in the form of a film. Hereinafter, a method of forming a film-form noble metal catalyst in an exposed region of a semiconductor substrate and singulating it will be described.

圖24A係形成有複數個元件區域12之半導體基板10之局部剖視圖。各元件區域12由絕緣膜15保護。絕緣膜15劃定出半導體基板10中之被絕緣膜15覆蓋之區域與半導體基板10之露出之部分即露出區域18。再者，於半導體基板10之背面設置有切割片材20。將該半導體基板10之俯視圖示於圖24B。 24A is a partial cross-sectional view of a semiconductor substrate 10 in which a plurality of element regions 12 are formed. Each element region 12 is protected by an insulating film 15. The insulating film 15 defines an exposed region 18 which is a portion of the semiconductor substrate 10 covered by the insulating film 15 and which is exposed by the semiconductor substrate 10. Further, a dicing sheet 20 is provided on the back surface of the semiconductor substrate 10. A plan view of the semiconductor substrate 10 is shown in Fig. 24B.

於形成有絕緣膜15之半導體基板10之整個上表面，如圖25A所示般形成金屬觸媒膜57。金屬觸媒膜57可藉由例如濺鍍或蒸鍍而形成。藉由利用該方法成膜，可獲得均勻膜厚之金屬觸媒膜57。若考慮蝕刻等後續步驟，則期望將金屬觸媒膜57之膜厚設為10至50nm左右。由於在半導體基板10之整個面形成金屬觸媒膜57，故而如圖25B之俯視 圖所示般，絕緣膜15及露出區域18被金屬觸媒膜57覆蓋。 On the entire upper surface of the semiconductor substrate 10 on which the insulating film 15 is formed, a metal catalyst film 57 is formed as shown in FIG. 25A. The metal catalyst film 57 can be formed by, for example, sputtering or evaporation. By forming a film by this method, a metal catalyst film 57 having a uniform film thickness can be obtained. When a subsequent step such as etching is considered, it is desirable to set the thickness of the metal catalyst film 57 to about 10 to 50 nm. Since the metal catalyst film 57 is formed on the entire surface of the semiconductor substrate 10, it is as seen in FIG. 25B. As shown in the figure, the insulating film 15 and the exposed region 18 are covered by the metal catalyst film 57.

繼而，如圖26A所示般，形成抗蝕圖案58，而選擇性地保護金屬觸媒膜57中之位於露出區域18上之區域。抗蝕圖案58係只要藉由常用方法形成並保護金屬觸媒膜57之特定區域即可。如圖26B之俯視圖所示般，由於在與露出區域對應之部分形成抗蝕圖案58，故而金屬觸媒膜57於絕緣膜15之位置露出。 Then, as shown in FIG. 26A, a resist pattern 58 is formed, and a region of the metal catalyst film 57 on the exposed region 18 is selectively protected. The resist pattern 58 is only required to form and protect a specific region of the metal catalyst film 57 by a usual method. As shown in the plan view of FIG. 26B, since the resist pattern 58 is formed in a portion corresponding to the exposed region, the metal catalyst film 57 is exposed at the position of the insulating film 15.

若藉由常用方法去除金屬觸媒膜57之露出部分，則如圖27A所示般，僅於抗蝕圖案58之位置殘置金屬觸媒膜57。將該狀態之半導體基板10之俯視圖示於圖27B。金屬觸媒膜57之露出部分可使用例如鹵素溶液、鹵化銨溶液、硝酸、及王水等去除。 When the exposed portion of the metal catalyst film 57 is removed by a usual method, as shown in FIG. 27A, the metal catalyst film 57 is left only at the position of the resist pattern 58. A plan view of the semiconductor substrate 10 in this state is shown in Fig. 27B. The exposed portion of the metal catalyst film 57 can be removed using, for example, a halogen solution, an ammonium halide solution, nitric acid, aqua regia, or the like.

其後，將抗蝕圖案58剝離，而如圖28A所示般使經圖案化之金屬觸媒膜57'露出。抗蝕圖案58係只要根據抗蝕劑材料使用適當之剝離液剝離即可。如圖28B之俯視圖所示般，經圖案化之金屬觸媒膜57'僅殘置於露出區域18上。 Thereafter, the resist pattern 58 is peeled off, and the patterned metal catalyst film 57' is exposed as shown in FIG. 28A. The resist pattern 58 may be peeled off by using a suitable stripping liquid depending on the resist material. As shown in the top view of FIG. 28B, the patterned metal catalyst film 57' remains only on the exposed area 18.

將經圖案化之金屬觸媒膜57'用作蝕刻掩膜，並按照如上所述之步驟選擇性地去除半導體基板10之基板去除區域18。藉此，如圖29A所示般，半導體基板10被單片化為晶片本體10'，從而獲得包含晶片本體10'與絕緣膜15之半導體晶片59。金屬觸媒膜57'係於該狀態下向下方移動，如圖示般到達至切割片材20。將經單片化所得之複數個半導體晶片59之俯視圖示於圖29B。 The patterned metal catalyst film 57' is used as an etching mask, and the substrate removal region 18 of the semiconductor substrate 10 is selectively removed in accordance with the steps described above. Thereby, as shown in FIG. 29A, the semiconductor substrate 10 is singulated into the wafer body 10', thereby obtaining the semiconductor wafer 59 including the wafer body 10' and the insulating film 15. The metal catalyst film 57' moves downward in this state, and reaches the cut sheet 20 as illustrated. A plan view of a plurality of semiconductor wafers 59 obtained by singulation is shown in Fig. 29B.

於使用膜狀之貴金屬觸媒之情形時，與配置粒狀之貴金屬觸媒之情形相比，膜厚之控制變得容易。於使用膜狀之貴金屬觸媒之情形時，可與半導體基板材料之種類無關而使用任意金屬形成觸媒膜。此外，於該情形時，亦不會產生針狀殘留。 In the case of using a film-shaped noble metal catalyst, the control of the film thickness is easier than in the case of arranging a granular noble metal catalyst. In the case of using a film-shaped noble metal catalyst, a catalyst film can be formed using any metal regardless of the kind of the semiconductor substrate material. In addition, in this case, needle-like residue does not occur.

於以上之例中，雖於半導體基板之背面直接接觸而設置有切割片材，但並不限定於此。亦可如圖30所示般介隔金屬化層70而於半導 體基板10之背面設置切割片材20。金屬化層70可使用任意金屬而形成，且設為單層膜及多層膜之任一構造均可。 In the above example, the cut sheet is provided in direct contact with the back surface of the semiconductor substrate, but the invention is not limited thereto. Alternatively, as shown in FIG. 30, the metallization layer 70 may be interposed to be semi-conductive. A cut sheet 20 is provided on the back surface of the body substrate 10. The metallization layer 70 can be formed using any metal, and can be either a single layer film or a multilayer film.

尤其於金屬化層70中含有Au、Ag、Pt等貴金屬之情形時，可於半導體基板10之蝕刻進行而到達至背面時，抑制切割片材之接著層被蝕刻液侵蝕。視情形，亦可直接殘留金屬化層70，將其用作對經單片化所得之晶片進行黏晶時之金屬化膜。 In particular, when the metallization layer 70 contains a noble metal such as Au, Ag or Pt, it is possible to suppress the etching of the etching layer of the dicing sheet by the etching liquid when the semiconductor substrate 10 is etched and reaches the back surface. As the case may be, the metallization layer 70 may be directly left and used as a metallized film when the wafer obtained by singulation is subjected to die bonding.

亦可組合如上所述之化學性蝕刻與基板研磨而進行單片化。該製程係所謂之先切割後研磨(dicing before grinding，DBG)法。參照圖31A及圖31B，對該製程進行說明。 It can also be singulated by combining the chemical etching and the substrate polishing as described above. This process is the so-called dicing before grinding (DBG) method. The process will be described with reference to FIGS. 31A and 31B.

首先，如圖31A所示般，對半導體基板10，以大於等於晶片本體10'之厚度的深度形成晶片分離溝槽24。其後，如圖31B所示般，藉由基板研磨裝置72去除半導體基板10之下表面側區域直至到達晶片分離溝槽24為止，從而獲得半導體晶片28。 First, as shown in FIG. 31A, for the semiconductor substrate 10, the wafer separation trench 24 is formed at a depth greater than or equal to the thickness of the wafer body 10'. Thereafter, as shown in FIG. 31B, the lower surface side region of the semiconductor substrate 10 is removed by the substrate polishing device 72 until reaching the wafer separation trench 24, thereby obtaining the semiconductor wafer 28.

半導體基板10之下表面側區域亦可藉由蝕刻而去除。作為蝕刻，例如可列舉濕式蝕刻或電漿蝕刻，上述濕式蝕刻係使用選自氫氟酸、硝酸及乙酸之混合液、TMAH、及KOH等之蝕刻液，上述電漿蝕刻係使用選自SF6、CF4、C2F6、C3F8、CClF2、CCl4、PCl3、及CBrF3等之氣體。 The lower surface side region of the semiconductor substrate 10 can also be removed by etching. Examples of the etching include wet etching or plasma etching, and the wet etching uses an etching liquid selected from the group consisting of hydrofluoric acid, a mixed solution of nitric acid and acetic acid, TMAH, and KOH, and the plasma etching system is selected from the group consisting of Gases such as SF 6 , CF 4 , C 2 F 6 , C 3 F 8 , CClF 2 , CCl 4 , PCl 3 , and CBrF 3 .

於採用先切割後研磨法之情形時，由於用以形成分離溝槽24之蝕刻係於分離溝槽24到達至半導體基板之背面之前停止，故而可於該蝕刻剛結束後保持半導體基板之剛性。因此，該方法有蝕刻剛結束後之基板之處理容易之優點。 In the case where the first dicing and post-polishing method is employed, since the etching for forming the separation trench 24 is stopped before the separation trench 24 reaches the back surface of the semiconductor substrate, the rigidity of the semiconductor substrate can be maintained immediately after the etching. Therefore, this method has an advantage that the processing of the substrate immediately after the etching is easy.

如以上所說明般，於一實施形態之方法中，可對相當於切割線之半導體基板之露出區域全體同時進行蝕刻加工，從而獲得半導體晶片。因此，即便變更例如切割線之數量，亦可於一定時間內完成單片化。而且，由於可藉由批次處理同時對複數個半導體基板進行加工， 故而每一片基板之加工時間被大幅度縮短，從而生產性提高。 As described above, in the method of one embodiment, the entire exposed region of the semiconductor substrate corresponding to the dicing line can be simultaneously etched to obtain a semiconductor wafer. Therefore, even if the number of the cutting lines is changed, for example, the singulation can be completed in a certain period of time. Moreover, since a plurality of semiconductor substrates can be processed simultaneously by batch processing, Therefore, the processing time of each substrate is greatly shortened, and productivity is improved.

又，於一實施形態之方法中，藉由使用貴金屬觸媒與蝕刻液或蝕刻氣體之化學性蝕刻處理進行單片化。因此，該方法中無需光學性對位，而不會產生因對位標記之讀取誤差或基板扭曲等而引起之位置偏差。而且，由於可利用保護樹脂覆蓋晶片本體之上表面端部之實質性全體，故而能夠儘可能地減少破裂或缺損。 Further, in the method of one embodiment, singulation is performed by a chemical etching treatment using a noble metal catalyst and an etching liquid or an etching gas. Therefore, in this method, optical alignment is not required, and positional deviation due to reading error of the alignment mark, substrate distortion, or the like is not generated. Further, since the substantial portion of the upper end surface of the wafer body can be covered with the protective resin, cracking or chipping can be reduced as much as possible.

已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並不意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施形態及其變化包含於發明之範圍或主旨，並且包含於申請專利範圍所記載之發明及其均等之範圍內。本實施形態包含以下態樣。 The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention may be embodied in other specific forms and various modifications, substitutions and changes may be made without departing from the scope of the invention. The scope of the invention and the scope of the invention are included in the scope of the invention and the scope of the invention as set forth in the appended claims. This embodiment includes the following aspects.

[1]一種半導體晶片之製造方法，其包括如下步驟：於半導體基板上形成分別包含保護膜之複數個蝕刻掩膜，而劃定上述半導體基板中之被上述複數個蝕刻掩膜保護之複數個第1區域、及上述半導體基板中之露出之區域即第2區域；以及藉由化學性蝕刻處理將上述第2區域各向異性地去除，而形成分別具有至少一部分位於與上述蝕刻掩膜之端面為同一面內之側壁、及到達至上述半導體基板之背面之底部的複數個溝槽，藉此，將上述半導體基板單片化為與上述複數個第1區域對應之複數個晶片本體。 [1] A method of manufacturing a semiconductor wafer, comprising: forming a plurality of etching masks each including a protective film on a semiconductor substrate, and defining a plurality of the semiconductor substrates protected by the plurality of etching masks; a first region and a second region which is an exposed region of the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process to form an end face each having at least a portion located on the etching mask A plurality of trenches in the same plane and a plurality of trenches reaching the bottom of the back surface of the semiconductor substrate, thereby singulating the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions.

[2]如[1]之方法，其中上述蝕刻掩膜之上表面不具有由一端彼此相接之2條線段界定之角部。 [2] The method of [1], wherein the upper surface of the etching mask does not have a corner defined by two line segments whose ends are in contact with each other.

[3]如[1]之方法，其中上述蝕刻掩膜之上表面為具有大於等於5條邊 之多邊形。 [3] The method of [1], wherein the upper surface of the etching mask has 5 or more sides The polygon.

[4]如[1]至[3]中任一項之方法，其中上述化學性蝕刻處理包括如下步驟：於上述第2區域設置貴金屬觸媒，其後，使蝕刻液或蝕刻氣體接觸於上述半導體基板。 [4] The method according to any one of [1] to [3] wherein the chemical etching treatment comprises the steps of: providing a noble metal catalyst in the second region, and thereafter contacting the etching liquid or the etching gas to the above Semiconductor substrate.

[5]如[4]之方法，其係藉由無電解鍍敷於上述第2區域設置上述貴金屬觸媒。 [5] The method according to [4], wherein the noble metal catalyst is provided in the second region by electroless plating.

[6]如[4]或[5]之方法，其中上述貴金屬觸媒為粒狀。 [6] The method according to [4] or [5] wherein the noble metal catalyst is granular.

[7]如[4]至[6]中任一項之方法，其中上述化學性蝕刻處理包括使上述蝕刻液接觸於上述半導體基板之步驟，且上述蝕刻液包含氫氟酸與過氧化氫。 [7] The method according to any one of [4] to [6] wherein the chemical etching treatment comprises the step of contacting the etching liquid to the semiconductor substrate, and the etching liquid contains hydrofluoric acid and hydrogen peroxide.

[8]如[1]至[7]中任一項之方法，其中進行上述化學性蝕刻處理以使上述複數個晶片本體之各者於其端面具有自上述晶片本體之形成有上述保護膜之面朝向相反側之面各自延伸之條紋狀之凹部或凸部。 [8] The method of any one of [1] to [7] wherein the chemical etching treatment is performed such that each of the plurality of wafer bodies has a protective film formed from the wafer body at the end surface thereof Stripe-shaped recesses or projections each extending toward the opposite side.

[9]如[8]之方法，其中上述凹部或凸部之各者具有10至100nm之寬度。 [9] The method of [8], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 100 nm.

[10]如[8]之方法，其中上述凹部或凸部之各者具有10至50nm之寬度。 [10] The method of [8], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 50 nm.

[11]如[1]至[10]中任一項之方法，其中上述複數個第1區域包含具有 電極墊之半導體元件。 [11] The method of any one of [1] to [10] wherein the plurality of first regions include A semiconductor component of an electrode pad.

[12]如[1]至[11]中任一項之方法，其中上述半導體基板為矽基板。 [12] The method of any one of [1] to [11] wherein the semiconductor substrate is a germanium substrate.

[13]一種半導體晶片，其包括晶片本體，該晶片本體具有包含半導體元件之表面區域，且上述晶片本體之端面具有蝕刻痕。 [13] A semiconductor wafer comprising a wafer body having a surface region including a semiconductor element, and an end surface of the wafer body having an etching mark.

[14]如[13]之半導體晶片，其中上述蝕刻痕係自上述晶片本體之上述表面區域側之面朝向相反側之面各自延伸之條紋狀之凹部或凸部。 [14] The semiconductor wafer according to [13], wherein the etching trace is a stripe-shaped concave portion or a convex portion extending from a surface of the wafer body on a surface side of the surface side toward an opposite side.

[15]如[14]之半導體晶片，其中上述凹部或凸部之各者具有10至100nm之寬度。 [15] The semiconductor wafer according to [14], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 100 nm.

[16]如[14]之半導體晶片，其中上述凹部或凸部之各者具有10至50nm之寬度。 [16] The semiconductor wafer according to [14], wherein each of the above-mentioned concave portions or convex portions has a width of 10 to 50 nm.

[17]如[13]至[16]中任一項之半導體晶片，其進而包括覆蓋上述表面區域之保護膜，且上述晶片本體之上述表面區域側之面之輪廓與上述保護膜向包含上述表面區域側之面之平面的正投影之輪廓至少部分一致。 [17] The semiconductor wafer according to any one of [13], further comprising a protective film covering the surface region, wherein a contour of a surface of the surface of the wafer body on the side of the surface region and the protective film are included The contours of the orthographic projections of the planes of the faces on the side of the surface region are at least partially identical.

[18]如[13]至[17]中任一項之半導體晶片，其中上述晶片本體之上述表面區域側之面不具有由一端彼此相接之2條線段界定之角部。 [18] The semiconductor wafer according to any one of [13] to [17] wherein the surface of the wafer body on the surface area side does not have a corner portion defined by two line segments whose ends are in contact with each other.

[19]一種半導體晶片，其包括：晶片本體，其具有包含半導體元件之表面區域；及保護膜，其覆蓋上述表面區域；且上述晶片本體係藉 由在半導體基板上形成包含上述保護膜之蝕刻掩膜，並將該半導體基板供於使用貴金屬觸媒與蝕刻液或蝕刻氣體之化學性蝕刻處理中而單片化所得者，上述晶片本體之上述表面區域側之面之輪廓與上述保護膜向包含該上表面之平面的正投影之輪廓至少部分一致。 [19] A semiconductor wafer comprising: a wafer body having a surface region including a semiconductor element; and a protective film covering the surface region; and the wafer system borrowing Forming an etching mask including the protective film on a semiconductor substrate, and supplying the semiconductor substrate to a chemical etching treatment using a noble metal catalyst and an etching liquid or an etching gas, wherein the wafer body is as described above The contour of the surface on the side of the surface region at least partially coincides with the contour of the orthographic projection of the protective film to the plane containing the upper surface.

[20]一種半導體晶片，其包括晶片本體，該晶片本體具有包含半導體元件之表面區域，且上述晶片本體係藉由在半導體基板上形成包含保護膜之蝕刻掩膜，並將該半導體基板供於使用貴金屬觸媒與蝕刻液或蝕刻氣體之化學性蝕刻處理中而單片化所得者，上述晶片本體之上述表面區域側之面不具有由一端彼此相接之2條線段界定之角部。 [20] A semiconductor wafer comprising a wafer body having a surface region including a semiconductor element, and the wafer system is formed by forming an etching mask including a protective film on the semiconductor substrate In the chemical etching treatment using a noble metal catalyst and an etching liquid or an etching gas, the surface of the wafer body on the surface side side does not have a corner portion defined by two line segments whose ends are in contact with each other.

[21]一種半導體裝置，其包括：支持構件；如[13]至[20]中任一項之半導體晶片，其位於上述支持構件上；及模塑樹脂，其以覆蓋上述半導體晶片之方式設置於上述支持構件上。 [21] A semiconductor device comprising: a support member; the semiconductor wafer according to any one of [13] to [20], which is located on the support member; and a molding resin which is disposed in such a manner as to cover the semiconductor wafer On the above support member.

[22]一種半導體裝置，其包括：支持構件；如[13]至[20]中任一項之半導體晶片，其位於上述支持構件上；及接合構件，其介於上述支持構件與上述半導體晶片之間。 [22] A semiconductor device comprising: a support member; the semiconductor wafer according to any one of [13] to [20], which is located on the support member; and a bonding member interposed between the support member and the semiconductor wafer between.

10‧‧‧半導體基板 10‧‧‧Semiconductor substrate

12‧‧‧元件區域 12‧‧‧Component area

14‧‧‧蝕刻掩膜 14‧‧‧ etching mask

15‧‧‧絕緣膜 15‧‧‧Insulation film

16‧‧‧保護膜 16‧‧‧Protective film

20‧‧‧切割片材 20‧‧‧Cut sheet

22‧‧‧貴金屬觸媒 22‧‧‧ precious metal catalyst

Claims (15)

一種半導體晶片之製造方法，其包括如下步驟：於半導體基板上形成分別包含保護膜之複數個蝕刻掩膜，而劃定上述半導體基板中之被上述複數個蝕刻掩膜保護之複數個第1區域、及上述半導體基板中之露出之區域即第2區域；以及藉由化學性蝕刻處理將上述第2區域各向異性地去除，而形成分別具有至少一部分位於與上述蝕刻掩膜之端面為同一面內之側壁、及到達至上述半導體基板之背面之底部的複數個溝槽，藉此，將上述半導體基板單片化為與上述複數個第1區域對應之複數個晶片本體。 A method of manufacturing a semiconductor wafer, comprising: forming a plurality of etching masks each including a protective film on a semiconductor substrate, and defining a plurality of first regions of the semiconductor substrate protected by the plurality of etching masks And a second region which is an exposed region of the semiconductor substrate; and the second region is anisotropically removed by a chemical etching process, and each of the second regions is formed to have at least a portion located on the same surface as the end surface of the etching mask The inner sidewall and the plurality of trenches reaching the bottom of the back surface of the semiconductor substrate, thereby singulating the semiconductor substrate into a plurality of wafer bodies corresponding to the plurality of first regions. 如請求項1之方法，其中上述蝕刻掩膜之上表面不具有由一端彼此相接之2條線段界定之角部。 The method of claim 1, wherein the upper surface of the etching mask does not have a corner defined by two line segments whose ends are in contact with each other. 如請求項2之方法，其中上述化學性蝕刻處理包括如下步驟：於上述第2區域設置貴金屬觸媒，其後，使蝕刻液或蝕刻氣體接觸於上述半導體基板。 The method of claim 2, wherein the chemical etching treatment comprises the step of disposing a noble metal catalyst in the second region, and thereafter contacting the etching solution or the etching gas with the semiconductor substrate. 如請求項3之方法，其中上述貴金屬觸媒為粒狀。 The method of claim 3, wherein the noble metal catalyst is granular. 如請求項4之方法，其中進行上述化學性蝕刻處理以使上述複數個晶片本體之各者於其端面具有自上述晶片本體之形成有上述保護膜之面朝向相反側之面各自延伸之條紋狀之凹部或凸部。 The method of claim 4, wherein the chemical etching treatment is performed such that each of the plurality of wafer bodies has a stripe shape extending from a surface of the wafer body on which the protective film is formed toward the opposite side a recess or a protrusion. 如請求項5之方法，其中上述凹部或凸部之各者具有10至100nm之寬度。 The method of claim 5, wherein each of said concave or convex portions has a width of 10 to 100 nm. 如請求項6之方法，其中上述半導體基板為矽基板。 The method of claim 6, wherein the semiconductor substrate is a germanium substrate. 一種半導體晶片，其包括晶片本體，該晶片本體具有包含半導體元件之表面區域，且上述晶片本體之端面具有自上述晶片本體之上述表面區域側之面朝向相反側之面各自延伸之條紋狀之 凹部或凸部即蝕刻痕。 A semiconductor wafer comprising a wafer body having a surface region including a semiconductor element, wherein an end surface of the wafer body has a stripe shape extending from a surface of the wafer body on a side of the surface region toward an opposite side The recess or the projection is an etch mark. 如請求項8之半導體晶片，其中上述凹部或凸部之各者具有10至100nm之寬度。 The semiconductor wafer of claim 8, wherein each of said recesses or protrusions has a width of 10 to 100 nm. 如請求項9之半導體晶片，其進而包括覆蓋上述表面區域之保護膜，且上述晶片本體之上述表面區域側之面之輪廓與上述保護膜之向包含上述表面區域側之面之平面的正投影之輪廓至少部分一致。 The semiconductor wafer of claim 9, further comprising a protective film covering the surface region, and an orthographic projection of a contour of a surface of the wafer body on a surface of the surface region side and a plane of the protective film facing a surface including the surface region side The outlines are at least partially identical. 如請求項10之半導體晶片，其中上述晶片本體之上述表面區域側之面不具有由一端彼此相接之2條線段界定之角部。 A semiconductor wafer according to claim 10, wherein said surface of said wafer body on said surface region side does not have a corner portion defined by two line segments whose ends are in contact with each other. 一種半導體晶片，其包括：晶片本體，其具有包含半導體元件之表面區域；及保護膜，其覆蓋上述表面區域；且上述晶片本體係藉由在半導體基板上形成包含上述保護膜之蝕刻掩膜，並將該半導體基板供於使用貴金屬觸媒與蝕刻液或蝕刻氣體之化學性蝕刻處理中而單片化所得者，且上述晶片本體之上述表面區域側之面之輪廓與上述保護膜之向包含該上表面之平面的正投影之輪廓至少部分一致。 A semiconductor wafer comprising: a wafer body having a surface region including a semiconductor element; and a protective film covering the surface region; and the wafer system forming an etching mask including the protective film on the semiconductor substrate, And singulating the semiconductor substrate in a chemical etching process using a noble metal catalyst, an etching solution, or an etching gas, and the outline of the surface of the wafer body on the surface region side and the direction of the protective film are included The contours of the orthographic projections of the plane of the upper surface are at least partially identical. 一種半導體晶片，其包括晶片本體，該晶片本體具有包含半導體元件之表面區域，且上述晶片本體係藉由在半導體基板上形成包含保護膜之蝕刻掩膜，並將該半導體基板供於使用貴金屬觸媒與蝕刻液或蝕刻氣體之化學性蝕刻處理中而單片化所得者，且上述晶片本體之上述表面區域側之面不具有由一端彼此相接之2條線段界定之角部。 A semiconductor wafer comprising a wafer body having a surface region including a semiconductor element, and the wafer system is formed by forming an etching mask including a protective film on the semiconductor substrate, and supplying the semiconductor substrate to a noble metal contact In the chemical etching treatment of the etching liquid or the etching gas, the wafer is singulated, and the surface of the wafer main body on the surface side side does not have a corner portion defined by two line segments whose ends are in contact with each other. 一種半導體裝置，其包括：支持構件；如請求項8之半導體晶片，其位於上述支持構件上；及模塑樹脂，其以覆蓋上述半導體晶片之方式設置於上述支持 構件上。 A semiconductor device comprising: a support member; the semiconductor wafer of claim 8 located on the support member; and a molding resin disposed on the support in a manner of covering the semiconductor wafer On the component. 一種半導體裝置，其包括：支持構件；如請求項8之半導體晶片，其位於上述支持構件上；及接合構件，其介於上述支持構件與上述半導體晶片之間。 A semiconductor device comprising: a support member; the semiconductor wafer of claim 8 located on the support member; and a bonding member interposed between the support member and the semiconductor wafer.
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