JP6761592B2 - Electronic devices and their manufacturing methods - Google Patents

Electronic devices and their manufacturing methods Download PDF

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JP6761592B2
JP6761592B2 JP2016072682A JP2016072682A JP6761592B2 JP 6761592 B2 JP6761592 B2 JP 6761592B2 JP 2016072682 A JP2016072682 A JP 2016072682A JP 2016072682 A JP2016072682 A JP 2016072682A JP 6761592 B2 JP6761592 B2 JP 6761592B2
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substrate
electronic device
recess
wiring layer
conductive
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JP2017183649A (en
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野 貴 正 高
野 貴 正 高
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Dai Nippon Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Description

本開示の実施形態は、電子デバイス及びその製造方法に関する。 Embodiments of the present disclosure relate to electronic devices and methods of manufacturing them.

半導体チップなどの素子をパッケージングする技術として、ウェハレベルパッケージング（WLP:Wafer-Level-Packaging）が知られている。ウェハレベルパッケージングとは、素子をパッケージングする工程をウェハの状態で実施する技術である。例えば特許文献１は、ファンアウト型ウェハレベルパッケージング（FOWLP:Fan Out Wafer-Level-Packaging）を改善するための技術を開示している。ファンアウト型ウェハレベルパッケージングとは、ウェハの状態で素子をパッケージングする工程において、素子の領域を超える領域にわたって再配線層を形成する技術である。なお、本明細書においては、再配線層のことを単に配線層とも称する。 Wafer-level-packaging (WLP) is known as a technique for packaging elements such as semiconductor chips. Wafer level packaging is a technique for carrying out the process of packaging elements in the state of a wafer. For example, Patent Document 1 discloses a technique for improving fan-out wafer level packaging (FOWLP: Fan Out Wafer-Level-Packaging). Fan-out wafer level packaging is a technique for forming a rewiring layer over a region beyond the region of the device in the process of packaging the device in the wafer state. In addition, in this specification, a rewiring layer is also simply referred to as a wiring layer.

従来のファンアウト型ウェハレベルパッケージングにおいては、まず、複数の半導体チップを準備し、次に、複数の半導体チップをキャリア上に載置する。その後、キャリア上に樹脂材料を供給して、各半導体チップを樹脂で封止する。続いて、樹脂で封止された複数の半導体チップを含む樹脂封止部材をキャリアから取り外す。次に、樹脂封止部材を裏返して、樹脂封止部材の上に配線層を形成する。その後、樹脂封止部材及び配線層を、１つの半導体チップを含む区画ごとに切断して、半導体チップがパッケージングされた電子デバイスを得る。 In the conventional fan-out type wafer level packaging, first, a plurality of semiconductor chips are prepared, and then a plurality of semiconductor chips are placed on a carrier. After that, a resin material is supplied onto the carrier, and each semiconductor chip is sealed with the resin. Subsequently, the resin sealing member containing the plurality of semiconductor chips sealed with the resin is removed from the carrier. Next, the resin sealing member is turned over to form a wiring layer on the resin sealing member. Then, the resin sealing member and the wiring layer are cut for each section including one semiconductor chip to obtain an electronic device in which the semiconductor chip is packaged.

特開２０１３−５８５２０号公報Japanese Unexamined Patent Publication No. 2013-55820

従来のファンアウト型ウェハレベルパッケージングにおいては、樹脂で封止された複数の半導体チップなどの素子を含む樹脂封止部材の上に、配線層形成工程などの工程を行う。この場合、工程の条件や精度が、素子を封止する樹脂の特性に起因する制約を受けることになる。 In the conventional fan-out type wafer level packaging, a process such as a wiring layer forming step is performed on a resin sealing member including elements such as a plurality of semiconductor chips sealed with a resin. In this case, the process conditions and accuracy are restricted by the characteristics of the resin that seals the device.

本開示の実施形態は、このような点を考慮してなされたものであり、電子デバイスを製造する際の工程における制約を低減することができる電子デバイス製造方法を提供することを目的とする。 The embodiment of the present disclosure has been made in consideration of such a point, and an object of the present invention is to provide an electronic device manufacturing method capable of reducing restrictions in a process for manufacturing an electronic device.

本開示の一実施形態は、第１面及び前記第１面の反対側に位置する第２面を含むとともに無機層を有する基板を準備する準備工程と、前記第１面側から前記基板に素子を固定する固定工程と、前記素子に電気的に接続された導電部を含む配線層を形成する配線層形成工程と、を備え、前記配線層形成工程は、前記基板の法線方向に沿って前記導電部を見た場合に前記導電部が前記素子と重なる領域から、前記重なる領域の外側へ延びるよう、前記導電部を形成する、電子デバイス製造方法である。 One embodiment of the present disclosure includes a preparatory step of preparing a substrate including a first surface and a second surface located on the opposite side of the first surface and having an inorganic layer, and an element on the substrate from the first surface side. A wiring layer forming step of forming a wiring layer including a conductive portion electrically connected to the element is provided, and the wiring layer forming step is performed along the normal direction of the substrate. This is an electronic device manufacturing method in which the conductive portion is formed so as to extend from a region where the conductive portion overlaps with the element to the outside of the overlapping region when the conductive portion is viewed.

本開示の一実施形態による電子デバイス製造方法において、前記準備工程は、凹部が形成された前記基板を準備し、前記固定工程は、前記素子を前記凹部に固定してもよい。 In the electronic device manufacturing method according to the embodiment of the present disclosure, the preparation step may prepare the substrate on which the recess is formed, and the fixing step may fix the element to the recess.

本開示の一実施形態による電子デバイス製造方法において、前記準備工程は、前記第１面に平行な方向における寸法が前記第１面から前記第２面に向かうにつれて減少する前記凹部が形成された前記基板を準備してもよい。 In the method of manufacturing an electronic device according to an embodiment of the present disclosure, in the preparatory step, the recess is formed in which the dimension in the direction parallel to the first surface decreases from the first surface toward the second surface. A substrate may be prepared.

本開示の一実施形態による電子デバイス製造方法において、前記準備工程は、その側面に段部が設けられた前記凹部が形成された前記基板を準備してもよい。 In the method of manufacturing an electronic device according to an embodiment of the present disclosure, in the preparation step, the substrate having the recess provided with a step portion on the side surface thereof may be prepared.

本開示の一実施形態による電子デバイス製造方法において、前記準備工程は、その側面に突起が設けられた前記凹部が形成された前記基板を準備してもよい。 In the method for manufacturing an electronic device according to an embodiment of the present disclosure, in the preparation step, the substrate having the recesses provided on the side surfaces thereof may be prepared.

前記固定工程は、シリコーン系樹脂、ビスマレイミド系樹脂、アクリル系樹脂、エポキシ系樹脂、ポリイミド系樹脂、ウレタン系樹脂、ゴム系樹脂、導電性樹脂、又は複数の導電性粒子を含む接着剤を用いて、前記基板に前記素子を固定してもよい。 In the fixing step, a silicone-based resin, a bismaleimide-based resin, an acrylic resin, an epoxy-based resin, a polyimide-based resin, a urethane-based resin, a rubber-based resin, a conductive resin, or an adhesive containing a plurality of conductive particles is used. The element may be fixed to the substrate.

本開示の一実施形態による電子デバイス製造方法は、前記電子デバイス製造方法は、前記素子を前記凹部に固定した後、前記基板を前記第２面側から削る切削工程を更に備えていてもよい。 The electronic device manufacturing method according to the embodiment of the present disclosure may further include a cutting step of fixing the element in the recess and then cutting the substrate from the second surface side.

本開示の一実施形態は、第１面及び前記第１面の反対側に位置する第２面を含むとともに無機層を有する基板と、前記基板に固定された素子と、前記素子に電気的に接続された導電部を含む配線層と、を備え、前記配線層の前記導電部は、前記基板の法線方向に沿って前記導電部を見た場合に前記素子と重なる領域から、前記重なる領域の外側へ延びている、電子デバイスである。 In one embodiment of the present disclosure, a substrate including a first surface and a second surface located on the opposite side of the first surface and having an inorganic layer, an element fixed to the substrate, and electrically to the element. A wiring layer including a connected conductive portion is provided, and the conductive portion of the wiring layer has a region that overlaps with the element when the conductive portion is viewed along the normal direction of the substrate. It is an electronic device that extends to the outside of.

本開示の一実施形態による電子デバイスにおいて、前記基板は、前記素子を収容する凹部又は貫通孔を有していてもよい。 In the electronic device according to one embodiment of the present disclosure, the substrate may have recesses or through holes for accommodating the element.

本開示の一実施形態による電子デバイスにおいて、前記基板の前記凹部又は貫通孔の、前記第１面に平行な方向における寸法は、前記第１面から前記第２面に向かうにつれて減少してもよい。 In an electronic device according to an embodiment of the present disclosure, the dimensions of the recesses or through holes of the substrate in a direction parallel to the first surface may decrease from the first surface to the second surface. ..

本開示の一実施形態による電子デバイスにおいて、前記基板の前記凹部又は貫通孔の側面に段部が設けられていてもよい。 In the electronic device according to the embodiment of the present disclosure, a step portion may be provided on the side surface of the recess or the through hole of the substrate.

本開示の一実施形態による電子デバイスにおいて、前記基板の前記凹部又は貫通孔の側面に突起が設けられていてもよい。 In the electronic device according to the embodiment of the present disclosure, a protrusion may be provided on the side surface of the recess or the through hole of the substrate.

本開示の一実施形態による電子デバイスにおいて、前記基板は、前記第２面側に形成されたフィン構造部を有していてもよい。 In the electronic device according to the embodiment of the present disclosure, the substrate may have a fin structure formed on the second surface side.

本開示の一実施形態による電子デバイスにおいて、前記基板は、前記第１面と前記第２面との間に形成された流路を有していてもよい。 In the electronic device according to the embodiment of the present disclosure, the substrate may have a flow path formed between the first surface and the second surface.

本開示の一実施形態による電子デバイスにおいて、前記基板は、前記第２面を構成する伝熱層を有していてもよい。 In the electronic device according to the embodiment of the present disclosure, the substrate may have a heat transfer layer constituting the second surface.

本開示の一実施形態による電子デバイスにおいて、前記基板は、前記配線層の前記導電部に電気的に接続され、前記基板を前記第１面側から前記第２面側へ貫通する貫通電極部を有していてもよい。 In the electronic device according to the embodiment of the present disclosure, the substrate is electrically connected to the conductive portion of the wiring layer, and has a through electrode portion that penetrates the substrate from the first surface side to the second surface side. You may have.

本開示の一実施形態による電子デバイスにおいて、前記素子の側面に段部が設けられていてもよい。 In the electronic device according to the embodiment of the present disclosure, a step portion may be provided on the side surface of the element.

本開示の一実施形態による電子デバイスにおいて、前記素子の側面に突起が設けられていてもよい。 In the electronic device according to the embodiment of the present disclosure, protrusions may be provided on the side surface of the element.

本開示の一実施形態による電子デバイスは、前記基板と前記素子との間に設けられ、シリコーン系樹脂、ビスマレイミド系樹脂、アクリル系樹脂、エポキシ系樹脂、ポリイミド系樹脂、ウレタン系樹脂、ゴム系樹脂、導電性樹脂、又は複数の導電性粒子を含む接着剤を更に備えていてもよい。 The electronic device according to the embodiment of the present disclosure is provided between the substrate and the element, and is a silicone resin, a bismaleimide resin, an acrylic resin, an epoxy resin, a polyimide resin, a urethane resin, or a rubber resin. It may further include a resin, a conductive resin, or an adhesive containing a plurality of conductive particles.

本開示の実施形態によれば、電子デバイス製造方法の工程における制約を低減することができる。 According to the embodiment of the present disclosure, it is possible to reduce the restrictions in the process of the electronic device manufacturing method.

本開示の一実施形態に係る電子デバイスを示す断面図である。It is sectional drawing which shows the electronic device which concerns on one Embodiment of this disclosure. 本開示の一実施形態に係る電子デバイスを示す平面図である。It is a top view which shows the electronic device which concerns on one Embodiment of this disclosure. 図１Ａの電子デバイスの基板及び素子を拡大して示す断面図である。FIG. 5 is an enlarged cross-sectional view showing a substrate and an element of the electronic device of FIG. 1A. 素子を構成する素子基板を準備する工程を示す図である。It is a figure which shows the process of preparing the element substrate which comprises an element. 素子基板に機能層を形成する工程を示す図である。It is a figure which shows the process of forming a functional layer on a device substrate. 機能層が形成された素子基板を切断して複数の素子を得る工程を示す図である。It is a figure which shows the process of cutting the element substrate on which a functional layer was formed, and obtaining a plurality of elements. 無機層を有する基板を準備する工程を示す図である。It is a figure which shows the process of preparing the substrate which has an inorganic layer. 基板に凹部を形成する工程を示す図である。It is a figure which shows the process of forming a recess in a substrate. 素子を基板の凹部に固定する工程を示す図である。It is a figure which shows the process of fixing an element in a recess of a substrate. 基板の第１面側に配線層を形成する工程を示す図である。It is a figure which shows the process of forming a wiring layer on the 1st surface side of a substrate. 基板の第２面側を切削する形成する工程を示す図である。It is a figure which shows the process of forming by cutting the 2nd surface side of a substrate. 基板を切断して電子デバイスを得る工程を示す図である。It is a figure which shows the process of cutting a substrate and obtaining an electronic device. 基板の凹部の一変形例を示す図である。It is a figure which shows one modification of the concave part of a substrate. 基板の凹部の一変形例を示す図である。It is a figure which shows one modification of the concave part of a substrate. 基板の凹部の一変形例を示す図である。It is a figure which shows one modification of the concave part of a substrate. 基板の凹部の一変形例を示す図である。It is a figure which shows one modification of the concave part of a substrate. 基板の凹部の一変形例を示す図である。It is a figure which shows one modification of the concave part of a substrate. 図９Ａに示す基板の平面図である。It is a top view of the substrate shown in FIG. 9A. 基板の一変形例を示す図である。It is a figure which shows one modification of the substrate. 基板の一変形例を示す図である。It is a figure which shows one modification of the substrate. 基板の一変形例を示す図である。It is a figure which shows one modification of the substrate. 基板の一変形例を示す図である。It is a figure which shows one modification of the substrate. 基板の一変形例を示す図である。It is a figure which shows one modification of the substrate. 電子デバイスの一変形例を示す図である。It is a figure which shows one modification of an electronic device. 素子の一変形例を示す図である。It is a figure which shows one modification of the element. 図１６に示す素子を製造する方法の一例を示す図である。It is a figure which shows an example of the method of manufacturing the element shown in FIG. 素子の一変形例を示す図である。It is a figure which shows one modification of the element. 本開示の実施形態に係る電子デバイスが搭載される製品の例を示す図である。It is a figure which shows the example of the product which mounts the electronic device which concerns on embodiment of this disclosure.

以下、本開示の実施形態に係る電子デバイスの構成及びその製造方法について、図面を参照しながら詳細に説明する。なお、以下に示す実施形態は本開示の実施形態の一例であって、本開示はこれらの実施形態に限定して解釈されるものではない。また、本明細書において、「基板」、「基材」、「シート」や「フィルム」など用語は、呼称の違いのみに基づいて、互いから区別されるものではない。例えば、「基板」や「基材」は、シートやフィルムと呼ばれ得るような部材も含む概念である。更に、本明細書において用いる、形状や幾何学的条件並びにそれらの程度を特定する、例えば、「平行」や「直交」等の用語や長さや角度の値等については、厳密な意味に縛られることなく、同様の機能を期待し得る程度の範囲を含めて解釈することとする。また、本実施形態で参照する図面において、同一部分または同様な機能を有する部分には同一の符号または類似の符号を付し、その繰り返しの説明は省略する場合がある。また、図面の寸法比率は説明の都合上実際の比率とは異なる場合や、構成の一部が図面から省略される場合がある。 Hereinafter, the configuration of the electronic device and the manufacturing method thereof according to the embodiment of the present disclosure will be described in detail with reference to the drawings. The embodiments shown below are examples of the embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in the present specification, terms such as "board", "base material", "sheet" and "film" are not distinguished from each other based only on the difference in names. For example, "base material" and "base material" are concepts including members that can be called sheets or films. Furthermore, as used herein, terms such as "parallel" and "orthogonal" and values of length and angle that specify the shape and geometric conditions and their degrees are bound by strict meaning. Instead, the interpretation will include the range in which similar functions can be expected. Further, in the drawings referred to in the present embodiment, the same parts or parts having similar functions are designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. In addition, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

以下、図１Ａ乃至図４Ｆを参照して、本開示の一実施形態について説明する。本実施の形態においては、チップファースト型のファンアウト型ウェハレベルパッケージングによって、パッケージングされた素子を含む電子デバイスを製造する。 Hereinafter, an embodiment of the present disclosure will be described with reference to FIGS. 1A to 4F. In the present embodiment, an electronic device including a packaged element is manufactured by chip-first type fan-out type wafer level packaging.

電子デバイス
まず、図１Ａ及び図１Ｂを参照して、本実施の形態に係る電子デバイス１０について説明する。図１Ａは、電子デバイス１０を示す断面図であり、図１Ｂは、電子デバイス１０を示す平面図である。 Electronic Device First, the electronic device 10 according to the present embodiment will be described with reference to FIGS. 1A and 1B. FIG. 1A is a cross-sectional view showing the electronic device 10, and FIG. 1B is a plan view showing the electronic device 10.

電子デバイス１０は、基板２０、基板２０に固定された素子４０、素子４０を基板２０に固定する固定部３５、及び、素子４０に接続された配線層５０を備える。以下、電子デバイス１０の各構成要素について説明する。 The electronic device 10 includes a substrate 20, an element 40 fixed to the substrate 20, a fixing portion 35 fixing the element 40 to the substrate 20, and a wiring layer 50 connected to the element 40. Hereinafter, each component of the electronic device 10 will be described.

（素子）
素子４０は、半導体チップなどの能動素子であってもよく、抵抗器やインダクタなどの受動素子であってもよい。素子４０は、配線層５０に接続される端子部を有する。本実施の形態においては、素子４０が、図１Ｂに示すように、平面視において矩形状の輪郭を有する半導体チップである例について説明する。 (element)
The element 40 may be an active element such as a semiconductor chip, or may be a passive element such as a resistor or an inductor. The element 40 has a terminal portion connected to the wiring layer 50. In the present embodiment, as shown in FIG. 1B, an example in which the element 40 is a semiconductor chip having a rectangular contour in a plan view will be described.

（基板）
基板２０は、素子４０が搭載される第１面２１、及び第１面２１の反対側に位置する第２面２２を含む。また、基板２０は、第１面２１に形成された凹部２４Ａを有する。素子４０は凹部２４Ａに収容されている。なお、基板２０に搭載される素子４０の数や、１つの凹部２４Ａに収容される素子４０の数が特に限られることはない。複数の素子４０が、基板２０に搭載され、又は１つの凹部２４Ａに収容され得る。 (substrate)
The substrate 20 includes a first surface 21 on which the element 40 is mounted and a second surface 22 located on the opposite side of the first surface 21. Further, the substrate 20 has a recess 24A formed on the first surface 21. The element 40 is housed in the recess 24A. The number of elements 40 mounted on the substrate 20 and the number of elements 40 accommodated in one recess 24A are not particularly limited. A plurality of elements 40 may be mounted on the substrate 20 or housed in one recess 24A.

図２は、基板２０及び素子４０を拡大して示す断面図である。凹部２４Ａは、底面２５及び側面２６を含む。凹部２４Ａの深さＤは、例えば３０μｍ以上且つ３００μｍ以下である。また、素子４０は、基板２０の第１面２１側に位置する第１面４１、及び、第１面４１の反対側に位置する第２面４２を含む。なお、図２は、基板２０の第１面２１の位置と素子４０の第１面４１の位置とが一致する例を示しているが、第１面２１の位置と第１面４１の位置との関係が特に限られることはない。 FIG. 2 is an enlarged cross-sectional view of the substrate 20 and the element 40. The recess 24A includes a bottom surface 25 and a side surface 26. The depth D of the recess 24A is, for example, 30 μm or more and 300 μm or less. Further, the element 40 includes a first surface 41 located on the first surface 21 side of the substrate 20 and a second surface 42 located on the opposite side of the first surface 41. Note that FIG. 2 shows an example in which the position of the first surface 21 of the substrate 20 and the position of the first surface 41 of the element 40 match, but the position of the first surface 21 and the position of the first surface 41 The relationship is not particularly limited.

基板２０は、無機層２３を有する。基板２０が無機層２３を有することにより、基板２０の熱膨張率を低くすることができ、これによって、電子デバイス１０の製造工程において基板２０に反りや膨張などの変形が生じることを抑制することができる。また、基板２０に高い耐熱性を持たせることができ、これによって、電子デバイス１０の製造工程において電子デバイス１０の各層を高温で処理することが可能になる。基板２０の厚みＴは、例えば２５０μｍ以上且つ２０００μｍ以下である。 The substrate 20 has an inorganic layer 23. Since the substrate 20 has the inorganic layer 23, the coefficient of thermal expansion of the substrate 20 can be lowered, thereby suppressing deformation such as warpage and expansion of the substrate 20 in the manufacturing process of the electronic device 10. Can be done. Further, the substrate 20 can be provided with high heat resistance, which makes it possible to process each layer of the electronic device 10 at a high temperature in the manufacturing process of the electronic device 10. The thickness T of the substrate 20 is, for example, 250 μm or more and 2000 μm or less.

無機層２３を構成する無機材料としては、珪素、炭化珪素（ＳｉＣ）などの珪素の化合物、窒化ガリウム（ＧａＮ）などの金属窒化物、アルミナ（Ａｌ２Ｏ３）、ジルコニア（ＺｒＯ２）、ＡｌＮ、ＢＮなどのセラミックス、タングステン、モリブデン、銅、ステンレスなどの金属、若しくは、石英ガラスなどのガラスを用いることができる。また、サファイヤ、酸化物単結晶、フッ化物単結晶などの単結晶材料を用いてもよい。酸化物単結晶の例としては、ＳｒＴｉＯ３、ＬａＡｌＯ３、ＭｇＯ、ＴｉＯ２、Ａｌ２Ｏ３、ＳｉＯ２、ＬｉＮｂＯ３、ＬｉＴａＯ３などを挙げることができる。また、フッ化物単結晶の例としては、ＭｇＦ２、ＣａＦ２、ＢａＦ２、ＬｉＦなどを挙げることができる。 Examples of the inorganic material constituting the inorganic layer 23 include silicon, a compound of silicon such as silicon carbide (SiC), a metal nitride such as gallium nitride (GaN), alumina (Al 2 O 3 ), zirconia (ZrO 2 ), and AlN. , BN and other ceramics, tungsten, molybdenum, copper, stainless steel and other metals, or quartz glass and other glass can be used. Further, a single crystal material such as sapphire, an oxide single crystal, or a fluoride single crystal may be used. Examples of the oxide single crystal include SrTiO 3 , LaAlO 3 , MgO, TiO 2 , Al 2 O 3 , SiO 2 , LiNbO 3 , LiTaO 3, and the like. Further, examples of the fluoride single crystal include MgF 2 , CaF 2 , BaF 2 , LiF and the like.

平面視に基板２０の形状や、基板２０の供給形態は、特には限られない。例えば、基板２０は、平面視において円形状の輪郭を有する部材、いわゆるウェハであってもよい。また、基板２０は、矩形状の輪郭を有する部材、いわゆるパネルであってもよい。また、基板２０は、第１方向に延び、好ましくは可撓性を有するシート状の部材であってもよい。この場合、基板２０を第１方向に搬送しながら、電子デバイス１０を作製する工程を実施してもよい。 The shape of the substrate 20 and the supply form of the substrate 20 in a plan view are not particularly limited. For example, the substrate 20 may be a member having a circular contour in a plan view, a so-called wafer. Further, the substrate 20 may be a member having a rectangular contour, a so-called panel. Further, the substrate 20 may be a sheet-like member extending in the first direction and preferably having flexibility. In this case, the step of manufacturing the electronic device 10 may be carried out while transporting the substrate 20 in the first direction.

（固定部）
固定部３５は、素子４０を基板２０に固定するよう素子４０と基板２０との間に設けられている。固定部３５は、例えば、樹脂を含む接着剤３６である。接着剤３６は、図２に示すように、基板２０の凹部２４Ａの底面２５と素子４０の第２面４２との間、及び、凹部２４Ａの側面２６と素子４０の側面４３との間に設けられている。 (Fixed part)
The fixing portion 35 is provided between the element 40 and the substrate 20 so as to fix the element 40 to the substrate 20. The fixing portion 35 is, for example, an adhesive 36 containing a resin. As shown in FIG. 2, the adhesive 36 is provided between the bottom surface 25 of the recess 24A of the substrate 20 and the second surface 42 of the element 40, and between the side surface 26 of the recess 24A and the side surface 43 of the element 40. Has been done.

従来、素子のパッケージング方法においては、素子を樹脂で封止するという手段が採用されてきた。この場合、樹脂には、バリア性など、素子を外部環境から遮蔽するための特性が求められる。一方、本実施の形態においては、基板２０が無機層２３を含むので、無機層２３によって素子を外部環境から遮蔽することができる。従って、接着剤３６を構成する樹脂を、素子を外部環境から遮蔽するための特性以外の特性に着目して選定することができる。例えば、樹脂の接着性や耐熱性などに着目して、樹脂を選定することができる。このため、例えば接着性を重視して樹脂を選定した場合、従来に比べて、基板２０に対して素子４０をより強固に固定することができる。 Conventionally, in the device packaging method, a means of sealing the device with a resin has been adopted. In this case, the resin is required to have characteristics such as barrier properties for shielding the element from the external environment. On the other hand, in the present embodiment, since the substrate 20 includes the inorganic layer 23, the element can be shielded from the external environment by the inorganic layer 23. Therefore, the resin constituting the adhesive 36 can be selected by paying attention to the characteristics other than the characteristics for shielding the element from the external environment. For example, the resin can be selected by paying attention to the adhesiveness and heat resistance of the resin. Therefore, for example, when the resin is selected with an emphasis on adhesiveness, the element 40 can be more firmly fixed to the substrate 20 than in the conventional case.

接着剤３６を構成する樹脂としては、例えば、シリコーン系樹脂、ビスマレイミド系樹脂、アクリル系樹脂、エポキシ系樹脂、ポリイミド系樹脂、ウレタン系樹脂、ゴム系樹脂などを用いることができる。また、接着剤３６は、導電性を有していてもよい。接着剤３６に導電性を持たせるための手段としては、例えば、導電性樹脂を用いて接着剤３６を構成することや、接着剤３６を構成する樹脂の中に複数の導電性粒子を分散させることなどが採用され得る。導電性粒子は、例えば、金、銀、パラジウム、ニッケル、銅、銀でコートされた銅などを含む粒子である。導電性粒子の寸法は、例えば０．０１μｍ以上且つ５μｍ以下である。 As the resin constituting the adhesive 36, for example, a silicone resin, a bismaleimide resin, an acrylic resin, an epoxy resin, a polyimide resin, a urethane resin, a rubber resin, or the like can be used. Further, the adhesive 36 may have conductivity. As a means for making the adhesive 36 conductive, for example, the adhesive 36 is formed by using a conductive resin, or a plurality of conductive particles are dispersed in the resin constituting the adhesive 36. Things can be adopted. The conductive particles are particles containing, for example, gold, silver, palladium, nickel, copper, copper coated with silver, and the like. The dimensions of the conductive particles are, for example, 0.01 μm or more and 5 μm or less.

なお、素子４０を基板２０に固定する固定部３５が、接着剤３６に限られることはない。例えば、素子４０及び基板２０がいずれも珪素を含む場合、固定部３５が金の層を含んでいてもよい。この場合、素子４０と基板２０との間に金の層を含む固定部３５を設けた状態で基板２０及び素子４０を加熱して、珪素と金の共晶を形成することにより、素子４０を基板２０に固定することができる。なお、このような共晶を形成することができる限りにおいて、固定部３５に含まれる材料が金に限られることはない。 The fixing portion 35 for fixing the element 40 to the substrate 20 is not limited to the adhesive 36. For example, when the element 40 and the substrate 20 both contain silicon, the fixing portion 35 may include a gold layer. In this case, the element 40 is formed by heating the substrate 20 and the element 40 with a fixing portion 35 including a gold layer provided between the element 40 and the substrate 20 to form a eutectic of silicon and gold. It can be fixed to the substrate 20. As long as such a eutectic can be formed, the material contained in the fixing portion 35 is not limited to gold.

また、常温接合を利用して素子４０を基板２０に固定してもよい。常温接合とは、素子４０の表面を構成する材料と基板２０の表面を構成する材料との分子間結合を利用した接合である。この場合、固定部３５という用語は、素子４０を基板２０に固定するための部材ではなく、常温接合が生じている場所を意味する。常温接合を生じさせるための駆動力は、圧力や電流などである。 Further, the element 40 may be fixed to the substrate 20 by utilizing normal temperature bonding. The room temperature bonding is a bonding using an intermolecular bond between a material constituting the surface of the element 40 and a material constituting the surface of the substrate 20. In this case, the term fixing portion 35 does not mean a member for fixing the element 40 to the substrate 20, but a place where normal temperature bonding occurs. The driving force for causing normal temperature bonding is pressure, current, or the like.

（配線層）
配線層５０は、素子４０の端子に電気的に接続された導電部５５、及び絶縁層５４を含む。配線層５０の導電部５５は、図１Ａ及び図１Ｂに示すように、基板２０の第１面２１の法線方向に沿って導電部５５を見た場合に素子４０と重なる領域から、重なる領域の外側へ延びている。以下の説明において、配線層５０のうち、基板２０の第１面２１の法線方向に沿って導電部５５を見た場合に素子４０と重なる領域を第１領域Ｒ１と称し、素子４０と重なる領域の外側に位置する領域を第２領域Ｒ２と称することもある。 (Wiring layer)
The wiring layer 50 includes a conductive portion 55 electrically connected to the terminal of the element 40 and an insulating layer 54. As shown in FIGS. 1A and 1B, the conductive portion 55 of the wiring layer 50 has a region that overlaps with the element 40 when the conductive portion 55 is viewed along the normal direction of the first surface 21 of the substrate 20. Extends to the outside of. In the following description, the region of the wiring layer 50 that overlaps with the element 40 when the conductive portion 55 is viewed along the normal direction of the first surface 21 of the substrate 20 is referred to as a first region R1 and overlaps with the element 40. The region located outside the region may be referred to as a second region R2.

配線層５０は、多層構造を有していてもよい。例えば、配線層５０は、第１配線層５１と、第１配線層５１上に積層された第２配線層５２と、第２配線層５２上に積層された第３配線層５３と、を含む。配線層５１，５２，５３はいずれも、絶縁層５４及び導電部５５を含む。また、配線層５０は、第３配線層５３の導電部５５の一部を露出させその他を覆う被覆層５６を更に含んでいてもよい。また、配線層は、被覆層５６から露出している導電部５５上に設けられ、素子４０の端子に電気的に接続された接触端子５７を更に含んでいてもよい。接触端子５７は、電子デバイス１０をマザーボードなどの配線基板に搭載するときに、配線基板の電極に接触する。接触端子５７は、バンプとも称される。なお、配線層５０の層の数が特に限られることはない。 The wiring layer 50 may have a multi-layer structure. For example, the wiring layer 50 includes a first wiring layer 51, a second wiring layer 52 laminated on the first wiring layer 51, and a third wiring layer 53 laminated on the second wiring layer 52. .. The wiring layers 51, 52, and 53 all include an insulating layer 54 and a conductive portion 55. Further, the wiring layer 50 may further include a coating layer 56 that exposes a part of the conductive portion 55 of the third wiring layer 53 and covers the others. Further, the wiring layer may further include a contact terminal 57 provided on the conductive portion 55 exposed from the coating layer 56 and electrically connected to the terminal of the element 40. The contact terminal 57 comes into contact with the electrodes of the wiring board when the electronic device 10 is mounted on a wiring board such as a motherboard. The contact terminal 57 is also referred to as a bump. The number of layers of the wiring layer 50 is not particularly limited.

本実施の形態によれば、上述のとおり、配線層５０の導電部５５は、素子４０と重なる第１領域Ｒ１から、素子４０と重ならない第２領域Ｒ２まで延びている。このため、図１Ｂに示すように、接触端子５７を第２領域Ｒ２に設けることができる。このことにより、素子４０の端子と、電子デバイス１０が搭載されるマザーボードなどの配線基板の電極と、の間を容易に電気的に接続できるようになる。 According to the present embodiment, as described above, the conductive portion 55 of the wiring layer 50 extends from the first region R1 that overlaps with the element 40 to the second region R2 that does not overlap with the element 40. Therefore, as shown in FIG. 1B, the contact terminal 57 can be provided in the second region R2. This makes it possible to easily electrically connect the terminals of the element 40 and the electrodes of a wiring board such as a motherboard on which the electronic device 10 is mounted.

絶縁層５４を構成する絶縁性材料は、有機材料であってもよく、又は、無機材料であってもよい。また、絶縁層５４は、有機材料を含む層、及び、無機材料を含む層の両方を有していてもよい。 The insulating material constituting the insulating layer 54 may be an organic material or an inorganic material. Further, the insulating layer 54 may have both a layer containing an organic material and a layer containing an inorganic material.

絶縁層５４に含まれる有機材料の例としては、エポキシ樹脂、ポリイミド樹脂、ベンゾシクロブテン樹脂、ポリアミド、フェノール樹脂、シリコーン樹脂、フッ素樹脂、液晶ポリマー、ポリアミドイミド、ポリベンゾオキサゾール、シアネート樹脂、アラミド、ポリオレフィン、ポリエステル、BTレジン、FR-4、FR-5、ポリアセタール、ポリブチレンテレフタレート、シンジオタクチック・ポリスチレン、ポリフェニレンサルファイド、ポリエーテルエーテルケトン、ポリエーテルニトリル、ポリカーボネート、ポリフェニレンエーテルポリサルホン、ポリエーテルスルホン、ポリアリレート、ポリエーテルイミドなどを挙げることができる。上記の有機材料は、単体で用いてもよく、２種類以上の有機材料を組み合わせて用いてもよい。また、上記の有機材料と、ガラス、タルク、マイカ、シリカ、アルミナ、無機フィラー等とを組み合わせて用いてもよい。 Examples of the organic material contained in the insulating layer 54 include epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, and aramid. Polyolefin, polyester, BT resin, FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyether ether ketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, poly Examples thereof include allylate and polyetherimide. The above organic materials may be used alone or in combination of two or more kinds of organic materials. Further, the above organic material may be used in combination with glass, talc, mica, silica, alumina, an inorganic filler and the like.

絶縁層５４に含まれる無機材料の例としては、窒化シリコン（ＳｉＮ）、酸化シリコン（ＳｉＯ２）、酸化アルミニウム（ＡｌＯ３）、窒化アルミニウム（ＡｌＮ）、シリコンカーバイト（ＳｉＣ）、窒化シリコンカーバイト（ＳｉＣＮ）、炭素添加シリコンオキサイド（ＳｉＯＣ）などを挙げることができる。 Examples of the inorganic material contained in the insulating layer 54 include silicon nitride (SiN), silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), aluminum nitride (AlN), silicon carbide (SiC), and silicon carbide carbide. (SiCN), carbon-added silicon oxide (SiOC) and the like can be mentioned.

また、導電部５５を構成する導電性材料としては、銅、銀、金、錫、ニッケル、チタン、アルミニウム、タングステン、ベリリウム、ロジウム、イリジウム、ルテニウム、白金、パラジウム、クロム、タンタルタリウム、モリブデン、鉄などの金属またはそれらを含む合金を用いることができる。合金は、アルミとネオジウムの合金、アルミと珪素の合金、アルミと珪素と銅の合金、ニッケルと金の合金、ニッケルとパラジウムと金の合金、ベリリウムと銅の合金などである。 The conductive materials constituting the conductive portion 55 include copper, silver, gold, tin, nickel, titanium, aluminum, tungsten, beryllium, rhodium, iridium, ruthenium, platinum, palladium, chromium, tantalum, molybdenum, and iron. Metals such as or alloys containing them can be used. Alloys include alloys of aluminum and neodium, alloys of aluminum and silicon, alloys of aluminum and silicon and copper, alloys of nickel and gold, alloys of nickel and palladium and gold, and alloys of beryllium and copper.

電子デバイスの製造方法
以下、電子デバイス１０の製造方法の一例について説明する。 Manufacturing Method of Electronic Device Hereinafter, an example of a manufacturing method of the electronic device 10 will be described.

まず、素子４０の製造方法の一例について、図３Ａ乃至図３Ｃを参照して説明する。まず、図３Ａに示すように、素子４０を構成するための素子基板４６を準備する。素子基板４６は、例えば、平面視において円形状の輪郭を有する部材、いわゆるウェハである。この場合、素子基板４６は、珪素などの無機材料を含む。 First, an example of a method for manufacturing the element 40 will be described with reference to FIGS. 3A to 3C. First, as shown in FIG. 3A, an element substrate 46 for forming the element 40 is prepared. The element substrate 46 is, for example, a member having a circular contour in a plan view, a so-called wafer. In this case, the element substrate 46 contains an inorganic material such as silicon.

また、素子基板４６は、第１方向に延び、好ましくは可撓性を有するシート状の部材であってもよい。この場合、素子基板４６を第１方向に搬送しながら、素子４０を製造する工程を実施してもよい。なお、「可撓性」とは、室温例えば２５℃の環境下で素子基板４６を直径１０ｍｍの円筒状の部材に巻きつけた場合に、素子基板４６に折れ目が生じない程度の柔軟性を意味している。素子基板４６は、ガラスなどの無機材料を含んでいてもよく、ポリエチレンテレフタラートなどの有機材料を含んでいてもよい。 Further, the element substrate 46 may be a sheet-like member extending in the first direction and preferably having flexibility. In this case, the step of manufacturing the element 40 may be carried out while conveying the element substrate 46 in the first direction. In addition, "flexibility" means flexibility to the extent that the element substrate 46 does not crease when the element substrate 46 is wound around a cylindrical member having a diameter of 10 mm in an environment of room temperature, for example, 25 ° C. Means. The element substrate 46 may contain an inorganic material such as glass, or may contain an organic material such as polyethylene terephthalate.

続いて、図３Ｂに示すように、素子基板４６上に機能層４７を形成する。機能層４７は、例えば、珪素を含む素子基板４６に珪素とは異なる元素をドーピングすることによって形成されたトランジスタ、トランジスタの電極に接続された配線などを含む。 Subsequently, as shown in FIG. 3B, the functional layer 47 is formed on the element substrate 46. The functional layer 47 includes, for example, a transistor formed by doping an element substrate 46 containing silicon with an element different from silicon, wiring connected to the electrode of the transistor, and the like.

続いて、図３Ｃに示すように、機能層４７が形成された素子基板４６を切断する。このようにして、複数の素子４０を製造することができる。 Subsequently, as shown in FIG. 3C, the element substrate 46 on which the functional layer 47 is formed is cut. In this way, a plurality of elements 40 can be manufactured.

次に、素子４０をパッケージングして電子デバイス１０を作製する工程について、図４Ａ乃至図４Ｆを参照して説明する。まず、図４Ａに示すように、無機層２３を含む基板２０を準備する準備工程を実施する。 Next, a step of packaging the element 40 to manufacture the electronic device 10 will be described with reference to FIGS. 4A to 4F. First, as shown in FIG. 4A, a preparatory step for preparing the substrate 20 including the inorganic layer 23 is carried out.

続いて、図４Ｂに示すように、基板２０の第１面２１に複数の凹部２４Ａを形成する凹部形成工程を実施する。例えば、図示はしないが、まず、基板２０の第１面２１のうち凹部２４Ａが形成されない領域をレジスト層で覆う。例えば、まず、第１面２１にレジスト層を設け、次に、レジスト層のうち基板２０に凹部２４Ａが形成される領域に位置するレジスト層を、リソグラフィー法などによって除去する。 Subsequently, as shown in FIG. 4B, a recess forming step of forming a plurality of recesses 24A on the first surface 21 of the substrate 20 is performed. For example, although not shown, first, a region of the first surface 21 of the substrate 20 where the recess 24A is not formed is covered with a resist layer. For example, first, a resist layer is provided on the first surface 21, and then, among the resist layers, the resist layer located in the region where the recess 24A is formed in the substrate 20 is removed by a lithography method or the like.

続いて、基板２０の第１面２１のうちレジスト層で覆われていない領域を除去して、複数の凹部２４Ａを形成する。レジスト層で覆われていない領域を除去する方法としては、反応性イオンエッチング法、深掘り反応性イオンエッチング法などのドライエッチング法や、ウェットエッチング法などを用いることができる。複数の凹部２４Ａを形成した後、第１面２１上のレジスト層を除去する。 Subsequently, a region of the first surface 21 of the substrate 20 that is not covered with the resist layer is removed to form a plurality of recesses 24A. As a method for removing the region not covered by the resist layer, a dry etching method such as a reactive ion etching method or a deep digging reactive ion etching method, a wet etching method or the like can be used. After forming the plurality of recesses 24A, the resist layer on the first surface 21 is removed.

ウェットエッチング法のためのエッチング液としては、フッ化水素（ＨＦ）、硫酸（Ｈ２ＳＯ４）、硝酸（ＨＮＯ３）、塩酸（ＨＣｌ）のいずれか、又はこれらのうちの混合物を用いることができる。 As the etching solution for the wet etching method, any one of hydrogen fluoride (HF), sulfuric acid (H 2 SO 4 ), nitric acid (HNO 3 ), hydrochloric acid (HCl), or a mixture thereof can be used. it can.

ドライエッチング法としては、ＳＦ６ガスのプラズマなどを用いたドライエッチングＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）法、ボッシュプロセスを用いたＤＲＩＥ（Ｄｅｅｐ Ｒｅａｃｔｉｖｅ Ｉｏｎ ＥｔｃｈｉｎｇＲＩＥ）法、サンドブラスト法、レーザアブレーション等のレーザ加工等を用いることができる。 As the dry etching method, dry etching RIE (Reactive Ion Etching) method using SF 6 gas plasma or the like, DRIE (Deep Reactive Ion Etching RIE) method using the Bosch process, sandblasting method, laser processing such as laser ablation, etc. It can be used.

次に、図４Ｃに示すように、素子４０を基板２０の凹部２４Ａに固定する固定工程を実施する。例えば、まず、基板２０の凹部２４Ａに接着剤３６を供給して、凹部２４Ａの底面２５及び側面２６に接着剤３６を付着させる。続いて、素子４０を凹部２４Ａ内に配置する。これによって、素子４０の第２面４２及び側面４３を、接着剤３６を介して基板２０の凹部２４Ａに固定することができる。 Next, as shown in FIG. 4C, a fixing step of fixing the element 40 to the recess 24A of the substrate 20 is performed. For example, first, the adhesive 36 is supplied to the recess 24A of the substrate 20, and the adhesive 36 is adhered to the bottom surface 25 and the side surface 26 of the recess 24A. Subsequently, the element 40 is arranged in the recess 24A. As a result, the second surface 42 and the side surface 43 of the element 40 can be fixed to the recess 24A of the substrate 20 via the adhesive 36.

その後、図４Ｄに示すように、基板２０の第１面２１側において、素子４０に電気的に接続された導電部５５を含む配線層５０を形成する配線層形成工程を実施する。例えば、まず、基板２０の第１面２１側に絶縁層５４を形成する。次に、絶縁層５４のうち導電部５５が設けられる部分を除去して、絶縁層５４に貫通孔を形成する。その後、めっき法、サブトラクティブ法、セミアディティブ法、ダマシン法、ナノインプリント法などを用いて、絶縁層５４のうち貫通孔が形成されている部分に導電部５５を設ける。このようにして、図１Ａの第１配線層５１を形成することができる。その後、同様の工程を繰り返すことにより、第２配線層５２及び第３配線層５３を形成することができる。 Then, as shown in FIG. 4D, a wiring layer forming step of forming the wiring layer 50 including the conductive portion 55 electrically connected to the element 40 is performed on the first surface 21 side of the substrate 20. For example, first, the insulating layer 54 is formed on the first surface 21 side of the substrate 20. Next, the portion of the insulating layer 54 where the conductive portion 55 is provided is removed to form a through hole in the insulating layer 54. After that, the conductive portion 55 is provided in the portion of the insulating layer 54 where the through hole is formed by using a plating method, a subtractive method, a semi-additive method, a damascene method, a nanoimprint method, or the like. In this way, the first wiring layer 51 of FIG. 1A can be formed. After that, the second wiring layer 52 and the third wiring layer 53 can be formed by repeating the same steps.

次に、図４Ｅに示すように、基板２０を第２面２２側から削る切削工程、いわゆるバックグラインド工程を実施する。切削工程を実施することにより、基板２０の厚みを低減して電子デバイス１０を小型化することができる。なお、切削工程は、上述の固定工程を実施した後であって、上述の配線層形成工程を実施する前に実施してもよい。 Next, as shown in FIG. 4E, a cutting step of cutting the substrate 20 from the second surface 22 side, a so-called back grind step, is performed. By carrying out the cutting process, the thickness of the substrate 20 can be reduced and the electronic device 10 can be miniaturized. The cutting step may be carried out after the above-mentioned fixing step is carried out and before the above-mentioned wiring layer forming step is carried out.

続いて、図４Ｆに示すように、素子４０が搭載され配線層５０が形成された基板２０を、１つの素子４０を含む区画ごとに切断する。これによって、無機層２３を含む基板２０と、基板２０に固定された素子４０と、素子４０の外側にまで広がる配線層５０と、を備える複数の電子デバイス１０を得ることができる。 Subsequently, as shown in FIG. 4F, the substrate 20 on which the element 40 is mounted and the wiring layer 50 is formed is cut into sections including one element 40. As a result, it is possible to obtain a plurality of electronic devices 10 including the substrate 20 including the inorganic layer 23, the element 40 fixed to the substrate 20, and the wiring layer 50 extending to the outside of the element 40.

（本実施の形態の効果）
本実施の形態によれば、基板２０が無機層２３を含むので、無機層２３によって素子を外部環境から遮蔽することができる。このため、素子４０を樹脂で封止する場合に比べて、接着剤３６を構成する樹脂の選定の自由度が高くなる。従って、例えば、高い接着性を有する樹脂を用いて接着剤３６を構成することができ、これによって、基板２０に対して素子４０をより強固に固定することができる。また、絶縁性を有する接着剤３６、及び導電性を有する接着剤３６のいずれをも選択することが可能になる。このため、例えば導電性を有する接着剤３６を選択することにより、接着剤３６を介して素子４０を接地電位に接続することが可能になり、これによって、電子デバイスのノイズ耐性を向上させることができる。 (Effect of this embodiment)
According to the present embodiment, since the substrate 20 includes the inorganic layer 23, the element can be shielded from the external environment by the inorganic layer 23. Therefore, the degree of freedom in selecting the resin constituting the adhesive 36 is higher than that in the case where the element 40 is sealed with the resin. Therefore, for example, the adhesive 36 can be formed by using a resin having high adhesiveness, whereby the element 40 can be more firmly fixed to the substrate 20. Further, it becomes possible to select either the adhesive 36 having an insulating property and the adhesive 36 having a conductive property. Therefore, for example, by selecting the adhesive 36 having conductivity, it becomes possible to connect the element 40 to the ground potential via the adhesive 36, thereby improving the noise immunity of the electronic device. it can.

また、本実施の形態によれば、基板２０が無機層２３を含むので、基板２０が有機材料のみからなる場合に比べて、基板２０の熱膨張率を低くすることができる。このため、基板２０上に配線層５０を形成する際に、温度変化に起因して基板２０の膨張や収縮が生じることを抑制することができる。このことにより、配線層５０のパターンが微細な場合であっても、基板２０に固定されている素子４０の端子と、配線層５０の導電部５５とを精度良く接続することができる。従って、より微細なパターンを有する配線層５０を形成することが可能になる。また、基板２０に反りなどの変形が生じにくいので、配線層形成工程を複数回繰り返すことができ、このため、多層の配線層５０を得ることができる。 Further, according to the present embodiment, since the substrate 20 includes the inorganic layer 23, the coefficient of thermal expansion of the substrate 20 can be lowered as compared with the case where the substrate 20 is made of only an organic material. Therefore, when the wiring layer 50 is formed on the substrate 20, it is possible to suppress the expansion and contraction of the substrate 20 due to the temperature change. As a result, even when the pattern of the wiring layer 50 is fine, the terminals of the element 40 fixed to the substrate 20 and the conductive portion 55 of the wiring layer 50 can be connected with high accuracy. Therefore, it becomes possible to form the wiring layer 50 having a finer pattern. Further, since the substrate 20 is less likely to be deformed such as warped, the wiring layer forming step can be repeated a plurality of times, and therefore a multilayer wiring layer 50 can be obtained.

また、本実施の形態によれば、素子４０の素子基板４６と同一の無機材料を、基板２０が無機層２３において用いることができる。このことにより、素子４０の素子基板４６の熱膨張率と、基板２０の熱膨張率との差を小さくすることができる。このため、基板２０に素子４０を固定した後の工程において、例えば基板２０上に配線層５０を形成する工程において、温度変化に起因して基板２０と素子４０との間の固定部３５に応力が生じることを抑制することができる。このことにより、固定部３５にクラックなどの損傷が生じたり、固定部３５が基板２０又は素子４０から剥がれたりしてしまうことを抑制することができる。従って、電子デバイス１０の製造工程における不良発生率を低減することができ、また、電子デバイス１０の信頼性を向上させることができる。 Further, according to the present embodiment, the substrate 20 can use the same inorganic material as the element substrate 46 of the element 40 in the inorganic layer 23. As a result, the difference between the coefficient of thermal expansion of the element substrate 46 of the element 40 and the coefficient of thermal expansion of the substrate 20 can be reduced. Therefore, in the process after fixing the element 40 to the substrate 20, for example, in the process of forming the wiring layer 50 on the substrate 20, stress is applied to the fixing portion 35 between the substrate 20 and the element 40 due to the temperature change. Can be suppressed from occurring. As a result, it is possible to prevent damage such as cracks from occurring in the fixing portion 35 and peeling of the fixing portion 35 from the substrate 20 or the element 40. Therefore, the defect occurrence rate in the manufacturing process of the electronic device 10 can be reduced, and the reliability of the electronic device 10 can be improved.

また、本実施の形態においては、基板２０に形成された凹部２４Ａに素子４０を配置する。このため、平面上に素子４０を配置する場合に比べて、基板２０の第１面２１に平行な方向において素子４０の位置ずれが生じることを抑制することができる。また、基板２０の凹部２４Ａ及び素子４０のいずれもが平面視において矩形状の輪郭を有する場合、素子４０を基板２０に配置する際に素子４０が平面視において回転することを抑制することができる。すなわち、回転方向において素子４０の位置ずれが生じることを抑制することもできる。
素子４０の位置ずれを抑制するためには、基板２０の第１面２１に平行な方向における基板２０の凹部２４Ａの寸法Ｓ１と素子４０の寸法Ｓ２との差が小さいことが好ましい。寸法Ｓ１と寸法Ｓ２との差は、例えば１μｍ以上且つ１０００μｍ以下である。 Further, in the present embodiment, the element 40 is arranged in the recess 24A formed in the substrate 20. Therefore, as compared with the case where the element 40 is arranged on a flat surface, it is possible to prevent the element 40 from being displaced in the direction parallel to the first surface 21 of the substrate 20. Further, when both the recess 24A of the substrate 20 and the element 40 have a rectangular contour in a plan view, it is possible to suppress the element 40 from rotating in a plan view when the element 40 is arranged on the substrate 20. .. That is, it is possible to prevent the element 40 from being displaced in the rotation direction.
In order to suppress the misalignment of the element 40, it is preferable that the difference between the dimension S1 of the recess 24A of the substrate 20 and the dimension S2 of the element 40 in the direction parallel to the first surface 21 of the substrate 20 is small. The difference between the dimension S1 and the dimension S2 is, for example, 1 μm or more and 1000 μm or less.

なお、上述した実施の形態に対して様々な変更を加えることが可能である。以下、必要に応じて図面を参照しながら、変形例について説明する。以下の説明および以下の説明で用いる図面では、上述した実施の形態と同様に構成され得る部分について、上述の実施の形態における対応する部分に対して用いた符号と同一の符号を用いることとし、重複する説明を省略する。また、上述した実施の形態において得られる作用効果が変形例においても得られることが明らかである場合、その説明を省略することもある。 It is possible to make various changes to the above-described embodiment. Hereinafter, a modified example will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, the same reference numerals as those used for the corresponding portions in the above-described embodiment will be used for the portions that can be configured in the same manner as in the above-described embodiment. Duplicate description is omitted. Further, when it is clear that the action and effect obtained in the above-described embodiment can be obtained in the modified example, the description thereof may be omitted.

（基板の凹部の第１変形例）
上述の本実施の形態においては、基板２０の凹部２４Ａの側面２６が基板２０の法線方向に平行である例を示したが、これに限られることはない。例えば、図５に示すように、凹部２４Ａの、基板２０の第１面２１に平行な方向における寸法Ｓ１は、第１面２１から第２面２２に向かうにつれて減少していてもよい。言い換えると、凹部２４Ａの側面２６は、順テーパ形状を有していてもよい。この場合、図６に示すように、凹部２４Ａの側面２６は、湾曲面を有していてもよい。 (First modification of the recess of the substrate)
In the above-described embodiment, an example is shown in which the side surface 26 of the recess 24A of the substrate 20 is parallel to the normal direction of the substrate 20, but the present invention is not limited to this. For example, as shown in FIG. 5, the dimension S1 of the recess 24A in the direction parallel to the first surface 21 of the substrate 20 may decrease from the first surface 21 to the second surface 22. In other words, the side surface 26 of the recess 24A may have a forward taper shape. In this case, as shown in FIG. 6, the side surface 26 of the recess 24A may have a curved surface.

凹部２４Ａの側面２６にテーパ形状を持たせることにより、側面２６が基板２０の法線方向に平行である場合に比べて、側面２６が接着剤３６に接触する面積を増加させることができる。これによって、基板２０に対して素子４０をより強固に固定することができる。 By providing the side surface 26 of the recess 24A with a tapered shape, the area where the side surface 26 contacts the adhesive 36 can be increased as compared with the case where the side surface 26 is parallel to the normal direction of the substrate 20. As a result, the element 40 can be more firmly fixed to the substrate 20.

また、凹部２４Ａの側面２６が順テーパ形状を有する場合、素子４０を凹部２４Ａに配置する際に、素子４０が凹部２４Ａの側面２６に沿って摺動して平面視における凹部２４Ａの中心に近づくことができる。このため、基板２０の第１面２１に平行な方向において素子４０の位置ずれが生じることを更に抑制することができる。 Further, when the side surface 26 of the recess 24A has a forward taper shape, when the element 40 is arranged in the recess 24A, the element 40 slides along the side surface 26 of the recess 24A and approaches the center of the recess 24A in a plan view. be able to. Therefore, it is possible to further suppress the displacement of the element 40 in the direction parallel to the first surface 21 of the substrate 20.

（基板の凹部の第２変形例）
図７又は図８に示すように、基板２０の凹部２４Ａの側面２６に段部２６１を形成してもよい。段部２６１とは、基板２０の第１面２１に平行な方向における凹部２４Ａの側面２６の位置を不連続に変化させる構造部である。段部２６１が設けられる場合、基板２０の第１面２１に平行な方向において、第１面２１側に位置する側面２６の位置と第２面２２側に位置する側面２６の位置とが異なるようになる。なお、段部２６１は、図７に示すように、第２面２２側に位置する側面２６が第１面２１側に位置する側面２６よりも平面視における凹部２４Ａの中心側に位置するように構成されたものであってもよい。若しくは、段部２６１は、図８に示すように、第１面２１側に位置する側面２６が第２面２２に位置する側面２６よりも平面視における凹部２４Ａの中心側に位置するように構成されたものであってもよい。 (Second modification of the recess of the substrate)
As shown in FIG. 7 or 8, a step portion 261 may be formed on the side surface 26 of the recess 24A of the substrate 20. The step portion 261 is a structural portion that discontinuously changes the position of the side surface 26 of the recess 24A in the direction parallel to the first surface 21 of the substrate 20. When the step portion 261 is provided, the position of the side surface 26 located on the first surface 21 side and the position of the side surface 26 located on the second surface 22 side are different in the direction parallel to the first surface 21 of the substrate 20. become. As shown in FIG. 7, the step portion 261 is such that the side surface 26 located on the second surface 22 side is located closer to the center side of the recess 24A in the plan view than the side surface 26 located on the first surface 21 side. It may be configured. Alternatively, as shown in FIG. 8, the step portion 261 is configured such that the side surface 26 located on the first surface 21 side is located closer to the center side of the recess 24A in the plan view than the side surface 26 located on the second surface 22. It may be the one that has been done.

凹部２４Ａの側面２６に段部２６１を設けることにより、側面２６が接着剤３６に接触する面積を増加させることができる。また、段部２６１に起因するアンカー効果により、接着剤３６が剥がれにくくなる。このため、基板２０に対して素子４０をより強固に固定することができる。 By providing the step portion 261 on the side surface 26 of the recess 24A, the area where the side surface 26 contacts the adhesive 36 can be increased. In addition, the adhesive 36 is less likely to come off due to the anchor effect caused by the step portion 261. Therefore, the element 40 can be more firmly fixed to the substrate 20.

（基板の凹部の第３変形例）
図９Ａ及び図９Ｂに示すように、基板２０の凹部２４Ａの側面２６に、平面視における凹部２４Ａの中心側に突出する突起２６２を形成してもよい。これによって、側面２６が接着剤３６に接触する面積を増加させることができる。また、段部２６１に起因するアンカー効果により、接着剤３６が剥がれにくくなる。このため、基板２０に対して素子４０をより強固に固定することができる。また、図９Ｂに示すように、基板２０の第１面２１に平行な方向において、基板２０に対する素子４０の位置をより精密に定めることができる。なお、突起２６２の少なくとも一部が、素子４０の側面４３に接触していてもよい。若しくは、突起２６２が素子４０の側面４３に接触していなくてもよい。また、突起２６２の形状が特に限られることはない。例えば、図９Ａ及び図９Ｂにおいては、突起２６２が半球形状を有する例を示したが、これに限られることはなく、突起２６２は、円錐形状や三角錐形状などの錐形状を有していてもよく、また、円錐台形状や三角錐台形などの錐台形状を有していてもよい。 (Third modification example of the recess of the substrate)
As shown in FIGS. 9A and 9B, a protrusion 262 protruding toward the center of the recess 24A in a plan view may be formed on the side surface 26 of the recess 24A of the substrate 20. As a result, the area where the side surface 26 contacts the adhesive 36 can be increased. In addition, the adhesive 36 is less likely to come off due to the anchor effect caused by the step portion 261. Therefore, the element 40 can be more firmly fixed to the substrate 20. Further, as shown in FIG. 9B, the position of the element 40 with respect to the substrate 20 can be determined more precisely in the direction parallel to the first surface 21 of the substrate 20. At least a part of the protrusion 262 may be in contact with the side surface 43 of the element 40. Alternatively, the protrusion 262 may not be in contact with the side surface 43 of the element 40. Further, the shape of the protrusion 262 is not particularly limited. For example, in FIGS. 9A and 9B, an example in which the protrusion 262 has a hemispherical shape is shown, but the present invention is not limited to this, and the protrusion 262 has a cone shape such as a conical shape or a triangular pyramid shape. It may also have a truncated cone shape such as a truncated cone shape or a triangular truncated cone shape.

（基板の第１変形例）
図１０に示すように、基板２０は、第２面２２側に形成されたフィン構造部２７を有してもよい。フィン構造部２７は、例えば、第２面２２側において第２面２２の法線方向に突出する複数の突起２７１を含む。フィン構造部２７を設けることにより、第２面２２側における基板２０の表面積を増加させることができる。このため、素子４０で発生した熱を第２面２２から周囲雰囲気へより効果的に放出することができる。 (First modification of the substrate)
As shown in FIG. 10, the substrate 20 may have a fin structure portion 27 formed on the second surface 22 side. The fin structure 27 includes, for example, a plurality of protrusions 271 projecting in the normal direction of the second surface 22 on the second surface 22 side. By providing the fin structure portion 27, the surface area of the substrate 20 on the second surface 22 side can be increased. Therefore, the heat generated by the element 40 can be more effectively released from the second surface 22 to the surrounding atmosphere.

（基板の第２変形例）
図１１に示すように、基板２０は、第１面２１と第２面２２との間に形成された流路２８を有していてもよい。流路２８に冷媒を循環させることにより、素子４０で発生した熱をより効果的に外部に放出することができる。 (Second modification of the substrate)
As shown in FIG. 11, the substrate 20 may have a flow path 28 formed between the first surface 21 and the second surface 22. By circulating the refrigerant through the flow path 28, the heat generated by the element 40 can be more effectively released to the outside.

（基板の第３変形例）
図１２に示すように、基板２０は、第２面２２を構成する伝熱層２９を有していてもよい。伝熱層２９は、無機層２３を構成する無機材料よりも高い熱伝導率を有する材料の層である。例えば、伝熱層２９はアルミニウム層である。伝熱層２９を設けることにより、素子４０で発生した熱を第２面２２から周囲雰囲気へより効果的に放出することができる。 (Third modification example of the substrate)
As shown in FIG. 12, the substrate 20 may have a heat transfer layer 29 constituting the second surface 22. The heat transfer layer 29 is a layer of a material having a higher thermal conductivity than the inorganic material constituting the inorganic layer 23. For example, the heat transfer layer 29 is an aluminum layer. By providing the heat transfer layer 29, the heat generated by the element 40 can be more effectively released from the second surface 22 to the surrounding atmosphere.

（基板の第４変形例）
図１３に示すように、基板２０は、配線層５０の導電部５５に電気的に接続され、基板２０を第１面２１側から第２面２２側へ貫通する貫通電極部３０を有していてもよい。貫通電極部３０を設けることにより、素子４０の端子に基板２０の第２面２２側から電気的に接続することが可能になる。 (Fourth modification of the substrate)
As shown in FIG. 13, the substrate 20 has a through electrode portion 30 that is electrically connected to the conductive portion 55 of the wiring layer 50 and penetrates the substrate 20 from the first surface 21 side to the second surface 22 side. You may. By providing the through electrode portion 30, it becomes possible to electrically connect the terminal of the element 40 from the second surface 22 side of the substrate 20.

（基板の第５変形例）
上述の本実施の形態においては、基板２０が凹部２４Ａを有し、凹部２４Ａに素子４０が収容される例を示した。本変形例においては、図１４に示すように、基板２０が貫通孔２４Ｂを有し、貫通孔２４Ｂに素子４０が収容される例について説明する。 (Fifth modification of the substrate)
In the above-described embodiment, an example is shown in which the substrate 20 has a recess 24A and the element 40 is housed in the recess 24A. In this modification, as shown in FIG. 14, an example in which the substrate 20 has a through hole 24B and the element 40 is housed in the through hole 24B will be described.

図１４に示すように、基板２０の貫通孔２４Ｂは側面２６を有する。素子４０は、貫通孔２４Ｂの側面２６と素子４０の側面４３との間に設けられた接着剤３６によって、基板２０に固定される。ここで、上述の本実施の形態において述べたように、基板２０が無機層２３を含むので、高い接着性を有する樹脂を用いて接着剤３６を構成することができる。このため、本変形例のように素子４０の第２面４２が基板２０に固定されていない場合であっても、素子４０を基板２０に強固に固定することができる。 As shown in FIG. 14, the through hole 24B of the substrate 20 has a side surface 26. The element 40 is fixed to the substrate 20 by an adhesive 36 provided between the side surface 26 of the through hole 24B and the side surface 43 of the element 40. Here, as described in the above-described embodiment, since the substrate 20 includes the inorganic layer 23, the adhesive 36 can be formed by using a resin having high adhesiveness. Therefore, even when the second surface 42 of the element 40 is not fixed to the substrate 20 as in this modification, the element 40 can be firmly fixed to the substrate 20.

本変形例による基板２０は、例えば、上述の切削工程を、基板２０の第１面２１側に形成された凹部２４Ａが第２面２２につながって凹部２４Ａが貫通孔２４Ｂとなるまで継続することにより、得られる。本変形例によれば、基板２０の厚みをより小さくすることにより、より小型の電子デバイス１０を得ることができる。 In the substrate 20 according to this modification, for example, the above-mentioned cutting process is continued until the recess 24A formed on the first surface 21 side of the substrate 20 is connected to the second surface 22 and the recess 24A becomes a through hole 24B. Obtained by According to this modification, a smaller electronic device 10 can be obtained by making the thickness of the substrate 20 smaller.

なお、凹部２４Ａの側面２６に関して挙げた上述の第１変形例乃至第３変形例はいずれも、貫通孔２４Ｂの側面２６にも適用され得る。 In addition, any of the above-mentioned first modification to third modification mentioned with respect to the side surface 26 of the recess 24A can be applied to the side surface 26 of the through hole 24B.

（電子デバイスの第１変形例）
上述の本実施の形態及び各変形例においては、基板２０が凹部２４Ａ又は貫通孔２４Ｂを有し、凹部２４Ａ又は貫通孔２４Ｂに素子４０が収容される例を示した。しかしながら、これに限られることはなく、図１５に示すように、基板２０の第１面２１上に素子４０が設けられていてもよい。この場合、素子４０は、基板２０の第１面２１と素子４０の第２面４２との間に設けられた接着剤３６によって、基板２０に固定される。 (First modification of electronic device)
In the above-described embodiment and each modification, an example is shown in which the substrate 20 has a recess 24A or a through hole 24B, and the element 40 is housed in the recess 24A or the through hole 24B. However, the present invention is not limited to this, and as shown in FIG. 15, the element 40 may be provided on the first surface 21 of the substrate 20. In this case, the element 40 is fixed to the substrate 20 by the adhesive 36 provided between the first surface 21 of the substrate 20 and the second surface 42 of the element 40.

本変形例においても、基板２０が無機層２３を含むので、高い接着性を有する樹脂を用いて接着剤３６を構成することができる。このため、素子４０を基板２０に強固に固定することができる。 In this modification as well, since the substrate 20 contains the inorganic layer 23, the adhesive 36 can be formed by using a resin having high adhesiveness. Therefore, the element 40 can be firmly fixed to the substrate 20.

（素子の第１変形例）
上述の本実施の形態においては、素子４０の側面４３が第１面４１の法線方向に平行である例を示したが、これに限られることはない。例えば、図１６に示すように、素子４０の側面４３に段部４３１を形成してもよい。段部４３１とは、第１面４１に平行な方向における素子４０の側面４３の位置を不連続に変化させる構造部である。段部４３１が設けられる場合、第１面４１に平行な方向において、第１面４１側に位置する側面４３の位置と第２面４２側に位置する側面４３の位置とが異なるようになる。なお、段部４３１は、図１６に示すように、第１面４１側に位置する側面４３が第２面４２側に位置する側面４３よりも平面視における素子４０の中心側に位置するように構成されたものであってもよい。若しくは、図示はしないが、段部４３１は、第２面４２側に位置する側面４３が第１面４１側に位置する側面４３よりも平面視における素子４０の中心側に位置するように構成されたものであってもよい。 (First modification of the element)
In the above-described embodiment, the side surface 43 of the element 40 is parallel to the normal direction of the first surface 41, but the present invention is not limited to this. For example, as shown in FIG. 16, a step portion 431 may be formed on the side surface 43 of the element 40. The step portion 431 is a structural portion that discontinuously changes the position of the side surface 43 of the element 40 in a direction parallel to the first surface 41. When the step portion 431 is provided, the position of the side surface 43 located on the first surface 41 side and the position of the side surface 43 located on the second surface 42 side are different in the direction parallel to the first surface 41. As shown in FIG. 16, the step portion 431 is such that the side surface 43 located on the first surface 41 side is located closer to the center of the element 40 in a plan view than the side surface 43 located on the second surface 42 side. It may be configured. Alternatively, although not shown, the step portion 431 is configured such that the side surface 43 located on the second surface 42 side is located closer to the center side of the element 40 in a plan view than the side surface 43 located on the first surface 41 side. It may be a new one.

素子４０の側面４３に段部４３１を設けることにより、側面４３が接着剤３６に接触する面積を増加させることができる。また、段部４３１に起因するアンカー効果により、接着剤３６が剥がれにくくなる。このため、基板２０に対して素子４０をより強固に固定することができる。 By providing the step portion 431 on the side surface 43 of the element 40, the area where the side surface 43 comes into contact with the adhesive 36 can be increased. In addition, the adhesive 36 is less likely to come off due to the anchor effect caused by the step portion 431. Therefore, the element 40 can be more firmly fixed to the substrate 20.

図１７は、素子４０の側面４３に段部４３１を設ける方法の一例を示す図である。図１７において、符号４８は、機能層４７が形成された素子基板４６を第１面４１側から切断する第１カッターであり、符号４９は、機能層４７が形成された素子基板４６を第２面４２側から切断する第２カッターである。図１７に示すように、第１カッター４８の幅Ｗ１と第２カッター４９の幅Ｗ２とを異ならせることにより、素子４０の側面４３に段部４３１を設けることができる。 FIG. 17 is a diagram showing an example of a method of providing a step portion 431 on the side surface 43 of the element 40. In FIG. 17, reference numeral 48 is a first cutter that cuts the element substrate 46 on which the functional layer 47 is formed from the first surface 41 side, and reference numeral 49 is a second cutter on the element substrate 46 on which the functional layer 47 is formed. It is a second cutter that cuts from the surface 42 side. As shown in FIG. 17, by making the width W1 of the first cutter 48 different from the width W2 of the second cutter 49, the step portion 431 can be provided on the side surface 43 of the element 40.

（素子の第２変形例）
図１８に示すように、素子４０の側面４３に、平面視における素子４０の中心側に突出する突起４３２を形成してもよい。これによって、素子４０の側面４３が接着剤３６に接触する面積を増加させることができる。また、突起４３２に起因するアンカー効果により、接着剤３６が剥がれにくくなる。このため、基板２０に対して素子４０をより強固に固定することができる。 (Second modification of the element)
As shown in FIG. 18, a protrusion 432 projecting toward the center of the element 40 in a plan view may be formed on the side surface 43 of the element 40. As a result, the area where the side surface 43 of the element 40 comes into contact with the adhesive 36 can be increased. In addition, the adhesive 36 is less likely to come off due to the anchor effect caused by the protrusion 432. Therefore, the element 40 can be more firmly fixed to the substrate 20.

貫通電極基板が搭載される製品の例
図１９は、本開示の実施形態に係る電子デバイス１０が搭載されることができる製品の例を示す図である。本開示の実施形態に係る電子デバイス１０は、様々な製品において利用され得る。例えば、ノート型パーソナルコンピュータ１１０、タブレット端末１２０、携帯電話１３０、スマートフォン１４０、デジタルビデオカメラ１５０、デジタルカメラ１６０、デジタル時計１７０等に搭載される。 Example of Product on which Through Electrode Substrate is Mounted FIG. 19 is a diagram showing an example of a product on which the electronic device 10 according to the embodiment of the present disclosure can be mounted. The electronic device 10 according to the embodiment of the present disclosure can be used in various products. For example, it is mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, and the like.

１０ 電子デバイス
２０ 基板
２１ 第１面
２２ 第２面
２３ 無機層
２４Ａ 凹部
２４Ｂ 貫通孔
２５ 底面
２６ 側面
２６１ 段部
２６２ 突起
２７ フィン構造部
２７１ 突起
２８ 流路
２９ 伝熱層
３０ 貫通電極部
３５ 固定部
３６ 接着剤
４０ 素子
４１ 第１面
４２ 第２面
４３ 側面
４３１ 段部
４３２ 突起
４６ 素子基板
４７ 機能層
４８ 第１カッター
４９ 第２カッター
５０ 配線層
５１ 第１配線層
５２ 第２配線層
５３ 第３配線層
５４ 絶縁層
５５ 導電部
５６ 被覆層
６１ 第１カッター
６２ 第２カッター 10 Electronic device 20 Substrate 21 First surface 22 Second surface 23 Inorganic layer 24A Recess 24B Through hole 25 Bottom surface 26 Side 261 Steps 262 Projection 27 Fin structure 271 Projection 28 Flow path 29 Heat transfer layer 30 Through electrode 35 Fixed 36 Adhesive 40 Element 41 First surface 42 Second surface 43 Side surface 431 Steps 432 Protrusion 46 Element substrate 47 Functional layer 48 First cutter 49 Second cutter 50 Wiring layer 51 First wiring layer 52 Second wiring layer 53 Third Wiring layer 54 Insulation layer 55 Conductive part 56 Coating layer 61 First cutter 62 Second cutter

Claims (11)

第１面及び前記第１面の反対側に位置する第２面を含むとともに無機層を有する基板を準備する準備工程と、
導電性樹脂又は複数の導電性粒子を含む接着剤を用いて、前記第１面側から前記基板に素子を固定する固定工程と、
前記素子に電気的に接続された導電部を含む配線層を形成する配線層形成工程と、を備え、
前記配線層形成工程は、前記基板の法線方向に沿って前記導電部を見た場合に前記導電部が前記素子と重なる領域から、前記重なる領域の外側へ延びるよう、前記導電部を形成し、
前記準備工程は、その側面に段部が設けられた凹部が形成された前記基板を準備し、
前記段部は、前記第１面側に位置する前記凹部の前記側面が前記第２面側に位置する前記凹部の前記側面よりも平面視における前記凹部の中心側に位置するように構成されており、
前記固定工程は、前記素子を前記凹部に固定する、電子デバイス製造方法。 A preparatory step for preparing a substrate including a first surface and a second surface located on the opposite side of the first surface and having an inorganic layer.
A fixing step of fixing an element to the substrate from the first surface side using a conductive resin or an adhesive containing a plurality of conductive particles.
A wiring layer forming step of forming a wiring layer including a conductive portion electrically connected to the element is provided.
The wiring layer forming step, from said region where the conductive portion is overlapped with the device, so as to extend to the outside of the overlapping area, to form the conductive portion when viewed the conductive portion along the normal direction of the substrate ,
In the preparation step, the substrate having a recess provided with a step portion on the side surface thereof is prepared.
The step portion is configured such that the side surface of the recess located on the first surface side is located closer to the center of the recess in a plan view than the side surface of the recess located on the second surface side. Ori,
The fixing step is an electronic device manufacturing method in which the element is fixed in the recess . 前記準備工程は、前記第１面に平行な方向における寸法が前記第１面から前記第２面に向かうにつれて減少する前記凹部が形成された前記基板を準備する、請求項１に記載の電子デバイス製造方法。 The preparation process prepares the substrate on which the concave portion is formed to the dimension in the direction parallel to the first surface decreases toward the second surface from the first surface, the electronic device according to claim 1 Production method. 前記電子デバイス製造方法は、前記素子を前記凹部に固定した後、前記基板を前記第２面側から削る切削工程を更に備える、請求項１又は２に記載の電子デバイス製造方法。 The electronic device manufacturing method according to claim 1 or 2 , further comprising a cutting step of cutting the substrate from the second surface side after fixing the element in the recess. 第１面及び前記第１面の反対側に位置する第２面を含むとともに無機層を有する基板と、
前記基板に固定された素子と、
前記素子に電気的に接続された導電部を含む配線層と、
前記基板と前記素子との間に設けられ、導電性樹脂又は複数の導電性粒子を含む接着剤と、を備え、
前記配線層の前記導電部は、前記基板の法線方向に沿って前記導電部を見た場合に前記素子と重なる領域から、前記重なる領域の外側へ延びており、
前記基板は、前記素子を収容する凹部又は貫通孔を有し、
前記基板の前記凹部又は貫通孔の側面に段部が設けられており、
前記段部は、前記第１面側に位置する前記凹部又は貫通孔の前記側面が、前記第２面側に位置する前記凹部又は貫通孔の前記側面よりも、平面視における前記凹部又は貫通孔の中心側に位置するように構成されている、電子デバイス。 A substrate containing a first surface and a second surface located on the opposite side of the first surface and having an inorganic layer,
The element fixed to the substrate and
A wiring layer including a conductive portion electrically connected to the element,
A conductive resin or an adhesive containing a plurality of conductive particles, which is provided between the substrate and the element, is provided.
The conductive portion of the wiring layer extends from a region that overlaps with the element to the outside of the overlapping region when the conductive portion is viewed along the normal direction of the substrate .
The substrate has recesses or through holes for accommodating the element.
A step portion is provided on the side surface of the recess or the through hole of the substrate.
In the stepped portion, the side surface of the recess or through hole located on the first surface side is more than the side surface of the recess or through hole located on the second surface side. An electronic device that is configured to be located on the central side of the . 前記基板の前記凹部又は貫通孔の、前記第１面に平行な方向における寸法は、前記第１面から前記第２面に向かうにつれて減少する、請求項４に記載の電子デバイス。 The electronic device according to claim 4 , wherein the size of the recess or through hole of the substrate in a direction parallel to the first surface decreases from the first surface toward the second surface. 前記基板は、前記第２面側に形成されたフィン構造部を有する、請求項４又は５に記載の電子デバイス。 The electronic device according to claim 4 or 5 , wherein the substrate has a fin structure formed on the second surface side. 前記基板は、前記第１面と前記第２面との間に形成された流路を有する、請求項４乃至６のいずれか一項に記載の電子デバイス。 The electronic device according to any one of claims 4 to 6 , wherein the substrate has a flow path formed between the first surface and the second surface. 前記基板は、前記第２面を構成する伝熱層を有する、請求項４乃至７のいずれか一項に記載の電子デバイス。 The electronic device according to any one of claims 4 to 7 , wherein the substrate has a heat transfer layer constituting the second surface. 前記基板は、前記配線層の前記導電部に電気的に接続され、前記基板を前記第１面側から前記第２面側へ貫通する貫通電極部を有する、請求項４乃至８のいずれか一項に記載の電子デバイス。 Any one of claims 4 to 8 , wherein the substrate is electrically connected to the conductive portion of the wiring layer and has a through electrode portion that penetrates the substrate from the first surface side to the second surface side. The electronic device described in the section. 前記素子の側面に段部が設けられている、請求項４乃至９のいずれか一項に記載の電子デバイス。 The electronic device according to any one of claims 4 to 9 , wherein a step portion is provided on a side surface of the element. 前記素子の側面に突起が設けられている、請求項４乃至１０のいずれか一項に記載の電子デバイス。 The electronic device according to any one of claims 4 to 10 , wherein a protrusion is provided on the side surface of the element.
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