TW201517217A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201517217A
TW201517217A TW103120518A TW103120518A TW201517217A TW 201517217 A TW201517217 A TW 201517217A TW 103120518 A TW103120518 A TW 103120518A TW 103120518 A TW103120518 A TW 103120518A TW 201517217 A TW201517217 A TW 201517217A
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Taiwan
Prior art keywords
wire
electrode
semiconductor device
semiconductor wafer
wiring
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Application number
TW103120518A
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English (en)
Inventor
Susumu Inakawa
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Ps4 Luxco Sarl
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Publication of TW201517217A publication Critical patent/TW201517217A/zh

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Abstract

本發明係一種半導體裝置及其製造方法，其中，具備：第1範圍，和具有配置於第1範圍外側之中繼墊片及連接墊片之配線基板，和於一面，加以形成有電極墊片，加以搭載於配線基板之第1範圍之第1半導體晶片，和連接電極墊片與中繼墊片之第1導線，和連接中繼墊片與連接墊片之第2導線之半導體裝置。

Description

半導體裝置及其製造方法
本發明係有關半導體裝置及其製造方法，特別是有關BGA(Ball Grid Array)型之半導體裝置及其製造方法。
一般的BGA型半導體裝置係具有：連接搭載於配線基板之半導體晶片，和電性連接半導體晶片之電極墊片與配線基板的連接墊片的打線。
作為關聯於此等之技術，例如，有著日本特開2013-38296號(專利文獻1)，日本特開2000-124391號(專利文獻2)。
對於專利文獻1，係揭示有搭載複數之半導體晶片之MCP(Multi Chip Package)型的半導體裝置。另外，對於專利文獻2係，揭示有連續性地導線連接第1及第2半導體晶片的電極與配線基板之構成。
先前技術文獻 專利文獻
專利文獻1：日本特開2013-38296號公報
專利文獻2：日本特開2000-124391號公報
在上述以往技術中，配置於搭載在配線基板之半導體晶片的一邊之電極墊片的數量為多之情況，或者在複數之半導體晶片，於相同邊側，配置許多電極墊片之情況，配線基板上之配線圖案的引導則成為困難，或者有成為繞行之配線的問題。
因此，本發明係提供：可容易地進行配線基板上之配線圖案的引導之半導體裝置及其製造方法。
有關本發明之一形態之半導體裝置，其特徵為具備：第1範圍，和具有配置於該第1範圍外側之第1及第2連接墊片之配線基板，和於一面，加以形成有第1電極，加以搭載於前述配線基板之前述第1範圍之第1半導體晶片，和連接前述第1電極與前述第1連接墊片之第1導線，和連接前述第1連接墊片與前述第2連接墊片之第2導線者。
另外，有關本發明之一形態之半導體裝置之製造方法，其特徵為具有：於一面，準備第1範圍，和具有配置於該第1範圍外側之第1及第2連接墊片之配線基板的工程，和將加以形成有第1電極於一面之第1半導體晶片，搭載於前述配線基板之前述第1範圍的工程，和經由第1導線，連接前述第1電極與前述第1連接墊片之工程，和經由第2導線，連接前述第1連接墊片與前述第2連接墊片之工程者。
如根據本發明，可容易地進行配線基板上之配線圖案的引導者。
10‧‧‧配線基板
11‧‧‧絕緣基材
12‧‧‧配線
13‧‧‧貫孔
14‧‧‧絕緣膜
15‧‧‧連接墊片
16‧‧‧中繼墊片
17‧‧‧金屬銲點
18‧‧‧焊球
19‧‧‧半導體晶片
20‧‧‧接著構件
21‧‧‧電極墊片
22‧‧‧第1導線
23‧‧‧第2導線
24‧‧‧封閉體
25‧‧‧SR開口
40‧‧‧切割線
50‧‧‧毛細管
51‧‧‧導線
52‧‧‧球部
70‧‧‧半導體晶片(下段)
90‧‧‧半導體晶片(上段)
91‧‧‧第3導線
92‧‧‧電極墊片
93‧‧‧柱形凸塊
100‧‧‧半導體裝置
200‧‧‧半導體裝置
300‧‧‧半導體裝置
圖1係顯示有關本發明之第1實施形態的半導體裝置之概略構成的平面圖。
圖2係顯示圖1之A-A'間的概略構成的剖面圖。
圖3係顯示有關本發明之第1實施形態的半導體裝置之變形例的概略構成的剖面圖。
圖4係顯示有關本發明之第1實施形態的半導體裝置之組裝流程的剖面圖。
圖5係顯示打線接合之處理流程的剖面圖。
圖6係顯示本發明之第2實施形態之半導體裝置之概略構成的平面圖。
圖7係顯示圖6之B-B'間的概略構成的剖面圖。
圖8係顯示本發明之第3實施形態之半導體裝置之概略構成的平面圖。
圖9(a)，(b)係各顯示圖8之C-C’間，D-D’間的概略構成之剖面圖。
圖10係顯示本發明之第3實施形態之打線接合之處理流程的剖面圖。
圖11係顯示有關本發明之實施形態的半導體裝置之變形例的概略構成的平面圖。
以下，參照圖面的同時，對於本發明之理想的實施形態加以詳細說明。
(第1實施形態)
參照圖1，圖2，說明有關本發明之第1實施形態之半導體裝置之構成。
在此，圖1係顯示有關本發明之第1實施形態的半導體裝置之概略構成的平面圖。圖2係顯示圖1之A-A'間的概略構成的剖面圖。
第1實施形態的半導體裝置100係如圖1及 圖2所示，為略四角形的板狀，具有形成有特定之配線圖案之配線基板10。配線基板10係例如，具有玻璃聚酯基材或由預浸材料所成之絕緣基材11。並且，對於絕緣基材11之上面(一面)與下面(另一面)，係由特定的圖案而加以形成有配線(配線層)12，2層之配線12係經由貫孔13而加以電性連接。
另外，對於絕緣基材11之上面及下面，係加以形成有絕緣膜14(例如，抗焊劑膜)，配線12的一部分則從絕緣膜14加以露出。從配線基板10之上面側的配線12之絕緣膜14之開口(SR開口25)露出之部位，則成為連接墊片15，中繼墊片16，而從配線基板10之另一面側的配線12之絕緣膜14之開口(SR開口25)露出之部位，則成為金屬銲點17。並且，對於此金屬銲點17係搭載有焊球18。
另外，對於配線基板10之上面，係藉由接著構件(DAF)20而加以搭載有半導體晶片19。半導體晶片19係例如，形成有記憶體電路之記憶體晶片，例如沿著長方形之短邊而各加以配置複數之電極墊片21。並且，對於一方的短邊係主要配置有DQ系之電極墊片21，而對於另一方之短邊係加以配置有指令暫存器系之電極墊片21，DQ系側之短邊的電極墊片21的數量係呈較指令暫存器系側之電極墊片21的數量為多地加以構成。
電極墊片21與中繼墊片16係經由第1導線22而加以連接，中繼墊片16與連接墊片15係經由第2 導線23而加以連接。此時，第2導線23係呈跨越配線12地加以配置。並且，至少呈被覆半導體晶片19地，於配線基板10之上面，加以形成有封閉體(封閉樹脂)24。
如此之構成之下，在加以配置有電極墊片21之數量為多之DQ側的配線基板10之一面(上面)中，一部分之配線12則呈橫切地加以配置，而配線12之引導則成為困難，以及成為繞行之配線的情況，於半導體晶片19之電極墊片21與連接墊片15之間，配置中繼墊片16，呈經由第2導線23而跨越其他之橫切的配線12地構成。
如此之配線12的引導之問題係可將配線基板10，從2層之配線層，做為3層以上之配線層者而作為對策，但配線基板10之製造成本則上升(半導體裝置100之成本增加)，更且由層數增加者，配線基板10之厚度(半導體裝置100之厚度)亦變大。但如第1實施形態，於配線12密集之範圍，配置中繼墊片12，由呈以第2導線23跨越在其他的配線12地構成者，未增加有配線基板10之成本上升及基板厚度，而可容易地解決配線12之引導之課題。
更且，由設置中繼墊片16於配線基板10者。可提升配線基板10之佈局設計的自由度。另外，未做為引導，而以第2導線23而跨越其他的配線12進行連接者，可縮短配線長度。
另外，未使用中繼墊片16，而對於導線連接於離間之連接墊片15之情況，導線長度則變長，在塑模 時，產生導線偏移或導線短路之風險變大，但在第1實施形態中，對於中繼墊片16亦加以連接有第1導線22及第2導線23之故，導線長度係為同等，但作為圈之部分的長度為短之故，可降低產生導線偏移或導線短路之風險。
更且，為使導線連接於中繼墊片16，而呈藉由中繼墊片16而彎曲電極墊片21與連接墊片15地可布置導線之故，更可降低產生有導線短路之風險。
另外，在第1實施形態中，將連接半導體晶片19之電極墊片21與配線基板10之中繼墊片16之第1導線22，和連接配線基板10之中繼墊片16與連接墊片15之第2導線23，以一個導線連續性地構成。因此，在打線接合之時，可減少形成球於導線前端的次數，而可降低導線之使用量。例如，加以使用Au導線之故，而可降低Au之使用量而降低成本。
然而，在圖2中，對於將連接半導體晶片19之電極墊片21與配線基板10之中繼墊片16之第1導線22，和連接配線基板10之中繼墊片16與連接墊片15之第2導線23，以一個導線而形成之情況加以說明過。
但如圖3所示，將連接半導體晶片19之電極墊片21與配線基板10之中繼墊片16之第1導線22，和連接配線基板10之中繼墊片16與連接墊片15之第2導線23，各經由個別之導線而形成亦可。對於經由個別之導線而形成之情況，係可提升配置中繼墊片16的位置之自由度。
接著，參照圖4，對於有關本發明之第1實施形態之半導體裝置之製造方法，亦使用圖1，圖2而加以說明。在此，圖4係顯示有關第1實施形態的半導體裝置100之組裝流程的剖面圖。
首先，如圖4(a)所示，加以準備配線基板10。配線基板10係由絕緣基材11而加以形成，於一面(上面)，加以形成絕緣膜14與連接墊片15，中繼墊片16。另一方面，對於配線基板10之另一面(下面)，係加以形成有絕緣膜14與金屬銲點17。更且，對於配線基板10係加以設置有切割線40。
接著，如圖4(b)所示，將形成有接著構件(DAF)20於背面之半導體晶片19，加以搭載於配線基板10。
接著，如圖4(c)所示，經由第1導線22而電性連接半導體晶片19之電極墊片21和配線基板10之中繼墊片16。更且，經由第2導線23而電性連接配線基板10之中繼墊片16與連接墊片15。此時，第2導線23係呈跨越配線12地加以配置。
在此，參照圖5，對於第1導線22及第2導線23之連接方法加以說明。圖5係顯示打線接合之處理流程的剖面圖。
首先，如圖5(a)所示，第1導線22及第2導線23係例如由Au等而成，將形成有球部52於毛細管50之所熔融之前端之導線51，超音波熱壓著於半導體晶片 19之電極墊片21上。
接著，如圖5(b)所示，使毛細管50移動而描繪特定的圈形狀同時，將導線51之後端，超音波熱壓著於中繼墊片16上。經由此等，經由第1導線22而加以連接有半導體晶片19之電極墊片21與中繼墊片16。
接著，如圖5(c)所示，更使毛細管50移動，將導線51之後端，超音波熱壓著於連接墊片15上。經由此等，經由第2導線23而加以連接有半導體晶片19之中繼墊片16與連接墊片15。由如此作為，打線接合之處裡則完了。
接著，如圖2(d)所示，由一次塑模者，於配線基板10之一面上，形成有封閉體24(封閉樹脂)。封閉體24係例如，由未圖示之轉換模具裝置之上模與下模所成之成形金屬模具，夾合配線基板10，從澆口至經由上模與下模所形成之模孔內，使熱硬化性之環氧樹脂壓入，加以充填於模孔內之後，由加以使其熱硬化所形成。
接著，如圖2(e)所示，於配線基板10之另一面之金屬銲點17上，搭載焊球18而形成外部端子(凸塊電極)。在球安裝工程中，配合配線基板10上之金屬銲點17的配置，使用形成有複數之吸附孔之未圖示的吸附機構，將焊球18保持於吸附孔，於所保持之焊球18，轉印形成助熔劑，一次搭載於配線基板10之金屬銲點17。球搭載後，由進行迴焊而加以形成有外部端子。
接著，如圖2(f)所示，外部端子之所形成 的配線基板10係由切割線40進行切斷‧分離而作為個片化。基板切割係將配線基板10之封閉體24，接著於切割膠帶，經由切割膠帶而支持配線基板10。將配線基板10，經由未圖示之切割刀片，切斷切割線40於縱橫，個片化配線基板10。個片化完了後，由從切割膠帶拾取者，得到圖2所示之半導體裝置100。
(第2實施形態)
接著，參照圖6，圖7，對於有關本發明之第2實施形態之半導體裝置200之構成加以說明。在此，圖6係顯示第2實施形態之半導體裝置200之概略構成的平面圖。圖7係顯示圖6之B-B'間的概略構成的剖面圖。然而，說明的方便上，對於與圖1，圖2所示之第1實施形態之半導體裝置100相同部位，係附上相同參照符號，其說明係省略。
本發明之第2實施形態之半導體裝置200係與第1實施形態之半導體裝置100不同的點係於配線基板10與第1半導體晶片19(上段半導體晶片)之間，加以配置有其他之半導體晶片70(下段半導體晶片)的點。其他之半導體晶片70(下段半導體晶片)係具有與第1半導體晶片19略相同之構成。
如圖6及圖7所示，在第2實施形態之半導體裝置200中，於配線基板10上，加以搭載有2個半導體晶片19，70。如上述，第1半導體晶片19係構成上段 半導體晶片，其他的半導體晶片70係構成下段半導體晶片。
在此，半導體晶片70係形成有與第1實施形態之半導體晶片19同樣之記憶體電路之記憶體晶片，例如，沿著長方形之短邊而各加以配置有複數之電極墊片21。上段之半導體晶片19(記憶體晶片)係對於下段之半導體晶片70(記憶體晶片)而言，呈作為90°旋轉地加以層積搭載。並且，對於半導體晶片19，70之一方的短邊係主要配置有DQ系之複數的電極墊片21，而對於另一方之短邊係加以配置有指令暫存器系之複數的電極墊片21，DQ系側之短邊的電極墊片21的數量係呈較指令暫存器系側之電極墊片21的數量為多地加以構成。
各半導體晶片19，70係電極墊片21的數量為多之短邊與配線基板10之端部之間隔則呈較對向之電極墊片21的數量少之短邊與配線基板10之端部之間隔為寬地，加以搭載於配線基板10上。
並且，與第1實施形態同樣地，如圖6及圖7所示，在配置有各半導體晶片19，70之電極墊片21的數量為多之DQ側之配線基板10中，於配線12密集之處，配置中繼墊片16。並且，使半導體晶片19，70之電極墊片21與連接墊片15之間的中繼墊片16介入存在，呈經由第2導線23而跨越其他配線12地構成。
在第2實施形態中，得到與第1實施形態同樣的效果同時，交互層積2個半導體晶片19，70，由配 線12之密集的範圍呈變寬地偏移而搭載於配線基板10者，謀求半導體裝置200之大容量化同時，可提升配線佈局之自由度。
(第3實施形態)
接著，參照圖8，圖9，對於有關本發明之第3實施形態之半導體裝置300之構成加以說明。在此，圖8係顯示第3實施形態之半導體裝置300之概略構成的平面圖。圖9(a)，(b)係各顯示圖8之C-C’間，D-D’間的概略構成之剖面圖。
然而，說明的方便上，對於與圖1，圖2所示之第1實施形態之半導體裝置100相同部位，係附上相同參照符號，其說明係省略。
本發明之第3實施形態之半導體裝置300係與第1實施形態之半導體裝置100同樣地加以構成，但如圖8及圖9所示，於配線基板10上，加以搭載有複數之半導體晶片19，90，將成為各半導體晶片19，90之共通銷之電極墊片21與電極墊片92之間，呈以第3導線91而連接地構成的點則與第1實施形態不同。各半導體晶片19，90之獨立銷，例如，晶片選擇銷等之電極墊片21，92係各加以連接於配線基板10之連接墊片15。
如此，在第3實施形態中，於半導體晶片19上，層積形成有電極墊片92之半導體晶片90。在此，半導體晶片19係構成下段半導體晶片，而半導體晶片90係 構成上段半導體晶片。另外，對於下段之半導體晶片19之電極墊片21上，係加以有設置有Au等所成之柱形凸塊93。
在第3實施形態中，亦得到與第1實施形態同樣的效果同時，亦包含半導體晶片19與半導體晶片90間的連接而可以1個導線連接之故，可以1個導線而連接成為共通銷之電極墊片21，92。更且，以一個導線，由連接複數之半導體晶片19，90，和配線基板10之連接墊片15，和中繼墊片16者，減少對於導線之球形成次數與導線切割之次數，而可提升打線接合工程之處理效率。
接著，參照圖10，對於第3實施形態之打線接合之處理流程而加以說明。在此，圖10係顯示第3實施形態之打線接合之處理流程的剖面圖。
對於下段之半導體晶片19之電極墊片21上，係預先加以形成有Au等所成之柱形凸塊93。
並且，如圖10(a)所示，於上段之半導體晶片90之電極墊片92上，以超音波熱壓著，接合毛細管50之導線51的球部52。
接著，如圖10(b)所示，描繪特定的圈，於下段之半導體晶片19之電極墊片21上之柱形凸塊93，經由超音波熱壓著而接合另一端側。
接著，如圖10(c)所示，未切斷導線51，而又呈描繪圈地使毛細管50移動，將接下來之另一端側，經由超音波熱壓著而接合於配線基板10之中繼墊片 16。
接著，如圖10(d)所示，未切斷導線51，而使毛細管50移動，呈跨越配線12地，將接下來之另一端側，經由超音波熱壓著而接合於配線基板10之連接墊片15。由如此作為，如圖9(a)所示，連續性地形成第1，第2及第3導線22，23，91。
以上，依據實施形態而說明過經由本發明者所作為之發明，但本發明係並不加以限定於前述實施形態者，而在不脫離其內容的範圍當然可做種種變更者。
在上述實施形態中，對於設置中繼墊片16於配線基板10上之情況加以說明過，但呈設置中繼墊片16於半導體晶片19上地構成亦可。
另外，對於配置1個中繼墊片16於配線基板10上之情況已做過說明，但如圖11所示，呈歷經複數之中繼墊片16而連接半導體晶片19之電極墊片21與配線基板10之連接墊片15地構成亦可。
另外，對於搭載記憶體晶片之情況已做過說明，但如為成為配線基板10上之配線12為密集之構成之半導體裝置，亦可適用於任何之半導體晶片及晶片的組合，例如，記憶體晶片與邏輯晶片之組合等，或任何之墊片組合之晶片。
本申請係於2013年6月18日所提出申請，將自日本國專利申請第2013-127216號之優先權作為基礎，主張其利益，其揭示係作為全體參考文獻而放入於 此。
10‧‧‧配線基板
11‧‧‧絕緣基材
12‧‧‧配線
13‧‧‧貫孔
14‧‧‧絕緣膜
15‧‧‧連接墊片
16‧‧‧中繼墊片
17‧‧‧金屬銲點
18‧‧‧焊球
19‧‧‧半導體晶片
20‧‧‧接著構件
21‧‧‧電極墊片
22‧‧‧第1導線
23‧‧‧第2導線
24‧‧‧封閉體
100‧‧‧半導體裝置

Claims (18)

  1. 一種半導體裝置，其特徵為具備：具有第1範圍和配置於該第1範圍外側之第1及第2連接墊片之配線基板，和於一面形成有第1電極，搭載於前述配線基板之前述第1範圍之第1半導體晶片，和連接前述第1電極與前述第1連接墊片之第1導線，和連接前述第1連接墊片與第2連接墊片之第2導線者。
  2. 如申請專利範圍第1項記載之半導體裝置，其中，前述第1導線與前述第2導線係以一個導線而連續性地加以構成者。
  3. 如申請專利範圍第1項記載之半導體裝置，其中，前述第1導線與前述第2導線係以個別的導線而加以構成者。
  4. 如申請專利範圍第1項至第3項任一項記載之半導體裝置，其中，對於前述第1範圍之外側，係更設置有配線，前述第2導線係呈跨越前述配線地加以配置者。
  5. 如申請專利範圍第4項記載之半導體裝置，其中，前述第1半導體晶片係加以構成為略長方形，前述第1電極係沿著前述略長方形之第1及第2短邊而加以複數個配置， 配置於前述第1短邊之前述第1電極的數量係較配置於前述第2短邊之前述第1電極的數量為多，在前述第1短邊側中，藉由前述第2導線而加以連接有前述第1連接墊片與前述第2連接墊片者。
  6. 如申請專利範圍第5項記載之半導體裝置，其中，前述第1短邊側係前述配線為密集之配線密集範圍者。
  7. 如申請專利範圍第6項記載之半導體裝置，其中，前述第1連接墊片係在前述配線密集範圍中，構成中繼墊片，經過前述中繼墊片，前述第2導線越過前述配線而與前述第2連接墊片連接者。
  8. 如申請專利範圍第7項記載之半導體裝置，其中，前述第1導線係在前述第1電極與前述中繼墊片之間彎曲的狀態而加以連接者。
  9. 如申請專利範圍第5項至第8項任一項記載之半導體裝置，其中，對於前述配線基板與前述第1半導體晶片之間，係加以配置有具有與前述第1半導體晶片略相同構造之其他的半導體晶片，前述第1半導體晶片係對於前述其他的半導體晶片而言，呈90°地旋轉地加以層積搭載，前述第1短邊與前述配線基板之端部之間隔係較前述第2短邊與前述配線基板之端部之間隔為寬者。
  10. 如申請專利範圍第1項至第8項任一項記載之半 導體裝置，其中，更具備：於一面形成有第2電極，層積於前述第1半導體晶片上之第2半導體晶片，和連接前述第1電極與前述第2電極之第3導線者。
  11. 如申請專利範圍第7項至第10項任一項記載之半導體裝置，其中，前述中繼墊片係加以複數個設置於前述第1電極與前述第2連接墊片之間者。
  12. 一種半導體裝置之製造方法，其特徵為具有：於一面，準備第1範圍，和具有配置於該第1範圍外側之第1及第2連接墊片之配線基板的工程，和將加以形成有第1電極於一面之第1半導體晶片，搭載於前述配線基板之前述第1範圍的工程，和經由第1導線，連接前述第1電極與前述第1連接墊片之工程，和經由第2導線，連接前述第1連接墊片與第2連接墊片之工程者。
  13. 如申請專利範圍第12項記載之半導體裝置之製造方法，其中，更具有：至少呈被覆前述第1半導體晶片地，於前述配線基板之前述一面，形成封閉樹脂之工程。
  14. 如申請專利範圍第12項或第13項記載之半導體裝置之製造方法，其中，前述第1導線與前述第2導線係以一條導線連續地構成者。
  15. 如申請專利範圍第12項或第13項記載之半導體裝置之製造方法，其中，前述第1導線與前述第2導線係以個別的導線而形成者。
  16. 如申請專利範圍第12項至第15項任一記載之半導體裝置之製造方法，其中，更具有：於前述第1範圍的外側形成配線之工程，前述第2導線係呈跨越前述配線地加以形成者。
  17. 如申請專利範圍第12項至第16項任一記載之半導體裝置之製造方法，其中，更具有：於前述第1半導體晶片上，層積於一面形成有第2電極之第2半導體晶片的工程，和經由第3導線，連接前述第1電極與前述第2電極之工程者。
  18. 如申請專利範圍第17項記載之半導體裝置之製造方法，其中，更具有：預先形成柱形凸塊於前述第1半導體晶片的前述第1電極上之工程，和於前述第2半導體晶片之前述第2電極上，以超音波熱壓著而接合毛細管之導線的球部的工程，和使前述毛細管移動，前述導線呈描繪特定的圈地，於前述柱形凸塊，經由超音波熱壓著而接合前述球部的工程，和未切斷前述導線，而更且呈描繪圈地，使前述毛細管移動，於前述配線基板之前述第1及第2連接墊片，經由超音波熱壓著而接合之工程，經由此，連續性地形成前述第1，第2及第3導線者。
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