TW201413882A - 半導體裝置及成型一半導體裝置之方法 - Google Patents
半導體裝置及成型一半導體裝置之方法 Download PDFInfo
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Abstract
一種半導體裝置,包括一晶粒及一散熱器。晶粒係設置於一底材之內,並且係位於底材之一第一側邊處。晶粒具有複數個接觸墊。散熱器係設置於底材之內,並且係位於底材之一第二側邊處。散熱器係與晶粒熱接觸。
Description
本發明是有關於一種半導體裝置,特別是有關於一種成型一半導體裝置之方法。
一般來說,在現代電子設計中之其中一個驅動因素係為計算功率的數量以及能被裝入一指定空間中之儲存量。眾所周知之Moore's定律敘述了在一指定裝置上之電晶體的數目會每18個月粗略地加倍。為了壓縮更多之處理功率至較小之封裝之中,電晶體尺寸已被降低去指向進一步縮減電晶體尺寸之能力已被材料及製程之物理特性所限制。再者,在不斷萎縮封裝形式因素中之更為強力之處理器的使用係導致一熱量管理問題。被增加之裝置運作速度,會產生可能損壞或降低元件效率之熱量。再者,較緊密之封裝整合以及較小巧之裝置會帶來更多熱量產生裝置至較小的區域之中,以濃縮所產生之熱量。
本發明基本上採用如下所詳述之特徵以為了要解決上述之問題。
本發明之一實施例提供一種半導體裝置,包括一晶粒,設置於一底材之內,並且位於該底材之一第一側邊處,
其中,該晶粒具有複數個接觸墊;以及一散熱器,設置於該底材之內,並且位於該底材之一第二側邊處,其中,該散熱器係與該晶粒熱接觸。
根據上述之實施例,該半導體裝置更包括至少一中介窗,係設置於該底材之中,並且係從該底材之該第一側邊延伸至該底材之該第二側邊。
根據上述之實施例,該半導體裝置更包括一第一再分佈層,係位於該底材之該第一側邊處,其中,該第一再分佈層具有複數個再分佈層接觸墊以及至少一導線,該導線係電性連接位於該晶粒上之一接觸墊於該等再分佈層接觸墊之至少一個,以及該等再分佈層接觸墊具有大於設置於該晶粒上之該等接觸墊之接合節距之一接合節距。
根據上述之實施例,該半導體裝置更包括一第二再分佈層,係位於該底材之該第二側邊處,其中,該第二再分佈層具有至少一導線。
根據上述之實施例,該第二再分佈層係覆蓋該散熱器。
根據上述之實施例,該至少一導線之一部分係設置於該散熱器之上。
根據上述之實施例,該第二再分佈層係設置於該散熱器之一部分處,以及該第二再分佈層具有暴露該散熱器之一表面之一部分之一熱暴露開口。
根據上述之實施例,該半導體裝置更包括一晶粒附著層,係設置於該底材之該第二側邊與該散熱器之間以及係
與該底材之該第二側邊及該散熱器接觸。
本發明之另一實施例提供一種半導體裝置,包括一晶粒,設置於一底材之內,並且具有複數個接觸墊,其中,該等接觸墊係設置鄰接於該底材之一第一側邊;一晶粒附著層,設置鄰接於該底材之一第二側邊;一散熱器,嵌入於該底材之內,並且設置於該晶粒附著層之上;以及一第一再分佈層,設置於該晶粒之該等接觸墊之上。
根據上述之實施例,該底材係為一模鑄底材,以及該第一再分佈層係設置於該模鑄底材之該第一側邊之上。
根據上述之實施例,該半導體裝置更包括複數個再分佈層接觸墊,設置於該第一再分佈層之內;以及至少一導線,設置於該第一再分佈層之內,並且電性連接位於該底材之該第一側邊上之一接觸墊於該等再分佈層接觸墊之至少一個,其中,該等再分佈層接觸墊具有大於設置於該底材之該第一側邊上之該等接觸墊之接合節距之一接合節距。
本發明之又一實施例提供一種成型一半導體裝置之方法,包括:成型一被圖刻光罩於一攜載底材之上,其中,該被圖刻光罩具有一散熱器開口;成型一散熱器於位於該散熱器開口中之該攜載底材之上;固定一晶粒於該散熱器之上,其中,該晶粒係與該散熱器熱接觸;以及藉由應用一模鑄化合物成型一模鑄底材於該晶粒及該散熱器之上,其中,該晶粒係設置於該模鑄底材之一第一側邊處,以及該散熱器係設置於該模鑄底材之一第二側邊。
根據上述之實施例,該成型一半導體裝置之方法
更包括:成型至少一中介窗開口於該被圖刻光罩之中;以及成型一中介窗於該中介窗開口之中。
根據上述之實施例,成型該中介窗之步驟以及成型該散熱器之步驟係在相同時間使用一電鍍製程。
根據上述之實施例,該晶粒係經由一晶粒附著薄膜固定於該散熱器。
根據上述之實施例,成型一被圖刻光罩於一攜載底材之上之步驟包括:提供一攜載體;施加一黏著層於該攜載體之上;以及施加一基底薄膜層於該黏著層之上。
根據上述之實施例,成型一被圖刻光罩於一攜載底材之上之步驟更包括:施加一種晶層於該基底薄膜層之上。
根據上述之實施例,該成型一半導體裝置之方法更包括:成型一第一再分佈層於該模鑄底材之該第一側邊處,其中,該第一再分佈層具有複數個再分佈層接觸墊以及複數個導線,以及每一導線係提供一電性連接於一再分佈層接觸墊與該晶粒之一接觸墊之間。
根據上述之實施例,該成型一半導體裝置之方法更包括:成型一第二再分佈層於該模鑄底材之該第二側邊處以及覆蓋該散熱器之至少一部分,其中,該第二再分佈層具有至少一導線,以及該至少一導線係電性接觸於至少一中介窗。
根據上述之實施例,該成型一半導體裝置之方法更包括:提供一開口於暴露該散熱器之一部分之該第二再分佈層之中。
為使本發明之上述目的、特徵和優點能更明顯易
懂,下文特舉較佳實施例並配合所附圖式做詳細說明。
102‧‧‧攜載底材
104‧‧‧種晶層
106‧‧‧基底薄膜層
108‧‧‧黏著層
110‧‧‧攜載體
112‧‧‧光罩層
114‧‧‧被圖刻光罩
116‧‧‧中介窗開口
118‧‧‧散熱器開口
120‧‧‧散熱器
122‧‧‧中介窗
130‧‧‧晶粒
131‧‧‧接觸墊
132‧‧‧晶粒附著層
134、142‧‧‧模鑄化合物
800‧‧‧模鑄底材
900、1000‧‧‧晶圓級組件
901‧‧‧第一再分佈層
902‧‧‧第二再分佈層
904‧‧‧中間電介質
906‧‧‧再分佈層接觸墊
908‧‧‧球型陣列
910‧‧‧導線
1002‧‧‧熱暴露開口
第1至7圖係顯示用於成型一嵌入式散熱器之一方法之一實施例中之中間步驟之剖面示意圖;第8圖係顯示一模鑄底材與散熱器組件之剖面示意圖;第9至10圖係顯示具有嵌入式散熱器之一晶圓級裝置之實施例之剖面示意圖;以及第11圖係顯示用於成型具有一嵌入式散熱器之一晶圓級組件之一方法之流程圖。
茲配合圖式說明本發明之較佳實施例。
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之一較佳實施例的詳細說明中,將可清楚的呈現。以下實施例中所提到的方向用語,例如:上、下、左、右、前或後等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明並非用來限制本發明。
本發明係提供一種系統及方法去製造對於一主動裝置、嵌入式處理器、晶粒、晶片或分離元件之一嵌入式散熱器。一嵌入式散熱器可以允許一發熱元件去散熱或從元件轉移熱量,以降低原件上之熱量負載。提供用於一嵌入式晶粒之一散熱器可以允許較高的晶粒可靠度以及較長之晶粒壽命。
請參閱第1圖,用於成型一晶圓級嵌入式散熱器之一中間步驟之一實施例之剖面示意圖是被繪示。一攜載底材
102可以包括有一攜載體110。攜載體110可以提供結構強度或用於後續非剛性層之沉積之一基底。在一實施例之中,攜載體110可以是玻璃攜載體,但也可以是一晶圓、半導體、金屬、合成材料或具有一適當表面形貌及結構剛性之其他材料。
在一些實施例之中,一膠水或黏著層108可以被施加於攜載體110,其中,一選擇性之基底薄膜層106及一選擇性之種晶層104是被施加於黏著層108之上。在一實施例之中,黏著層108可以是一黏著膠帶或可以是一膠水或經由一旋塗製程(spin-on process)施加於攜載體110之環氧樹脂。在一些實施例之中,黏著層108可以被使用去分離攜載體110於散熱器組件以及關聯之裝置或層。
種晶層104可以是被成型於黏著層108之上,並且種晶層104可以做為對於後續金屬電鍍或沉積步驟之一基底。在一些實施例之中,種晶層104可以被使用做為一電極於一後續之電鍍製程之中。種晶層104可以經由物理氣相沉積(PVD)、化學氣相沉積(CVD)、電漿加強化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)、原子層化學氣相沉積、原子層沉積、濺鍍、電化學沉積等方式被沉積。在一些實施例之中,種晶層104可以是銅。然而,在其他實施例之中,種晶層104可以是金、鋁鉭、鎳或其合金。
在一些實施例之中,基底薄膜層106可以被施加,並且是由可允許後者之層去適當形成之一材料所構成。舉例來說,在一非限制之實施例之中,基底薄膜層106可以是由一聚合物所製成,例如,polybenzoxazole(PBO)。在此一實施例之
中,PBO可以被施加於黏著層108或選擇性地經由旋塗方式被直接施加於攜載體110。透過一旋塗製程,一可固化之聚合物(例如,PBO)可允許基底薄膜層106之應用,但仍然能夠透過固化方式成型一實質堅固之基底薄膜。此外,因為彈性結構被產生於固化做為在具有不同膨脹係數之材料間之一緩衝物之後,PBO可以是有利的。舉例來說,在一實施例之中,攜載體110可以是玻璃,並且其具有一膨脹係數遠低於由銅所製成之一種晶層104之一膨脹係數。在如此一實施例之中,一半剛性之基底薄膜層106可以用於緩衝不同之膨脹固化熱製程。然而,任何適當之材料可以被使用做為基底薄膜層106。
第2圖係顯示用於成型一晶圓級嵌入式散熱器之一中間步驟之一實施例之剖面示意圖。一光罩層112可以被施加於種晶層104之上。在一些實施例之中,光罩層112可以是一光阻,其是經由一旋塗製程被施加。在其他實施例之中,光罩層112可以是一硬光罩,例如,一氮化物、氧化物或氮氧化物等。係為一硬光罩之一光罩層112可以經由物理氣相沉積(PVD)、化學氣相沉積(CVD)或另外適當之沉積方法被施加。
第3圖係顯示使用一被圖刻光罩114用於成型一晶圓級嵌入式散熱器之一中間步驟之一實施例之剖面示意圖。光罩層112是被圖刻及顯影去形成被圖刻光罩114。光罩層112可以被圖刻去形成具有一散熱器開口118或一或多個中介窗開口116之被圖刻光罩114。在一實施例之中,被圖刻光罩114可以被成型,如此一來,被產生於中介窗開口116中之結構可以被初始成型為具有大約105μm之一高度,以及然後被研磨、拋光
或蝕刻成具有大約80μm至大約90μm之一高度。在一些實施例之中,在被圖刻光罩114中之中介窗開口116可以具有大約10μm之一節距以及大約70μm之一直徑。因此,在成型之後,被成型於中介窗開口116中之結構將會具有高度對於寬度比例為1.5:1。
第4圖係顯示根據本發明之一些實施例之散熱器120之成型之剖面示意圖。在一實施例之中,一散熱器120可以經由一電鍍製程(例如,一通過孔隙中介窗(through-aperture-via(TVA))電鍍製程)被沉積。在一些實施例之中,散熱器120可以像一或多個中介窗122一樣被成型以相同之步驟。舉例來說,一非限制之實施例可以在銅被電鍍於種晶層104之上去填充中介窗開口116及散熱器開口118之下部,以分別形成中介窗122及散熱器120。舉例來說,此可以藉由一銅電鍍製程被完成,其中,具有被圖刻光罩114之攜載底材102是被浸入一銅溶液之中,因而可導致銅在種晶層104上之積聚。此外,一無電電鍍製程、化學氣相沉積(CVD)、電漿加強化學氣相沉積(PECVD)或另外之金屬沉積製程可以被運用去成型散熱器120及中介窗122。散熱器120之厚度可以取決於散熱器120之面積以及中介窗122之數目。舉例來說,在一些實施例之中,可以有1200個中介窗122,以及散熱器120可以被成型去具有一厚度介於3μm與5μm之間。
在另一實施例之中,當用於成型散熱器120及中介窗122之製程使用一電鍍製程及同時發生時,成型散熱器120及任何中介窗122可以被執行於多個步驟之中。舉例來說,中介
窗122可以被成型於一第一電鍍步驟之中,以及散熱器120可以被成型於一後續之步驟之中。在如此一實施例之中,被圖刻光罩114可以不用散熱器開口118被成型,但被圖刻光罩114需要以中介窗開口116被成型。中介窗122可以被成型於中介窗開口116之中,以及散熱器開口118可以在中介窗122之成型後而被成型。在中介窗122已經被成型之後,散熱器120可以被成型於散熱器開口118之中。在如此一實施例之中,中介窗122可以在散熱器120之成型過程中被覆蓋。一多重步驟金屬沉積程序可以允許用於中介窗122及散熱器120之不同材料之應用。舉例來說,在由黃金所構成之中介窗122被產生之後,一銅製之散熱器120可以被成型。
在另一實施例之中,被嵌入之散熱器120亦可以被分別地成型以及然後被施加於攜載底材102。在如此一實施例之中,散熱器120可以是被研磨或模鑄遠離於攜載底材102,以及然後被施加於黏著層108、基底薄膜層106或種晶層104。在如此一實施例之中,種晶層104可以被消除,以及散熱器120可以直接被施加於基底薄膜層106、黏著層108或攜載體110。
第5圖係顯示根據本發明之一些實施例之一主動裝置(例如,一晶粒130至散熱器120)之應用之剖面示意圖。被圖刻光罩114是被移除於中介窗122及散熱器120之成型之後。舉例來說,在光罩層112是藉由一光阻被成型之實施例之中,導致之被圖刻光罩114可以經由灰燼化及一選擇性之洗滌或清洗製程而被移除掉。在光罩層112是藉由一硬光罩被成型之實施例之中,導致之被圖刻光罩114可以經由蝕刻而被移除掉,
以留下底下之攜載底材102。
一晶粒130是使用一晶粒附著層132(例如,一晶粒附著薄膜)被施加於散熱器。在一些實施例之中,晶粒附著層132可以具有足夠之熱特性去使晶粒130熱接觸散熱器120。在一些實施例之中,晶粒附著層132可以是一熱化合物,其具有一銀含量足夠去轉移來自於晶粒130之大量熱量至散熱器120,以允許晶粒130運作。因此,晶粒附著層132可以傳送來自於晶粒130之大量熱能至散熱器120,因而降低或維持晶粒130之溫度,當晶粒130是運作於一既定範圍之內時。如此之溫度管理可以允許晶粒130運作以一較高之速度於較長之時間內,當維持晶粒130之元件之完整性時。
在一些實施例之中,藉由晶粒附著層132以及附著晶粒130之上側或非接觸側於散熱器120,晶粒130可以附著於散熱器120。因此,晶粒130可以被置放以使得具有一或多個接觸墊131之一第一側邊或晶粒130之固定墊是相對於固定於散熱器120之晶粒130之一第二側邊。
第6圖係顯示一模鑄化合物134嵌入散熱器120之應用之剖面示意圖。模鑄化合物134可以是一可流動之化合物,其具有一高介電常數。在一些實施例之中,用於保持可模鑄化合物之一模具可以被使用去成型模鑄化合物134。在如此一實施例之中,一環氧樹脂或類似液體之模鑄化合物134可以有效地被使用去成型一模鑄底材800。此外,模鑄化合物134可以被固化於施加之後。舉例來說,模鑄化合物134可以是使用一觸媒之一環氧樹脂,並且是被固化於施加之後。再者,模鑄
化合物134可以透過一觸媒被固化於施加之後,舉例來說,經由紫外線曝光固化一模鑄化合物。
第7圖係顯示根據本發明之一些實施例之縮減之模鑄化合物142。模鑄化合物134可以受到一研磨步驟去從晶粒130、接觸墊131及中介窗122移除過多之材料。在如此一實施例之中,模鑄化合物134可以受到一化學機械研磨、一純機械研磨、化學蝕刻或另外適當之縮減製程。在一些實施例之中,導致之縮減之模鑄化合物142可以具有一上表面位於中介窗122、晶粒130及接觸墊131之上表面處或之下。因此,中介窗122、晶粒130及接觸墊131可以被暴露於縮減之模鑄化合物142之被研磨側邊處,如此一來,電氣接點可以被成型於中介窗122、晶粒130及接觸墊131之上。在一些實施例之中,研磨亦可以縮減中介窗122之高度至大約80μm與大約90μm之間,因而會導致了一高度對於寬度比例是介於大約1.1:1與大約1.3:1之間。
第8圖係顯示一模鑄底材800在分離於攜載底材102後之示意圖。攜載體110可以是分離於位於黏著層108處之模鑄底材800,以及任何殘留之黏著層108材料及任何基底薄膜層106或種晶層104材料可以藉由蝕刻或研磨而被移除掉。導致之模鑄底材800可以具有暴露於一第一側邊上之晶粒130以及設置於一第二側邊處之散熱器120。
第9圖係顯示根據本發明之具有一嵌入式散熱器120之一晶圓級組件900。模鑄底材800可以具有設置於一側邊上之一第一再分佈層901以及設置於一相對側邊上之一或多個
第二再分佈層902。在一些實施例之中,第一再分佈層901具有設置於一中間電介質904中之一或多個導線910,並且導線910是電性接觸於晶粒130上之接觸墊131。導線910可以被配置去提供一電性連接於晶粒130上之接觸墊131與複數個再分佈層接觸墊906之間。導線910可以從晶粒130上之接觸墊131扇出,如此一來,再分佈層接觸墊906可以具有比晶粒130大之一接合節距,其可以是適合於一球型陣列908或其他的封裝固定系統。雖然第一再分佈層901具有用於扇出及提供一電性連接於晶粒130上之接觸墊131與複數個再分佈層接觸墊906之間的複數個導線910時,但第一再分佈層901並不局限於如此之實施例。在一些實施例之中,第一再分佈層901亦可以具有連接一或多個中介窗122至複數個再分佈層接觸墊906之複數個導線910。在另一實施例之中,複數個導線910可以電性連接一中介窗122至另一中介窗122、一晶粒接觸墊或設置於模鑄底材800中之另一個晶粒或裝置。
此外,被成型大於晶粒130之一散熱器120之一實施例是被顯示。在一些實施例之中,散熱器120可以具有實質上與晶粒130相同之尺寸,因而會導致被需要去成型散熱器120之一降低之面積。散熱器120可以是實質上大於晶粒130,以提供一較大的散熱面積或吸熱能力。散熱器120可以是盡量大地被成型。
同樣地,設置於模鑄底材800之相對側邊上之第二再分佈層902可以具有一或多個設置於一中間電介質904中之一或多個導線910或其他的電氣材料。導線910可以內連接中介
窗122或可以連接中介窗122至一或多個其他裝置或設置於晶圓級組件900中之元件。
在一些實施例之中,第二再分佈層902可以被設置於散熱器120之上,以及在散熱器120上之區域可以包括有複數個導線910。因此,第二再分佈層902可以被設置於散熱器120之一部分之上,以及一導線910之一部分亦可以被設置於散熱器120之上。如此一實施例可以被運用於複數個元件或設置於散熱器120之相對側邊上之複數個中介窗122是連接於彼此之情況之中。
因此,在一些實施例之中,具有一嵌入式散熱器120之一晶圓級組件900可以是一裝置,其具有一模鑄底材800以及設置於底材中及具有複數個接觸墊131之一晶粒130,其中,一散熱器120可以進一步是與晶粒130熱接觸。此外,散熱器120可以是設置於晶粒130之一第二側邊處以及是用於轉移來自於晶粒130之熱量。在一些實施例之中,至少一中介窗122可以是被設置於模鑄底材800之中,並且是從模鑄底材800之第一側邊延伸至模鑄底材800之第二側邊。
在一些實施例之中,一第一再分佈層901可以被設置於模鑄底材800之第一側邊之上,並且第一再分佈層901可以具有複數個再分佈層接觸墊906以及至少一導線910,其中,導線910是電性連接位於晶粒130上之複數個接觸墊131至複數個再分佈層接觸墊906。再者,再分佈層接觸墊906可以具有大於接觸墊131之接合節距之一接合節距。一第二再分佈層902亦可以被設置於模鑄底材800之上,並且可以具有與中介窗122接觸
之複數個導線。第二再分佈層902是被設置於散熱器120之上,並且第二再分佈層902是覆蓋散熱器120。此外,至少一導線910之一部分可以是被設置於散熱器120之上。在一些實施例之中,一晶粒附著層132是設置於晶粒130之第二側邊與散熱器120之間以及接觸晶粒130之第二側邊及散熱器120。晶粒附著層132可以選擇性地是一晶粒附著薄膜,並且晶粒附著層132可以接合散熱器120及晶粒130。
第10圖係顯示根據本發明之另一實施例之具有一嵌入式散熱器120之一晶圓級組件1000。在一些實施例之中,第二再分佈層902可以被成型去具有一熱暴露開口1002。此可以允許較大之氣流於散熱器120之上,因而可導致更為有效率之熱輻射,進而可允許散熱器120散出過多之熱量至周圍或外部環境之中。在如此之實施例之中,位於第二再分佈層902中之導線910可以繞著熱暴露開口1002被佈置。在一些實施例之中,熱暴露開口1002可以在中間電介質904之產生過程中被成型。在其他實施例之中,在中間電介質904被產生之後,熱暴露開口1002可以被蝕刻或產生於散熱器120之上。
在一些實施例之中,第二再分佈層902可以只覆蓋散熱器120之一部分。在其他實施例之中,第二再分佈層902可以完全地避免散熱器120之表面去暴露散熱器120之一整個表面。因此,大於晶粒130之一散熱器120可以被成型,其中,第二再分佈層902之一部分只覆蓋散熱器120之一部分,以及散熱器120之一部分是被暴露。在如此一實施例之中,一或多個導線910可以被佈置通過位於散熱器120上之第二再分佈層902,
以允許散熱器120在不干涉第二再分佈層902及導線910之配置的情形下被成型。
第11圖係顯示用於形成具有一嵌入式散熱器120之一晶圓級組件900之一方法1100之流程圖。一攜載底材102可以藉由提供一攜載體110及施加一黏著層108於攜載體110之上而被成型,如方塊1102所示。一基底薄膜層106可以選擇性地被施加於黏著層108之上,如方塊1104所示。一種晶層104可以選擇性地被施加於基底薄膜層106之上,如方塊1106所示。具有一散熱器開口118之一被圖刻光罩114可以藉由施加及圖刻光罩層112而被成型於攜載底材102之上,如方塊1108所示。一散熱器120及複數個中介窗122可以被成型於被圖刻光罩114之中,如方塊1110所示。一晶粒附著層132(其可以選擇性地是一晶粒附著薄膜)可以被施加於散熱器120之上,如方塊1112所示。具有複數個接觸墊131設置於晶粒130之一第二側邊上之一晶粒130可以經由一第一側邊被固定於晶粒附著層132之上,如方塊1114所示。一模鑄化合物142可以被施加於晶粒130及散熱器120之上,以產生一模鑄底材800,如方塊1116所示,如此一來,晶粒130之複數個接觸墊131是暴露於模鑄底材800之第一側邊以及散熱器120是設置於模鑄底材800之第二側邊處。攜載體110可以是接著分離於晶圓級組件900。複數個中介窗122及散熱器120可以是被成型於相同之時間,使用一電鍍製程或另外適當之金屬沉積製程。
在一些實施例之中,晶圓級組件900之產生方法可以進一步包括有成型一第一再分佈層901於模鑄底材800之第
一側邊處,如方塊1120所示。第一再分佈層901可以具有複數個再分佈層接觸墊906以及複數個導線910,以及每一導線910係提供一電性連接於一再分佈層接觸墊906與晶粒130之一接觸墊之間。在額外的實施例之中,再分佈層接觸墊906可以具有大於晶粒130之接觸墊131之接合節距之一接合節距。一第二再分佈層902亦可以被成型於模鑄底材800之第二側邊之上,如方塊1120所示,並且第二再分佈層902可以覆蓋散熱器120之至少一部分以及具有至少一導線910電性接觸至少一中介窗122。
雖然本發明已以較佳實施例揭露於上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
120‧‧‧散熱器
122‧‧‧中介窗
130‧‧‧晶粒
800‧‧‧模鑄底材
900‧‧‧晶圓級組件
901‧‧‧第一再分佈層
902‧‧‧第二再分佈層
904‧‧‧中間電介質
906‧‧‧再分佈層接觸墊
908‧‧‧球型陣列
910‧‧‧導線
Claims (10)
- 一種半導體裝置,包括:一晶粒,設置於一底材之內,並且位於該底材之一第一側邊處,其中,該晶粒具有複數個接觸墊;以及一散熱器,設置於該底材之內,並且位於該底材之一第二側邊處,其中,該散熱器係與該晶粒熱接觸。
- 如申請專利範圍第1項所述之半導體裝置,更包括至少一中介窗,係設置於該底材之中,並且係從該底材之該第一側邊延伸至該底材之該第二側邊。
- 如申請專利範圍第2項所述之半導體裝置,更包括一第一再分佈層,係位於該底材之該第一側邊處,其中,該第一再分佈層具有複數個再分佈層接觸墊以及至少一導線,該導線係電性連接位於該晶粒上之一接觸墊於該等再分佈層接觸墊之至少一個,以及該等再分佈層接觸墊具有大於設置於該晶粒上之該等接觸墊之接合節距之一接合節距。
- 如申請專利範圍第2項所述之半導體裝置,更包括一第二再分佈層,係位於該底材之該第二側邊處,其中,該第二再分佈層具有至少一導線,並且係覆蓋該散熱器,該至少一導線之一部分係設置於該散熱器之上,以及該第二再分佈層係設置於該散熱器之一部分處,以及該第二再分佈層具有暴露該散熱器之一表面之一部分之一熱暴露開口。
- 如申請專利範圍第1項所述之半導體裝置,更包括一晶粒附著層,係設置於該底材之該第二側邊與該散熱器之間以及係與該底材之該第二側邊及該散熱器接觸。
- 一種半導體裝置,包括:一晶粒,設置於一底材之內,並且具有複數個接觸墊,其中,該等接觸墊係設置鄰接於該底材之一第一側邊;一晶粒附著層,設置鄰接於該底材之一第二側邊;一散熱器,嵌入於該底材之內,並且設置於該晶粒附著層之上;一第一再分佈層,設置於該晶粒之該等接觸墊之上;複數個再分佈層接觸墊,設置於該第一再分佈層之內;以及至少一導線,設置於該第一再分佈層之內,並且電性連接位於該底材之該第一側邊上之一接觸墊於該等再分佈層接觸墊之至少一個,其中,該等再分佈層接觸墊具有大於設置於該底材之該第一側邊上之該等接觸墊之接合節距之一接合節距。
- 一種成型一半導體裝置之方法,包括:成型一被圖刻光罩於一攜載底材之上,其中,該被圖刻光罩具有一散熱器開口;成型一散熱器於位於該散熱器開口中之該攜載底材之上;固定一晶粒於該散熱器之上,其中,該晶粒係與該散熱器熱接觸;藉由應用一模鑄化合物成型一模鑄底材於該晶粒及該散熱器之上,其中,該晶粒係設置於該模鑄底材之一第一側邊處,以及該散熱器係設置於該模鑄底材之一第二側邊;成型至少一中介窗開口於該被圖刻光罩之中;成型一中介窗於該中介窗開口之中; 成型一第一再分佈層於該模鑄底材之該第一側邊處,其中,該第一再分佈層具有複數個再分佈層接觸墊以及複數個導線,以及每一導線係提供一電性連接於一再分佈層接觸墊與該晶粒之一接觸墊之間;以及成型一第二再分佈層於該模鑄底材之該第二側邊處以及覆蓋該散熱器之至少一部分,其中,該第二再分佈層具有至少一導線,以及該至少一導線係電性接觸至少一中介窗。
- 如申請專利範圍第7項所述之成型一半導體裝置之方法,其中,成型一被圖刻光罩於一攜載底材之上之步驟包括:提供一攜載體;施加一黏著層於該攜載體之上;以及施加一基底薄膜層於該黏著層之上。
- 如申請專利範圍第8項所述之成型一半導體裝置之方法,其中,成型一被圖刻光罩於一攜載底材之上之步驟更包括:施加一種晶層於該基底薄膜層之上。
- 如申請專利範圍第7項所述之成型一半導體裝置之方法,更包括:提供一開口於暴露該散熱器之一部分之該第二再分佈層之中。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI585920B (zh) * | 2014-11-26 | 2017-06-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及製造方法 |
TWI640067B (zh) * | 2016-01-26 | 2018-11-01 | 珠海越亞封裝基板技術股份有限公司 | New embedded package |
US10163861B2 (en) | 2014-07-01 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company | Semiconductor package for thermal dissipation |
US10269685B2 (en) | 2013-03-06 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for package-on-package devices |
US10347612B2 (en) | 2014-03-07 | 2019-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solution for reducing poor contact in InFO package |
TWI800977B (zh) * | 2020-11-11 | 2023-05-01 | 南韓商Nepes股份有限公司 | 半導體封裝以及其製造方法 |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9165878B2 (en) * | 2013-03-14 | 2015-10-20 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
US9655253B2 (en) * | 2013-07-25 | 2017-05-16 | Cyntec Co., Ltd. | Method of fabrication of encapsulated electronics devices mounted on a redistribution layer |
DE102014202220B3 (de) | 2013-12-03 | 2015-05-13 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung eines Deckelsubstrats und gehäustes strahlungsemittierendes Bauelement |
US10971476B2 (en) * | 2014-02-18 | 2021-04-06 | Qualcomm Incorporated | Bottom package with metal post interconnections |
US9355983B1 (en) * | 2014-06-27 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer structure and method of manufacture thereof |
US9691726B2 (en) * | 2014-07-08 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming fan-out package structure |
CN106971993B (zh) | 2016-01-14 | 2021-10-15 | 三星电子株式会社 | 半导体封装件 |
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CN107871732A (zh) * | 2016-09-23 | 2018-04-03 | 深圳市中兴微电子技术有限公司 | 封装结构 |
KR102527409B1 (ko) | 2016-12-19 | 2023-05-02 | 에스케이하이닉스 주식회사 | 칩들 사이에 열 전달 블록을 배치한 반도체 패키지 및 제조 방법 |
US10347574B2 (en) * | 2017-09-28 | 2019-07-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out packages |
US10643919B2 (en) | 2017-11-08 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
US10566261B2 (en) | 2017-11-15 | 2020-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out packages with embedded heat dissipation structure |
KR20190124892A (ko) * | 2018-04-27 | 2019-11-06 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10510595B2 (en) * | 2018-04-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out packages and methods of forming the same |
US10490479B1 (en) * | 2018-06-25 | 2019-11-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packaging of semiconductor device with antenna and heat spreader |
US10573618B1 (en) * | 2018-07-31 | 2020-02-25 | Delta Electronics, Inc. | Package structures and methods for fabricating the same |
KR102164795B1 (ko) * | 2018-09-06 | 2020-10-13 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
EP3629682A1 (en) * | 2018-09-25 | 2020-04-01 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded component having pads connected in different wiring layers |
US10741534B2 (en) | 2018-09-28 | 2020-08-11 | Intel Corporation | Multi-die microelectronic device with integral heat spreader |
TWI703685B (zh) | 2018-11-21 | 2020-09-01 | 欣興電子股份有限公司 | 發光二極體封裝及其製作方法 |
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KR102584991B1 (ko) * | 2019-06-14 | 2023-10-05 | 삼성전기주식회사 | 반도체 패키지 |
EP3772087A1 (de) * | 2019-07-30 | 2021-02-03 | Siemens Aktiengesellschaft | Montage einer elektronischen baugruppe |
CN110729273B (zh) * | 2019-09-24 | 2021-10-01 | 浙江臻镭科技股份有限公司 | 一种芯片嵌入式三维异构互联结构及其制作方法 |
TWI709218B (zh) * | 2019-12-30 | 2020-11-01 | 欣興電子股份有限公司 | 晶片封裝結構及其製作方法 |
US11145610B2 (en) * | 2019-12-30 | 2021-10-12 | Unimicron Technology Corp. | Chip package structure having at least one chip and at least one thermally conductive element and manufacturing method thereof |
KR20210087751A (ko) | 2020-01-03 | 2021-07-13 | 삼성전자주식회사 | 반도체 패키지 |
CN113161298B (zh) * | 2020-01-07 | 2024-06-11 | 欣兴电子股份有限公司 | 芯片封装结构及其制作方法 |
KR20210099244A (ko) * | 2020-02-03 | 2021-08-12 | 삼성전자주식회사 | 반도체 장치 및 그의 제조 방법 |
EP3876683A1 (en) | 2020-03-05 | 2021-09-08 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Heat removal mechanism for stack-based electronic device with process control component and processing components |
US20220310529A1 (en) * | 2020-06-16 | 2022-09-29 | Zhuhai Access Semiconductor Co., Ltd | Heat dissipation-electromagnetic shielding embedded packaging structure, manufacturing method thereof, and substrate |
US11527518B2 (en) * | 2020-07-27 | 2022-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat dissipation in semiconductor packages and methods of forming same |
CN112164677A (zh) * | 2020-08-25 | 2021-01-01 | 珠海越亚半导体股份有限公司 | 一种线路预排布散热嵌埋封装结构及其制造方法 |
KR20220042705A (ko) | 2020-09-28 | 2022-04-05 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
KR20220043519A (ko) * | 2020-09-29 | 2022-04-05 | 삼성전자주식회사 | 열 발산층을 구비한 반도체 패키지 |
CN115020369A (zh) * | 2021-03-03 | 2022-09-06 | 华为技术有限公司 | 电路板组件及其制造方法和电子设备 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6265771B1 (en) | 1999-01-27 | 2001-07-24 | International Business Machines Corporation | Dual chip with heat sink |
US6075700A (en) * | 1999-02-02 | 2000-06-13 | Compaq Computer Corporation | Method and system for controlling radio frequency radiation in microelectronic packages using heat dissipation structures |
EP1346411A2 (en) * | 2000-12-01 | 2003-09-24 | Broadcom Corporation | Thermally and electrically enhanced ball grid array packaging |
US6905914B1 (en) * | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7868472B2 (en) | 2004-04-08 | 2011-01-11 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Thermal dissipation in integrated circuit systems |
US7253089B2 (en) * | 2004-06-14 | 2007-08-07 | Micron Technology, Inc. | Microfeature devices and methods for manufacturing microfeature devices |
US7271034B2 (en) * | 2004-06-15 | 2007-09-18 | International Business Machines Corporation | Semiconductor device with a high thermal dissipation efficiency |
TWI229433B (en) * | 2004-07-02 | 2005-03-11 | Phoenix Prec Technology Corp | Direct connection multi-chip semiconductor element structure |
US7361986B2 (en) | 2004-12-01 | 2008-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat stud for stacked chip package |
TWI269423B (en) * | 2005-02-02 | 2006-12-21 | Phoenix Prec Technology Corp | Substrate assembly with direct electrical connection as a semiconductor package |
TWI283050B (en) * | 2005-02-04 | 2007-06-21 | Phoenix Prec Technology Corp | Substrate structure embedded method with semiconductor chip and the method for making the same |
JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
CN102646628B (zh) * | 2006-11-06 | 2014-08-06 | 瑞萨电子株式会社 | 用于制造半导体装置的方法 |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
TWI353047B (en) * | 2006-12-28 | 2011-11-21 | Siliconware Precision Industries Co Ltd | Heat-dissipating-type semiconductor package |
KR100843236B1 (ko) * | 2007-02-06 | 2008-07-03 | 삼성전자주식회사 | 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법 |
US20080237828A1 (en) * | 2007-03-30 | 2008-10-02 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same |
US8217511B2 (en) * | 2007-07-31 | 2012-07-10 | Freescale Semiconductor, Inc. | Redistributed chip packaging with thermal contact to device backside |
TWI357135B (en) * | 2008-05-29 | 2012-01-21 | Ind Tech Res Inst | Chip package structure and manufacturing method th |
US7977161B2 (en) * | 2008-11-17 | 2011-07-12 | Infineon Technologies Ag | Method of manufacturing a semiconductor package using a carrier |
CN102959811B (zh) * | 2009-12-19 | 2016-06-29 | 三流明公司 | 用于组合用于数字输出的激光器阵列的***和方法 |
US8349658B2 (en) | 2010-05-26 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe |
US8097490B1 (en) * | 2010-08-27 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die |
US8531032B2 (en) * | 2011-09-02 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced structure for multi-chip device |
-
2012
- 2012-09-20 US US13/623,474 patent/US9735087B2/en active Active
-
2013
- 2013-05-03 CN CN201310161095.0A patent/CN103681541B/zh active Active
- 2013-08-19 TW TW102129620A patent/TWI609464B/zh active
-
2017
- 2017-07-03 US US15/641,116 patent/US10177073B2/en active Active
-
2018
- 2018-12-24 US US16/231,783 patent/US11101192B2/en active Active
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11037861B2 (en) | 2013-03-06 | 2021-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for package-on-package devices |
US10515875B2 (en) | 2013-03-06 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for package-on-package devices |
US10269685B2 (en) | 2013-03-06 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for package-on-package devices |
US10347612B2 (en) | 2014-03-07 | 2019-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solution for reducing poor contact in InFO package |
US10861835B2 (en) | 2014-03-07 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solution for reducing poor contact in InFO package |
US10163861B2 (en) | 2014-07-01 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company | Semiconductor package for thermal dissipation |
US10811389B2 (en) | 2014-07-01 | 2020-10-20 | Taiwan Semiconductor Manufacturing Company | Semiconductor package for thermal dissipation |
US11594520B2 (en) | 2014-07-01 | 2023-02-28 | Taiwan Semiconductor Manufacturing Company | Semiconductor package for thermal dissipation |
US11804475B2 (en) | 2014-07-01 | 2023-10-31 | Taiwan Semiconductor Manufacturing Company | Semiconductor package for thermal dissipation |
US10515937B2 (en) | 2014-11-26 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
TWI585920B (zh) * | 2014-11-26 | 2017-06-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及製造方法 |
US10008485B2 (en) | 2014-11-26 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US11056471B2 (en) | 2014-11-26 | 2021-07-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
TWI640067B (zh) * | 2016-01-26 | 2018-11-01 | 珠海越亞封裝基板技術股份有限公司 | New embedded package |
TWI800977B (zh) * | 2020-11-11 | 2023-05-01 | 南韓商Nepes股份有限公司 | 半導體封裝以及其製造方法 |
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US9735087B2 (en) | 2017-08-15 |
CN103681541B (zh) | 2017-06-16 |
CN103681541A (zh) | 2014-03-26 |
US10177073B2 (en) | 2019-01-08 |
US11101192B2 (en) | 2021-08-24 |
US20170301608A1 (en) | 2017-10-19 |
US20190148264A1 (en) | 2019-05-16 |
US20140077394A1 (en) | 2014-03-20 |
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