1282160 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種整合半導體晶片之電路板結構及 其製法，尤指一種可在電路板中整合有半導體晶片之結構 及其製作方式。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其中球 < 柵陣列式（Ball grid array, BGA)為一種先進的半導體封裝 技術，其特點在於採用一基板來安置半導體晶片，並利用 自動對位（Self-alignment)技術以於該基板背面植置複數個 > 成栅狀陣列排列之錫球（Solder ball)，使相同單位面積之半 _ 導體晶片承載件上可以容納更多輸入/輸出連接端（I/O connection)以符合高度集積化（Integration)之半導體晶片 所需，以藉由此些錫球將整個封裝單元銲結並電性連接至 外部之印刷電路板。 < 另自IBM公司在1960年早期引入覆晶封裝（Flip chip package)技術以來，相較於打線（Wire bond)技術，覆晶技 術之特徵在於半導體晶片與基板間的電性連接係透過銲錫 凸塊而非一般之金線。而該種覆晶技術之優點在於該技術 可提高封裝密度以降低封裝構成尺寸，同時，該種覆晶技 術不需使用長度較長之金屬導線，故可提高電性性能，以 滿足高密度、高速度之半導體裝置需求。 5 17814(修正本) 1 * . 1282160 在現行覆晶技術中，半導體積體電路（IC)晶片的表面 -置有電極知墊（Eiectr〇(je pads)，而供承載晶片之電路 板上亦具有相對應的接觸銲墊，在該晶片以及電路板之間 可以適當地設置銲錫凸塊或其他導電黏著材料，使該晶片 $以電性接觸面朝下的方式設置於該電路板上，其中，該 、干錫凸塊或‘電黏著材料提供該晶片以及電路板間的電性 輸入/輸出（I/O)以及機械性的連接。 明芩閱弟1A及1B圖，係說明一種習知的覆晶構成， 圖所不數個金屬凸塊11係形成於晶片13之電極銲墊 12上’以及數個由銲料所製成的預銲錫凸塊η係形成於 、=板之接觸料15上。奴以使該預銲錫凸塊14 、谷融之迴#溫度條件下，藉由將預銲錫凸塊Μ迴銲至相對 :王屬凸塊11即可形成鋅錫接17。就銲錫凸塊鲜錫接 門的n bUmPjGmt)^ S ’可進—步在該晶片以及該電路板 間的間隊中殖入: 】 ^ ，、有機底膠18，以抑制該晶片13以及該電 H 熱膨脹差並降低該_接的應力。 @ g $ f界主要係藉由模板印刷技術伽心 technology)在電路板接 銲錫凸塊H Μ 沈積鲜錫材料以形成預 電腦等各^ ’貫際操作上，由於現今通訊、網路及 封裳（(L>/Ch密度與多接腳化特性的BGA、晶片尺寸 chip m d ηΓ ⑽ PaCkage)與多晶片模組（MCM，Multi P odule)專封裝件已日漸成為 〜 與微處理器、晶片植、給 市琢上的主/瓜，亚兩 、、、、日圖日日片等高效能晶片搭配，以發 6 17814(修正本） 1282160 揮更高速之運算功能，惟該些結構勢必縮小線路寬度與# 塾尺寸，當録墊間隙持續縮減時，因為該鲜塾間形成有: 緣保護層，將遮蔽住部分之銲墊面積，致使外露出該嗜緣巴 保護層之銲墊尺寸更義小，不僅造錢續形成預鮮錫凸 塊之對位問題的產生，同時亦因該絕緣保護層敷設所佔之 空間與其形成之高度影響’使模板印刷技術巾之模板開孔 尺寸要求縮小，銲錫材料亦不易沈積在該接觸銲墊上Y 致模板印刷技術變得良率過低而不可彳，況且模板之費用 係因銲塾尺寸、間距之料而增加，致使製程費之增加； 此外，隨著銲墊間隙的縮減，絕緣保護層對於該電路板本 身的接觸面積則變得更小，而使該絕緣保護層對於該電路 板本身的黏著力有減弱的趨勢。 另外，於覆晶式半導體裝置之製程中，同樣須在完成 晶圓積體電路製程後，於該晶圓内晶片之電極銲墊上形成 一銲塊底部金屬化（Under bump metallurgy，UBM)結構層 以供承載金屬凸塊，再進行切單作業以將該晶圓切割形成 複數個晶片，之後將該覆晶式半導體晶片接置並電性連接 至一電路板上。其中該UBM結構層與金屬凸塊之製程首 先於該半導體晶圓表面形成一絕緣保護層（Passivati〇n layer)，並曝露出電極銲墊位置，接著於該電極銲墊上利用 濺鍍及電鍍形成一包含有多層金屬之UBM結構層；之後 將一拒銲層設置於該絕緣保護層上，且該拒銲層預設有複 數個開口’用以曝露出該UBM結構層；然後進行一銲料 塗佈製程，用以將例如為錫鉛合金（Sn/Pb)之銲料，透過該 17814(修正本) 7 1282160 * « 拒銲層開口以利用網版印刷之技術而塗佈至該Ubm結構 層，再進行回銲（Reflow)製程以將銲料銲結至該UBM結構 層上，之後將該拒銲層移除，並進行第二次回銲程序以將 該銲料圓球化，以在半導體晶圓上形成金屬凸塊，以藉由 該金屬凸塊提供半導體晶片與電路板間之電性導接。 因此，對於覆晶式半導體裝置而言，需在半導體晶片 與對應接置之電路板上各自形成有對應之電性連接單元 (如金屬凸塊及預銲錫凸塊），不僅提高製程步驟與成本， 同時伴隨製程中信賴性風險之增加。 另無論是採用覆晶式封裝製程亦或打線式封裝萝程， 該電路板之製程與半導體晶片之封裝形式，均需採用不同 :4程機具與製程步驟，且其製程繁靖，製造成本高；再 進行觀封膠製程時，係將完成佈設晶片之電路板 由、，封裝柄具中，俾供—環氧樹脂(Epoxy)材料注入模具 ^成用以包覆該晶片與銲線之封裝膠體，然而，於實 二Γ二Γ莫具由於受限於半導體封裝件之設計，故其 :二St置勢必有所差異而造成無法緊密夹固等 路板夺面:t树月曰材料時’容易導致封裝膠體溢膠至該電 非但降低該半導體封裝件之表面平整产 Γ ΓΓ能污染該電路板上後續欲植置錫球:薛塾位 +導體封裝件之生產品質及產品信賴度。嚴重，…乂 …卜 叙半導體裝置之製程，係首先由S曰片是都杜 以造業者（例如電路板製造商）生產適用於半導體s曰裝置之晶 Π8]4(修正本） 8 1282160 之後:、再將該些晶片承载件交由半導體封裝業 日日、模壓、以及植球等製程，最後，方可完成客 =所需之電子功能之半導體裝置。其間涉及不同製程業 此λ包iff片承載件製造業者與半導體封農業者），因 且，、二二衣化過程中不僅步驟繁瑣且界面整合不易，況 屏品右客戶端右人進行變更功能設計時，其牽涉變更與整合 π更疋硬雜’亦不符合需求變更彈性與經濟效益。 【發明内容】 整合曰只^ 路板結構及其製法，俾同時 :曰山曰7載件之製造與半導體封裝技術之製程，以提供 面整需求彈性’同時得以簡化半導體業者製程與界 板結:提供:種整合半導體晶片之電路 所導致之各·題。$知半導體晶片與電路板電性導接 本發明之又—目的係提供一 板結構及其製法，, 。+蜍體曰曰片之電路 ^ ^猎以間化該電路板與半導體晶片之整人 形式，以降低製程步驟與成本。 5之正。 板結:;二之:'目的係提供一種整合半導趙晶片之電路 之溢膠問題,導趙封裝作業中所產生 賴度。 +導料置之生產品質及產品信 為達上揭及其它目的，本發明之整合半導體晶片之電 17814(修正本) 9 1282160 * . 路板製法，主要係提供一支承板’該支承板可為一般之承 載板或電路板，且該支承板形成至少一貫穿表面之開孔， 俾於該開孔中收納至少一具有複數電性連接端之半導體晶 片；於該支承板上形成第一絕緣層，並令第—絕緣層於對 應該電性連接端之處形成第一開口，以露出該電性連接 端；於該第一開口中形成電性導接至該電性連接端之導電 結構，其中，該導電結構係為一金屬凸塊且其高度不 高於該第一開口；在該第一絕緣層上形成第二絕緣層 並於該第二絕緣層中形成複數第二開口，由部分第二開口 中露出該導電結構；以及於該第二開口中形成線路結構。 其中該導電結構可為-包含有鎳、金、銅等金屬構成之金 屬凸塊，係可用以提供晶片緩衝與阻障作用，以及後續線 路與晶片電性連接端間良好接著。 、 透過前述製冑，本發明亦揭露出一種整合 之電路板結構，主要係包括有一支承板，該支承板可^曰一 般之承载板或電路板，且該支承板形成有至少一貫穿開 孔；至少-具有複數個電性連接端之半導體晶片，係收納 於該開孔中；-第-絕緣層，係形成於該支承板上且涵莫 該開孔，且該第一絕緣層中具有複數個第一開口，該第： 開口形成有一導電結構以電性導接至該晶片之電性連接 端，其中，該導電結構係為一金屬凸塊且其高度不高 於該弟一開口，·以及一第二絕緣層，係形成於該第一絕 緣層上，且該第二絕緣層中具有複數個第二開口，該第二 開口形成有-導電結構以電性連接至該導電結構之圖案化 17814(修正本) 10 1282160 線路結構。其中該導電結構可選自一包含有鎳、金、銅等 =組之-所構成之金屬凸塊，係可用以提供晶片緩衝與阻 作用，以及後績線路與晶片電性連接端間良好接著。 因此，透過本發明之整合半導體晶片之電路板結構及 其製法’主要係可預先提供至少—表面形成有電性連接端 之半導體晶片，並將其收納於一形成有開孔之支承板中， 俾可縮短半導體裝置之整體厚度，以達輕薄短小目的，·此 =，本發明於該收納有半導體晶片之支承板上形成有第— 絕緣層，並於該第—絕緣層中設置有電性連接至晶片電性 連接端之導電結構’以使晶#之電性連接端外拉至外部， 俾可供後續在該第—絕緣層上形成第二絕緣層時，得以藉 由形成在該第二絕緣層中之線路結構，經過該導電結構力曰口 以電性導接至該晶片之電性連接端，藉此，即可結合晶片 承載件之製造與半導體封裝技術之製程，俾提供較 大需求彈性以及簡化半導體業者製程與界面協調問題，同 時避免習知半㈣封裝製程巾之電性導接與模壓等。 【實施方式】 ' 知徵及功效，能更進 為使本發明之目的 ’ "/八 此又疋一芡的際朝 兵認同1配合詳細揭露及圖式詳加說明如后。當然， 發明可以多種形式實施之，以下所述㈣本發明之較佳實 施例，而非用以限制本發明之範圍，合先敛日月。 、 請參閱第2A至2G圖，係為本發明之整合半導體曰 之電路板製法之剖面示意圖。 如第2A圖所示，首先提供—支承板22,該支承板22 17814(修正本) 11 12821601282160 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure for integrating a semiconductor wafer and a method of fabricating the same, and more particularly to a structure in which a semiconductor wafer can be integrated in a circuit board and a manufacturing method thereof. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, in which ball <Ball grid array (BGA) is an advanced semiconductor packaging technology, The utility model is characterized in that a semiconductor substrate is arranged by using a substrate, and a plurality of solder balls arranged in a grid array are arranged on the back surface of the substrate by using a self-alignment technique to make the same unit area. The semi-conductor wafer carrier can accommodate more I/O connections to meet the requirements of a highly integrated semiconductor wafer to solder the entire package unit with the solder balls. Electrically connected to an external printed circuit board. < Since IBM introduced the Flip chip package technology in the early 1960s, the flip chip technology is characterized by the fact that the electrical connection between the semiconductor wafer and the substrate is transmitted through the solder. Bumps instead of the usual gold wire. The advantage of this flip chip technology is that the technology can increase the package density to reduce the package size. At the same time, the flip chip technology does not need to use a long metal wire, so the electrical performance can be improved to meet high density, High speed semiconductor device requirements. 5 17814 (Revised) 1 * . 1282160 In the current flip chip technology, the surface of the semiconductor integrated circuit (IC) chip is provided with an electrode pad (Eiectr〇(je pads), and the circuit board for carrying the chip is also Having a corresponding contact pad, a solder bump or other conductive adhesive material may be appropriately disposed between the wafer and the circuit board, so that the wafer is disposed on the circuit board with an electrical contact surface facing downward, wherein The dry tin bump or 'electro-adhesive material provides electrical input/output (I/O) and mechanical connection between the chip and the circuit board. Alum read 1A and 1B to illustrate a conventional The flip chip is formed, in which a plurality of metal bumps 11 are formed on the electrode pads 12 of the wafer 13 and a plurality of pre-solder bumps η made of solder are formed on the contact material 15 of the board. In the condition of temperature, the pre-solder bumps 14 are back-welded to the opposite: the king-shaped bumps 11 to form a zinc-tin junction 17. The solder bumps are formed. n bUmPjGmt) ^ S ' can be stepped in between the wafer and the circuit board In the squadron, 】 ^ , an organic primer 18 is used to suppress the difference in thermal expansion between the wafer 13 and the electric H and to reduce the stress of the splicing. The @g $ f boundary is mainly based on the stencil printing technology, the solder bumps H Μ deposited on the board to form a pre-computer, etc., due to the current communication, network and Singer (B>, density of BGA, chip size chip md ηΓ (10) PaCkage) and multi-chip module (MCM, Multi P odule) package has become increasingly ~ with microprocessor, chip Planting, giving the high-performance chips such as the main/guar, the Asian, the Japanese, the Japanese, the Japanese, the Japanese, and the Japanese, and the high-speed computing function of the 6 17814 (Revised) 1282160, but these structures are bound to shrink Line width and #塾 size, when the recording pad gap is continuously reduced, because the fresh enamel is formed with: edge protection layer, which will cover part of the pad area, so that the size of the pad which exposes the fascia protective layer is more Yi Xiao, not only created the problem of the alignment of the pre-preserved tin bumps, but also because of the high impact of the space occupied by the insulating protective layer and the formation of the stencil printing technology. , solder material is not The stencil printing technique deposited on the contact pad becomes too low and unsatisfactory, and the cost of the template is increased due to the size of the solder bump and the pitch, resulting in an increase in the process cost; With the reduction, the contact area of the insulating protective layer to the circuit board itself becomes smaller, and the adhesion of the insulating protective layer to the circuit board itself tends to be weakened. In addition, in the process of the flip chip semiconductor device After the completion of the wafer integrated circuit process, a solder bump metallurgy (UBM) structural layer is formed on the electrode pads of the wafer in the wafer for carrying metal bumps, and then singulation is performed. Working to cut the wafer into a plurality of wafers, and then attaching and electrically connecting the flip-chip semiconductor wafer to a circuit board, wherein the UBM structural layer and the metal bumps are processed first on the surface of the semiconductor wafer Forming an insulating protective layer (Passivati〇n layer) and exposing the position of the electrode pad, and then forming a multi-layer metal by sputtering and electroplating on the electrode pad a UBM structural layer; a solder resist layer is then disposed on the insulating protective layer, and the solder resist layer is pre-set with a plurality of openings 'to expose the UBM structural layer; and then a solder coating process is performed for For example, tin-lead alloy (Sn/Pb) solder, through the 17814 (Revised) 7 1282160 * « Solder mask opening to the Ubm structural layer using screen printing technology, and then reflow (Reflow a process for soldering the solder to the UBM structural layer, then removing the solder resist layer, and performing a second reflow process to spheroidize the solder to form metal bumps on the semiconductor wafer to The metal bumps provide electrical connection between the semiconductor wafer and the circuit board. Therefore, for a flip-chip type semiconductor device, a corresponding electrical connection unit (such as a metal bump and a pre-solder bump) is formed on each of the semiconductor wafer and the correspondingly connected circuit board, which not only improves the process steps and costs. , accompanied by an increase in the risk of reliability in the process. In addition, whether it is a flip-chip package process or a wire-wound package, the process of the board and the package form of the semiconductor chip are different: the 4-step machine tool and the process steps, and the process is complicated and the manufacturing cost is high. When the encapsulation process is completed, the circuit board for laying the wafer is completed, and the epoxy resin (Epoxy) material is injected into the mold to encapsulate the wafer and the wire bonding package. Colloid, however, is limited by the design of the semiconductor package, so its two: St will have to be different, resulting in the inability to tightly clamp the board to win the surface: t tree 'Easy to cause the encapsulation gel to overflow to the electricity, but to reduce the surface of the semiconductor package. It can contaminate the subsequent solder ball on the board: the production quality and reliability of the product. Seriously, ... 乂 卜 卜 半导体 半导体 半导体 半导体 半导体 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜: The wafer carrier is then transferred to the semiconductor packaging industry for day-to-day, molding, and ball-planting processes, and finally, the semiconductor device of the electronic function required by the customer can be completed. In the process, the manufacturer of the λ-package 144-sheet carrier and the semiconductor-sealed farmer are involved in different process industries. Because of the cumbersome steps and the interface integration, the right-hand side of the right-hand side of the screen is changed. At the time of design, it involves changes and integrations that are more ambiguous and do not meet the elasticity and economic benefits of demand changes. [Invention] The integration of the 路 路 路 结构 路 及其 及其 及其 及其 路 路 路 路 路 路 路 路 路 路 路 路 路 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载 载: Provided: various problems caused by the integration of circuits of semiconductor wafers. It is a further object of the present invention to provide a board structure and a method of manufacturing the same. + The circuit of the 曰曰 曰曰 ^ ^ ^ Hunting to intervene the board and the semiconductor chip as a whole person to reduce the process steps and costs. 5 is positive. Knot: 2: 'The purpose is to provide an overflow problem in the circuit of the integrated semiconductor wafer, which is the result of the package operation. +The production quality and product information of the guide material are for the purpose of lifting and other purposes, the integrated semiconductor wafer of the present invention is 17814 (amendment) 9 1282160 *. The method of manufacturing the road plate mainly provides a support plate. a general carrier board or a circuit board, and the support board forms at least one opening through the surface, and the semiconductor hole accommodates at least one semiconductor wafer having a plurality of electrical connection ends; forming a first insulation on the support board And forming a first opening at a portion corresponding to the electrical connection end to expose the electrical connection end; forming a conductive structure electrically connected to the electrical connection end in the first opening Wherein the conductive structure is a metal bump and has a height not higher than the first opening; forming a second insulating layer on the first insulating layer and forming a plurality of second openings in the second insulating layer, The conductive structure is exposed in a portion of the second opening; and a wiring structure is formed in the second opening. The conductive structure may be a metal bump comprising a metal such as nickel, gold or copper, which can be used to provide wafer buffering and barrier action, and a good connection between the subsequent line and the wafer electrical connection end. Through the foregoing process, the present invention also discloses an integrated circuit board structure, which mainly comprises a support plate, which can be used for a general carrier board or a circuit board, and the support board is formed with at least one through hole. At least a semiconductor wafer having a plurality of electrical terminals is received in the opening; a first insulating layer is formed on the support plate and has the opening, and the first insulating layer has a plurality of first openings, the first opening is formed with a conductive structure electrically connected to the electrical connection end of the chip, wherein the conductive structure is a metal bump and the height is not higher than the opening of the brother And a second insulating layer formed on the first insulating layer, wherein the second insulating layer has a plurality of second openings, and the second opening is formed with a conductive structure electrically connected to the conductive structure Patterning 17814 (Revised) 10 1282160 Line structure. The conductive structure may be selected from a metal bump composed of a group consisting of nickel, gold, copper, etc., which can be used to provide buffering and resisting of the wafer, and a good connection between the subsequent circuit and the electrical connection end of the wafer. . Therefore, the circuit board structure and the manufacturing method thereof for integrating the semiconductor wafer of the present invention are mainly provided by providing at least a semiconductor wafer having an electrical connection end formed thereon and accommodating it in a support plate formed with the opening.俾 缩短 缩短 俾 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Connecting the conductive structure of the electrical connection end of the wafer to externally pull the electrical connection end of the crystal to the outside, and then forming a second insulating layer on the first insulating layer, by forming The circuit structure in the second insulating layer is electrically connected to the electrical connection end of the chip through the conductive structure, thereby combining the manufacturing process of the wafer carrier and the manufacturing process of the semiconductor packaging technology. Great demand elasticity and simplifying the process and interface coordination of the semiconductor industry, while avoiding the electrical conduction and molding of the conventional semi-fourth package process towel. [Embodiment] 'Intelligence and efficacy can be further improved to make the purpose of the present invention' "/ 八 此 疋 芡 芡 芡 认同 认同 认同 认同 认同 认同 认同 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合 配合Of course, the invention may be embodied in a variety of forms, and the following is a preferred embodiment of the invention, and is not intended to limit the scope of the invention. Please refer to FIG. 2A to FIG. 2G for a schematic cross-sectional view of a circuit board manufacturing method for an integrated semiconductor device of the present invention. As shown in Fig. 2A, a support plate 22 is first provided, which is a support plate 22 17814 (revision) 11 1282160
1 I 承tn:緣板等各式承载板甚或為電路板，且該支 曰 V 至少一貫穿開孔220，俾可供至少一半導體 日日片23收納於該支 、 晶片23上m奴 之開孔220中，其中該半導體 形成有歿數電性連接端（電極銲墊）23〇。 層24, 圖所示’接著’於支承板22上形成第一絕緣 4 =以—絕緣層24充填於該支承板開孔2 °亥弟—絕緣層24可例如為输炝改几此 脂層或感光高分子等。 強化树脂、盼聚酯或環氧樹 式以2 =圖所示，利用例如雷射鑽孔或微影製程等方 以顯二形成有複數個第-開口 24〇,藉 、\出該日日片23電路面之電性連接端230。 如第2D圖所示’於顯露出該第一開口挪之该 電十連接端23〇上形成導電 a 得以電性導接至該晶K M ㈣該W結構25 電社椹Μ ,, 〇日片23之電性連接端230。其中，該導 電、、、口構25之製作係可利用雷 沈積（如I電電梦）等方切& 沈積（如濺鑛）或化學 (”、、u鍍）#方式形成有例如錄、金 一者所構成之金屬凸塊，且幻寺孟屬之 离於> M 一 „ 口 V電、、Ό構25之高度係不 。、以罘一開口 240，俾用以 障作用，以及後續線路與晶片電性二":體—㈣與阻 ，、日日月电性連接端間良好接著。 如弟2Ε圖所示’於該第一絕緣層2 層26,該第二絕緣層26 成弟一、，、巴緣 緣層24之材質。 材貝了專同或相異於該第一絕 如弟2F圖所不’利用例如雷射開 術，以於該第二絕緣層26中报Α古、Ρ衣私4技 中形成有複數對應後續欲形成線 17814(修正本） 12 1282160 路之第二開口 26G，其中部分第二開口層係外露出該導 電結構25。 如第2G圖所#，利用電鍍、物理沈積（如濺鑛）或化學 /尤積（如揲电包鍍）等方式，以於該第二絕緣層％中之第二 開口 26G $成有線路結構27，俾使該線路結構π得以透 過該導電結構f電性連接至該日日日片23之電性連接端230。 此外，後績亦得在該第二絕緣層上進行線路之增層製 程，俾在該㈣有半導體晶片23之支承板22上形成有多 層線路結構，並使該線路結構得以電性連接至該晶片。其 中該曰層線路之製程係為習知製程技術，故於此不再為 文^ ί 層線路結構亦可同時實施於該支承板之兩 侧或單一側上。 復請參閱第2G圖所示，本發明亦揭露出一種整合半 導體晶片之電路板結構，主㈣包括有—支承板22，該支 ^板22可為—般之承载板或電路板，且該支承板22形成 =少—貫穿開孔22〇;至少—半導體晶片23，係收納於 该開孔220中，JL中讀曰y 電性連接端欺-第3^複__該開孔之 上且填充於該開孔220中f於該支承板22 數個第-開口 24。，該第：一：緣層22中具有複數複 23^4^1 ^ ^ m 9r ^ ^ 11連接鈿230，其中，該導 Γ=.25ί為一金屬凸塊且其高度不高於該第一開 一絶緣層26 ’係形成於該第-絕緣層24上， 弟二絕緣層26中具有複數個第二開口 ，該第二開 17814(修正本) 13 1282160 口 260形成有電性、 ' 27，並使魏 冑導電結構之圖案化線路結構 兮曰月°構27得以透過導電結構25電性連接至 鋅之紐連接端a。其中該導電結構25可選自 匕3有鎳、金、銅箄菜 用以楹徂a μ 則寺群組之一所構成之金屬凸塊，係可 =二，與阻障作用一線路與晶"性 法，主本發明之整合半導體晶片之電路板結構及 ^導體^ 先提供至少—表㈣成有電性連接端 俾可縮rl\ ’亚將其㈣於—形成有開孔之支承板中， 外，太=冷體裝置之整體厚度’以達輕薄短小目的；此 r緣厚$月於該收納有半導體晶片之支承板上形成有第一 Γ曰=亚於該第一絕緣層中之第一開口設置有電性連接 曰曰片電性連接端之導電結構，以使晶片之電性連接端外 β =俾可供後續在該第一絕緣層上形成第二絕緣層 才件以藉由形成在該第二絕緣層中第二開口之線路結 過該導電結構加以電性導接至該晶片之電性連接 而制藉此’即可結合晶片承載件之製造與半導體封裝技術 =衣耘，俾提供客戶端較大需求彈性以及簡化半導體業者 製程與界面協調問題，同時避免習知半導體封褒製程中之 電性導接與模覆等問題。 以上所述之具體實施例，僅係用以例釋本發明之特點 ^功效’而非用以限定本發明之可實施範蜂，在未脫離本 2明上揭之精神與技術料下，任何利本發明所揭示内 合而元成之等效改變及修飾，均仍應為下述之申請專利範 17814(修正本) 14 1282160 圍所涵蓋。 【圖式簡單說明】 第1A及1B圖係習知之覆晶式半導體封裝件之叫面示 意圖；以及 弟2A至2G圖係本發明之整合半導體晶片 法之剖面示意圖。 【主要元件符號說明】 11 金屬凸塊 12 電極鲜塾 13 半導體晶片 14 鲜錫凸塊 15 接觸銲墊 16 電路板 17 銲錫接 18 底膠材料 22 支承板 220 開孔 23 半導體晶片 230 電性連接端 24 第一絕緣層 240 第一開口 25 導電結構 26 第二絕緣層 260 第二開口 27 線路結構 之電路板製 17814(修正本) 151 I 承tn: various types of carrier boards such as edge plates or even circuit boards, and the support V is at least one through the opening 220, and at least one semiconductor day piece 23 is received on the branch and the chip 23 In the opening 220, the semiconductor is formed with a plurality of electrical connection terminals (electrode pads) 23A. Layer 24, shown as 'following' on the support plate 22 to form a first insulation 4 = with an insulating layer 24 filled in the support plate opening 2 ° Haidi - insulating layer 24 can be modified for example Or a photosensitive polymer. Reinforced resin, anti-polyester or epoxy tree type, as shown in Fig. 2, using a laser drilling or lithography process, for example, to form a plurality of first opening 24〇, borrowing, and exiting the day The electrical connection end 230 of the circuit surface of the chip 23. As shown in FIG. 2D, a conductive a is formed on the electrical connection terminal 23 of the first opening to electrically conduct the connection to the crystal KM. (4) The W structure 25, the Japanese film 23 electrical connection terminal 230. Wherein, the conductive, and the structure of the mouth structure 25 can be formed by using a square deposition & deposition (such as sputtering) or chemical (", u plating" method, such as recording, The metal bumps formed by the gold one, and the genus of the temple is separated from the height of the M-portion V, and the height of the structure 25 is not. With an opening 240, 俾 is used for the barrier function, and the subsequent line and the wafer electrical two ": body - (four) and resistance, and the monthly and monthly electrical connection between the good end. As shown in Fig. 2, the second insulating layer 26 is made of the first insulating layer 2, and the second insulating layer 26 is made of the material of the first layer. Material shells have the same or different from the first one, such as the 2F map does not use, for example, laser-opening, so that the second insulating layer 26 is reported in the ancient and the Ρ衣私4 Subsequent to form a new opening 26G of the line 17814 (Revised) 12 1282160, a portion of the second opening layer exposes the conductive structure 25. As shown in FIG. 2G, using electroplating, physical deposition (such as sputtering) or chemical/special product (such as galvanic plating), the second opening 26G $ of the second insulating layer is formed into a line. The structure 27 is configured to electrically connect the line structure π to the electrical connection end 230 of the day and the day sheet 23 through the conductive structure f. In addition, the post-production layer also has a line build-up process on the second insulating layer, and a multi-layer line structure is formed on the support board 22 of the (4) semiconductor wafer 23, and the line structure is electrically connected to the line structure. Wafer. The process of the layer line is a conventional process technology, so that the layer structure can no longer be applied to both sides or a single side of the support board. Referring to FIG. 2G, the present invention also discloses a circuit board structure for integrating a semiconductor chip. The main (4) includes a support board 22, which can be a general carrier board or a circuit board, and the board The support plate 22 is formed = less - through the opening 22 〇; at least - the semiconductor wafer 23 is received in the opening 220, and the JL is read 曰 y electrically connected to the end - the third hole _ _ above the opening And filling the opening 220 with a plurality of first openings 24 in the support plate 22. , the first: the edge layer 22 has a complex complex 23^4^1 ^ ^ m 9r ^ ^ 11 connection 钿 230, wherein the guide Γ = .25 ί is a metal bump and its height is not higher than the first An opening and insulating layer 26' is formed on the first insulating layer 24, and the second insulating layer 26 has a plurality of second openings. The second opening 17814 (corrected) 13 1282160 port 260 is formed with electrical, ' 27, and the patterned circuit structure of the Wei Wei conductive structure is electrically connected to the zinc connection terminal a through the conductive structure 25 . The conductive structure 25 may be selected from the group consisting of nickel, gold, and copper amaranth for the metal bumps formed by one of the group of 楹徂a μ temples, which may be two, and a barrier and a line and crystal "Sexual method, the circuit board structure and the conductor of the integrated semiconductor wafer of the present invention are provided at least - (4) into an electrically connected terminal 俾 俾 rl ' ' ' ' 四 四 四 四 四 形成 形成 形成 形成 形成 形成 形成 形成In the board, outside, too = the overall thickness of the cold body device is to be light, thin and short; the edge of the r is thicker than the first insulating layer formed on the supporting plate on which the semiconductor wafer is housed. The first opening is provided with a conductive structure electrically connected to the electrical connection end of the yoke, so that the electrical connection end of the wafer is β = 俾 for subsequent formation of the second insulating layer on the first insulating layer The fabrication of the wafer carrier can be combined with the semiconductor packaging technology by electrically connecting the conductive structure to the second opening of the second insulating layer to electrically connect the conductive structure to the wafer. = 耘, 俾 provide greater flexibility for the client and simplify the semiconductor industry Interface and coordination process, while avoiding the conventional power semiconductor package manufacturing process of praise of overlying conductive contact with the mold problems. The specific embodiments described above are merely used to illustrate the features of the present invention, and are not intended to limit the implementation of the present invention, and without departing from the spirit and technical materials disclosed in the present specification, The equivalent changes and modifications of the inventions disclosed in the present invention are still covered by the following patent application No. 17814 (Revised) 14 1282160. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are schematic views of a conventional flip-chip semiconductor package; and 2A to 2G are schematic cross-sectional views of the integrated semiconductor wafer method of the present invention. [Main component symbol description] 11 Metal bump 12 Electrode fresh slab 13 Semiconductor wafer 14 Fresh tin bump 15 Contact pad 16 Circuit board 17 Solder joint 18 Primer material 22 Support plate 220 Opening 23 Semiconductor wafer 230 Electrical connection 24 first insulating layer 240 first opening 25 conductive structure 26 second insulating layer 260 second opening 27 circuit board circuit structure 17814 (amendment) 15