TW201318127A - 形成包含保護層之凸塊結構的方法 - Google Patents
形成包含保護層之凸塊結構的方法 Download PDFInfo
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Abstract
揭示於本文的一個示範方法包括下列步驟:在一層絕緣材料中形成導電墊,形成鈍化層於該導電墊上方,對該鈍化層執行至少一個蝕刻製程以在該鈍化層中定義暴露該導電墊之至少一部份的開口,在該鈍化層上、在該開口中、以及在該導電墊之該暴露部份上形成保護層,形成熱固化材料層於該保護層上方,執行蝕刻製程以定義有暴露該保護層之一部份之開口的圖案化熱固化材料層,對該保護層執行蝕刻製程以藉此暴露該導電墊之至少一部份,以及形成導電耦合至該導電墊的導電凸塊。
Description
本揭示內容大體有關於精密半導體裝置的製造,且更特別的是,形成導電凸塊結構於積體電路裝置上的各種方法以及包含該等結構的裝置。
在製造現代積體電路時,通常需要在構成微型電子裝置的各種半導體晶片之間提供電氣連接。取決於晶片的類型與整體的裝置設計要求,可用各種方法實現這些電氣連接,例如,打線接合法、捲帶式自動接合法(TAB),覆晶接合法及其類似者。近年來,利用覆晶技術,其中半導體晶片用由所謂焊料凸塊形成的焊球來附著至基板、載體或其他晶片,已變成半導體加工工業的重要方面。在覆晶技術中,焊球係形成於待連接晶片中之至少一個晶片的接觸層上,例如,在形成於包含複數個積體電路之半導體晶片的最後金屬化層上方的電介質鈍化層上。同樣,有適當大小及定位的接合墊形成於另一晶片上,例如,承載封裝件,各個接合墊對應至形成於半導體晶片上的焊球。然後,這兩種單元(亦即,半導體晶片與承載封裝件)的電氣連接係藉由“翻轉”半導體晶片以及使焊球與接合墊物理接觸,以及進行“回焊”製程使得每個焊球黏著至對應接合墊。通常有數百甚至數千個焊料凸塊可分布於整個晶片區域,藉此提供,例如,現代半導體晶片所要求的輸入及輸出性能,而現代半導體晶片經常包括複雜的電路,例如微處理
器、儲存電路、三維(3D)晶片及其類似者,及/或形成完整複雜電路系統的複數個積體電路。
第1A圖至第1F圖圖示用於形成半導體裝置之導電凸塊的一個示範先前技術加工流程。第1A圖圖示在早期製造階段的示範先前技術裝置100。如圖示,在一層絕緣材料10中形成複數個導電墊12。在該層絕緣材料上方形成示範鈍化層14。在一個示範實施例中,鈍化層14可由多層材料構成。更具體而言,在圖示實施例中,鈍化層14可由示範厚度約100奈米的氮化矽碳(BLOK)14A層,示範厚度約450奈米的二氧化矽14B層以及示範厚度約400奈米的氮化矽層構成。可用傳統沉積製程來形成層14A、14B及14C,例如化學氣相沉積(CVD)製程。
接下來,如第1B圖所示,在鈍化層14中形成數個開口16以藉此部份暴露導電墊12。開口16可用傳統微影技術及蝕刻製程形成。更具體而言,通過圖案化光阻遮罩(未圖示)完成一個或多個蝕刻製程以形成該等開口16。開口的尺寸可隨著特定應用而有所不同。
接下來,如第1C圖所示,形成聚亞醯胺層18。聚亞醯胺層18的形成通常藉由用旋塗技術初始沉積聚亞醯胺材料,之後,以例如約360℃的溫度執行加熱製程,以固化聚亞醯胺層18。在有些情形下,聚亞醯胺層18可具有約2至10微米的厚度。可惜,在形成聚亞醯胺層18的加工期間,在聚亞醯胺層18與導電墊12的介面處形成氧化物材料19,例如,氧化銅。應注意,儘管氧化物材料19
被圖示成為均勻層,然而實際上氧化可能並非如此均勻地分布於導電墊12上。氧化物材料19的存在可能傾向局部增加導電墊12與將形成於導電墊12上方的導電凸塊之間的電阻。電阻增加可能降低所得半導體裝置的績效性能。
第1D圖圖示在已執行數個製程操作之後的裝置100。首先,已用習知微影技術及蝕刻技術圖案化聚亞醯胺層18。更具體而言,通過形成於聚亞醯胺層18上方的圖案化光阻遮罩(未圖示)執行一個或多個蝕刻製程以形成第1D圖的圖案化聚亞醯胺層18。然後,凸塊下金屬化(UBM)層20係以毯覆方式沉積(blanket-deposited)在整個裝置100上。UBM層20可由多層材料構成以及可用一個或多個沉積製程形成。在一個實施例中,UBM層20可由由鈦構成的初始層與由銅構成的第二層構成。
然後,如第1E圖所示,在裝置100上方形成圖案化遮罩層22,例如,光阻遮罩,以及在裝置100上形成用於導電凸塊的導電材料24。在一個示範實施例中,執行鍍覆製程以形成一層鎳(未圖示)於裝置的暴露部份上,接著用另一鍍覆製程形成導電材料24的塊材(bulk)。在一個示範實施例中,導電材料24由錫-銀構成,但是也可使用其他材料。
第1F圖圖示在已執行其他製程操作之後的裝置100。起先,移除圖案化遮罩層22(參考第1E圖)。之後,執行加熱或回焊製程導致形成第1F圖的示範導電凸塊24B。
本揭示內容針對形成導電凸塊於半導體裝置上的各
種方法用以避免或至少減少上述問題中之一個或多個的影響。
為供基本理解本發明的一些態樣,提出以下簡化的總結。此總結並非本發明的詳盡總覽。它不是想要識別本發明的關鍵或重要元件或者是描繪本發明的範疇。唯一的目的是要以簡要的形式提出一些概念作為以下更詳細之說明的前言。
一般而言,本揭示內容針對形成導電凸塊結構於積體電路裝置上的各種方法,其中,在一些具體實施例中,使用保護層,以及包含此類結構的裝置。在一實施例中,該方法包括:在一層絕緣材料中形成導電墊,形成鈍化層於該導電墊及該層絕緣材料上方,對該鈍化層執行至少一個蝕刻製程以在該鈍化層中定義暴露該導電墊之至少一部份的開口以及在該鈍化層上、在該開口中以及在該導電墊之該暴露部份上形成保護層。在此實施例中,該方法更包括下列步驟:形成熱固化材料層(例如,聚亞醯胺層或PBO層)於該保護層上方,對熱固化材料層執行蝕刻製程以定義有暴露該保護層之一部份之開口的圖案化熱固化材料層,執行蝕刻製程以移除該保護層之該暴露部份以藉此暴露該導電墊的至少一部份,以及在移除該保護層之該暴露部份後,形成導電耦合至該導電墊的導電凸塊。
在一個示範具體實施例中,揭示於本文的裝置包含:位於絕緣材料層中的第一及第二隔開導電墊,各自導電耦
合至該第一及該第二導電墊的第一及第二凸塊下金屬化層,以及各自導電耦合至該第一及該第二凸塊下金屬化層的第一及第二隔開導電凸塊。在此實施例中,該裝置更包含在該第一及該第二隔開導電凸塊之間位於該層絕緣材料上方的鈍化層,以及位在該層絕緣材料上的保護層,其中該保護層在該第一及該第二凸塊下金屬化層之間延伸以及與彼等接觸。
揭示於本文的另一示範方法包括:在一層絕緣材料中形成導電墊,形成積層鈍化層(multi-layer passivation layer)於該導電墊上方以及於該層絕緣材料上方,其中該積層鈍化層的第一層與該導電墊及該層絕緣材料接觸,對該積層鈍化層執行至少一個蝕刻製程以移除該積層鈍化層之至少一層,以藉此定義有凹處的蝕刻後鈍化層,該凹處暴露該第一層之至少一部份以及形成熱固化材料層於該蝕刻後鈍化層及該第一層之該暴露部份上方。在此實施例中,該方法更包括:對該熱固化材料層執行蝕刻製程以定義有開口的圖案化熱固化材料層,該開口係暴露該蝕刻後鈍化層之一部份以及該第一層之該暴露部份,執行蝕刻製程以移除該第一層之該暴露部份以藉此暴露該導電墊之至少一部份,以及在移除該第一層之該暴露部份後,形成導電耦合至該導電墊的一導電凸塊。
以下描述本發明的各種示範具體實施例。為了清楚說明,本專利說明書沒有描述實際具體實作的所有特徵。當
然,應瞭解,在開發任一此類的實際具體實施例時,必需做許多與具體實作有關的決策以達成開發人員的特定目標,例如遵循與系統相關及商務有關的限制,這些都會隨著每一個具體實作而有所不同。此外,應瞭解,此類開發即複雜又花時間,但對本技藝一般技術人員而言,在閱讀本揭示內容後不過是例行工作。
此時以參照附圖來描述本發明。示意圖示於附圖的各種結構、系統及裝置係僅供解釋以及避免熟諳此藝者所習知的細節混淆本揭示內容。儘管如此,仍納入附圖用來描述及解釋本揭示內容的示範實施例。應使用與相關技藝技術人員所熟悉之意思一致的方式理解及解釋用於本文的字彙及片語。本文沒有特別定義的用語或片語(亦即,與熟諳此藝者所理解之普通慣用意思不同的定義)是想要用用語或片語的一致用法來暗示。在這個意義上,希望用語或片語具有特定的意思時(亦即,不同於熟諳此藝者所理解的意思),則會在本專利說明書中以直接明白地提供特定定義的方式清楚地陳述用於該用語或片語的特定定義。
本揭示內容針對形成導電凸塊結構於積體電路裝置上的各種方法。熟諳此藝者在讀完本申請案會明白,揭示於本文的方法可應用於各種裝置,包括但不受限於:ASIC,邏輯裝置,記憶體裝置、等等。參考第2A圖至第2G圖及第3A圖至第3G圖,此時會更詳細地描述揭示於本文之方法及裝置的各種示範具體實施例。只要用於第1A圖至第1F圖以及第2A圖至第2G圖或第3A圖至第3G圖的元件符
號相同,該等結構的先前說明同樣可應用於第2A圖至第2G圖及第3A圖至第3G圖。
第2A圖至第2G圖圖示揭示於本文用於形成半導體裝置200之導電凸塊的一個示範加工流程。第2A圖圖示在早期製造階段的新穎裝置200。如圖示,在一層絕緣材料10中形成複數個隔開的導電墊12。該層絕緣材料10可由各種絕緣材料構成,例如,低k(k值小於3)材料、二氧化矽、等等。該層絕緣材料10的形成可藉由執行各種習知沉積製程,例如,CVD製程。導電墊12可由各種材料構成,例如,銅、銅合金、鋁、鋁合金、等等。導電墊12可具有任何所欲組構以及它們可用傳統技術形成。也圖示於第2A圖的是形成於該層絕緣材料10上方的圖案化鈍化層14。一般而言,第2A圖的裝置200對應至第1B圖的裝置100。在一個示範實施例中,鈍化層14可由多層材料構成。更具體而言,在圖示實施例中,鈍化層14可由以下3層構成:示範厚度約100奈米的氮化矽碳(BLOK)14A層、示範厚度約450奈米的二氧化矽14B層、以及示範厚度約400奈米的氮化矽層。另外,在有些情形下,層14A、14B及14C的順序可顛倒,然而在其他情形下,用來構成積層鈍化層的層數可大於3,例如,4層鈍化層14(BLoK/SiO2/SiN/SiO2)。熟諳此藝者在讀完本申請案後會明白,鈍化層14可由各種材料構成,例如二氧化矽、氮化矽、TEOS、FTEOS、SiOF、等等,包括該等材料的組合物。層14A、14B及14C可用傳統沉積製程形成,例如CVD製程。如第2A圖所示,在鈍化層14
中形成複數個開口16以藉此部份暴露導電墊12。開口16可用傳統微影技術及蝕刻製程形成。更具體而言,通過圖案化光阻遮罩(未圖示)執行一個或多個蝕刻製程以形成該等開口16。開口16的尺寸可隨著特定應用而有所不同。
接下來,如第2B圖所示,形成保護層202於裝置200上方,特別是於導電墊12的暴露部份上方。在一個示範實施例中,保護層202可由二氧化矽、含氟矽玻璃(SiOF)、氮化矽、氮化矽碳(SiCN)等等構成,它可厚約20至300奈米,以及可藉由執行各種習知沉積製程(例如,CVD)、原子層沉積(ALD)、或該等製程的電漿增強版來形成。
然後,如第2C圖所示,形成熱固化材料層218。熱固化材料218可由各種材料形成,例如,聚亞醯胺、聚苯噁唑(PBO)、等等。熱固化材料層218的形成通常藉由用旋塗技術初始沉積熱固化材料,之後以例如約360℃的溫度執行加熱製程,以固化熱固化材料層218。在有些情形下,熱固化材料層218可厚約2至10微米。除了別的以外,保護層202用來保護底下導電墊12免受害於在使用第1A圖至第1F圖之先前技術加工流程執行加熱製程以固化聚亞醯胺層18時發生的不合意氧化作用。
第2D圖圖示在已用習知微影技術及蝕刻技術圖案化熱固化材料層218之後的裝置200。更具體而言,通過形成於熱固化材料層218上方的圖案化光阻遮罩(未圖示)執行一個或多個蝕刻製程以形成第2D圖的圖案化熱固化材料層218A。
接下來,如第2E圖所示,通過圖案化熱固化材料層218A,對保護層202執行蝕刻製程以形成第2E圖的圖案化保護層202A。此蝕刻製程暴露導電墊12的部份供進一步加工。
第2F圖圖示在已執行數個製程操作之後的裝置200。首先,毯覆式沉積凸塊下金屬化(UBM)層20於裝置200上。UBM層20可由多層材料構成以及可用一個或多個沉積製程形成。在一個實施例中,UBM層20可由厚約50至300奈米由鈦構成的初始層(未圖示)以及形成於該鈦層或鈦-鎢層上厚約100至500奈米的銅層(未圖示)構成。UBM層20的形成可藉由執行各種習知技術,例如,執行一個或多個物理氣相沉積(PVD)製程。然後,繼續參考第2F圖,在裝置200上方形成圖案化遮罩層22,例如,光阻遮罩,以及在裝置200上形成用於導電凸塊的導電材料24。在一個示範實施例中,執行鍍覆製程以形成一層鎳(未圖示)於裝置200的暴露部份上,接著用另一鍍覆製程形成導電材料24的塊材。在一個示範實施例中,導電材料24由錫-銀構成,但是也可使用其他材料,例如SnCu或SnAgCu。
第2G圖圖示在已執行其他製程操作之後的裝置200。初始,移除圖案化遮罩層22(參考第2F圖)。之後,執行加熱或回焊製程導致形成第2G圖的示範導電凸塊24B。
由第2G圖可見,揭示於本文的新穎裝置200包含位在一層絕緣材料10之中的第一及第二隔開導電墊12,各自導電耦合至第一及第二導電墊12的第一及第二隔開凸
塊下金屬化層20,以及各自導電耦合至該第一及該第二凸塊下金屬化層20的第一及第二隔開導電凸塊24B。在此實施例中,裝置200更包含在第一及第二隔開導電凸塊24B之間位於該層絕緣材料10上方的鈍化層以及位在該層絕緣材料10上的保護層302,其中保護層302在第一及第二凸塊下金屬化層20之間延伸及與彼等接觸。
第3A圖至第3G圖圖示揭示於本文用以形成半導體裝置300之導電凸塊的另一示範加工流程。第3A圖圖示在早期製造階段的新穎裝置300。如圖示,在一層絕緣材料10中形成複數個隔開導電墊12。也圖示於第2A圖的是積層鈍化層(multi-layer passivation layer)14。在圖示實施例中,積層鈍化層14係由以下3層構成:形成於該層絕緣材料10上有示範厚度約100奈米的氮化矽碳(BLOK)302層、形成於層302上有示範厚度約450奈米的二氧化矽14B層、以及形成於層14B上有示範厚度約400奈米的氮化矽14C層。前文已討論過鈍化層14的替代材料。層302、14B及14C可用傳統沉積製程形成,例如CVD製程。在第3A圖中,已通過圖案化遮罩層(未圖示),例如,光阻遮罩,對鈍化層14執行一個或多個蝕刻製程,以部份移除構成積層鈍化層14的材料層。這些蝕刻製程導致在鈍化層14中形成數個凹處304以及部份暴露層302,該層與導電墊12及該層絕緣材料10接觸。
然後,如第3B圖所示,如上述,形成熱固化材料層218。除了別的以外,第一層302用來保護底下導電墊12
免受害於在使用第1A圖至第1F圖之先前技術加工流程來形成聚亞醯胺層18時發生的不合意氧化作用。
第3C圖圖示在已用習知微影技術及蝕刻技術圖案化熱固化材料層218之後的裝置300。更具體而言,通過形成於熱固化材料層218上方的圖案化光阻遮罩(未圖示),執行一個或多個蝕刻製程以形成第3C圖的圖案化熱固化材料層218A。
接下來,如第3D圖所示,通過圖案化熱固化材料層218A,對層302執行蝕刻製程以形成第3D圖的圖案化層302A。此蝕刻製程暴露導電墊12以便進一步加工。
第3E圖圖示在毯覆式沉積凸塊下金屬化(UBM)層20於裝置300上之後的裝置300。UBM層20可由多層材料構成以及可用一個或多個沉積製程形成。在一個實施例中,UBM層20可由厚約50至300奈米由鈦構成的初始層(未圖示)以及形成於該鈦層或鈦-鎢層上厚約100至500奈米的銅層(未圖示)構成。UBM層20的形成可藉由執行各種習知技術,例如,執行一個或多個物理氣相沉積(PVD)製程。
然後,如第3F圖所示,在裝置300上方形成圖案化遮罩層22,例如,光阻遮罩,以及在裝置300上形成用於導電凸塊的導電材料24。在一個示範實施例中,執行鍍覆製程以形成一層鎳(未圖示)於裝置300的暴露部份上,接著用另一鍍覆製程形成導電材料24的塊材。在一個示範實施例中,導電材料24由錫-銀構成,但是也可使用其他材料,例如SnCu或SnAgCu。
第3G圖圖示在已執行其他製程操作之後的裝置300。起先,移除圖案化遮罩層22(參考第3F圖)。之後,執行加熱或回焊製程導致形成第3G圖的示範導電凸塊24B。
以上所揭示的特定具體實施例均僅供圖解說明,因為熟諳此藝者在受益於本文的教導後顯然可以不同但等價的方式來修改及實施本發明。例如,可用不同的順序完成以上所提出的製程步驟。此外,除非在以下申請專利範圍有提及,不希望本發明受限於本文所示之構造或設計的細節。因此,顯然可改變或修改以上所揭示的特定具體實施例而所有此類變體都被認為仍然是在本發明的範疇與精神內。因此,本文提出以下的申請專利範圍尋求保護。
10‧‧‧絕緣材料層
12‧‧‧導電墊
14‧‧‧圖案化鈍化層
14A、302‧‧‧氮化矽碳(BLOK)層
14B‧‧‧二氧化矽層
14C‧‧‧氮化矽層
16‧‧‧開口
18‧‧‧聚亞醯胺層
19‧‧‧氧化物材料
20‧‧‧凸塊下金屬化(UBM)層
22‧‧‧圖案化遮罩層
24‧‧‧導電材料
24B‧‧‧第一及第二隔開導電凸塊
100‧‧‧示範先前技術裝置
200、300‧‧‧半導體裝置
202、302‧‧‧保護層
202A‧‧‧圖案化保護層
218‧‧‧熱固化材料層
218A‧‧‧圖案化熱固化材料層
302A‧‧‧圖案化層
304‧‧‧凹處
參考以下結合附圖的說明可明白本揭示內容,其中類似的元件係以相同的元件符號表示。
第1A圖至第1F圖圖示用來形成凸塊結構於積體電路裝置上的示範先前技術的技術;第2A圖至第2G圖圖示揭示於本文用以形成導電凸塊結構於積體電路裝置上的示範加工流程,其中凸塊結構係包含保護層;以及第3A圖至第3G圖圖示揭示於本文用以形成導電凸塊結構於積體電路裝置上的另一示範加工流程。
儘管本發明容易做成各種修改及替代形式,本文仍以附圖為例圖示幾個本發明的特定具體實施例且詳述其中的細節。不過,應瞭解本文所描述的特定具體實施例不是想
要把本發明限定成本文所揭示的特定形式,反而是,本發明是要涵蓋落在如隨附申請專利範圍所界定之本發明精神及範疇內的所有修改、等價及替代性陳述。
10‧‧‧絕緣材料層
12‧‧‧導電墊
14A‧‧‧氮化矽碳(BLOK)層
14B‧‧‧二氧化矽層
14C‧‧‧氮化矽層
20‧‧‧凸塊下金屬化(UBM)層
24B‧‧‧第一及第二隔開導電凸塊
200‧‧‧半導體裝置
202‧‧‧保護層
218A‧‧‧圖案化熱固化材料層
Claims (25)
- 一種方法,係包含:在一層絕緣材料中形成導電墊;形成鈍化層於該導電墊及該層絕緣材料上方;對該鈍化層執行至少一個蝕刻製程,以在該鈍化層中定義暴露該導電墊之至少一部份的開口;在該鈍化層上、在該開口中以及該導電墊之該暴露部份上形成保護層;在該保護層上方形成熱固化材料層;對該熱固化材料層執行蝕刻製程,以定義具有暴露該保護層之一部份之開口的圖案化熱固化材料層;執行蝕刻製程,以移除該保護層之該暴露部份,藉此暴露該導電墊之至少一部份;以及在移除該保護層之該暴露部份後,形成導電耦合至該導電墊的導電凸塊。
- 如申請專利範圍第1項所述之方法,其中,形成該熱固化材料層於該保護層上方包括:沉積用於該熱固化材料層的熱固化材料以及執行加熱製程以固化用於該熱固化材料層之該熱固化材料,同時該保護層位在該導電墊之該暴露部份上。
- 如申請專利範圍第1項所述之方法,其中,形成該鈍化層於該導電墊及該層絕緣材料上方包括:形成積層鈍化層於該導電墊及該層絕緣材料上方。
- 如申請專利範圍第3項所述之方法,其中,該積層鈍化 層由以下三層所構成:由形成於該層絕緣材料上之矽、碳及氮構成的第一層,由形成於該第一層上之二氧化矽構成的第二層,以及由形成於該第二層上之氮化矽構成的第三層。
- 如申請專利範圍第1項所述之方法,其中,在該層絕緣材料中形成該導電墊包括:在該層絕緣材料中形成由銅構成的導電墊。
- 如申請專利範圍第1項所述之方法,其中,形成該導電凸塊包括:形成由錫及銀、SnAg、或SnAgCu構成的導電凸塊。
- 如申請專利範圍第1項所述之方法,其中,在形成該導電凸塊之前,形成與該導電墊、該保護層及該圖案化熱固化材料層接觸的凸塊下金屬化層。
- 如申請專利範圍第1項所述之方法,其中,在該鈍化層上形成該保護層包括:在該鈍化層上沉積由二氧化矽或含氟矽玻璃(SiOF)、氮化矽(SiN)或氮化矽碳(SiCN)中之一者構成的保護層。
- 如申請專利範圍第8項所述之方法,其中,該保護層具有20至300奈米的厚度。
- 如申請專利範圍第1項所述之方法,其中,該熱固化材料層係由聚亞醯胺與聚苯噁唑(PBO)中之一者構成。
- 一種裝置,係包含:位於一層絕緣材料中的第一及第二隔開導電墊;各自導電耦合至該第一及該第二導電墊的第一及 第二凸塊下金屬化層;各自導電耦合至該第一及該第二凸塊下金屬化層的第一及第二隔開導電凸塊;在該層絕緣材料上方位於該第一及該第二隔開導電凸塊之間的鈍化層;以及位在該層絕緣材料上的保護層,該保護層在該第一及該第二凸塊下金屬化層之間延伸並與該第一及該第二凸塊下金屬化層接觸。
- 如申請專利範圍第11項所述之裝置,其中,該保護層係由二氧化矽或含氟矽玻璃(SiOF)、氮化矽(SiN)或氮化矽碳(SiCN)中之一者構成。
- 如申請專利範圍第12項所述之裝置,其中,該保護層具有20至300奈米的厚度。
- 如申請專利範圍第11項所述之裝置,其中,該第一及該第二隔開導電凸塊中之每一者由錫及銀、SnAg或SnAgCu構成。
- 如申請專利範圍第14項所述之裝置,其中,該第一及該第二隔開導電墊係由銅構成。
- 如申請專利範圍第11項所述之裝置,其中,該鈍化層係由以下三層構成的積層鈍化層:由形成於該層絕緣材料上之矽、碳及氮構成的第一層,由形成於該第一層上之二氧化矽構成的第二層,以及由形成於該第二層上之氮化矽構成的第三層。
- 如申請專利範圍第16項所述之裝置,其中,該保護層 係形成於該第三層上。
- 如申請專利範圍第11項所述之裝置,更包含形成於該保護層上的熱固化材料層,該熱固化材料層在該第一及該第二凸塊下金屬化層之間延伸並與該第一及該第二凸塊下金屬化層接觸。
- 如申請專利範圍第18項所述之裝置,其中,該熱固化材料層係由聚亞醯胺與聚苯噁唑(PBO)中之一者構成。
- 一種方法,係包含:在一層絕緣材料中形成導電墊;形成積層鈍化層於該導電墊上方以及於該層絕緣材料上方,該積層鈍化層之第一層係與該導電墊及該層絕緣材料接觸;對該積層鈍化層執行至少一個蝕刻製程,以移除該積層鈍化層之至少一個層,該至少一個蝕刻製程定義具有暴露該第一層之至少一部份之凹處的蝕刻後鈍化層;形成熱固化材料層於該蝕刻後鈍化層及該第一層之該暴露部份上方;對該熱固化材料層執行蝕刻製程,以定義具有開口的圖案化熱固化材料層,該開口係暴露該蝕刻後鈍化層之一部份以及該第一層之該暴露部份;執行蝕刻製程,以移除該第一層之該暴露部份,藉此暴露該導電墊之至少一部份;以及在移除該第一層之該暴露部份後,形成導電耦合至該導電墊的導電凸塊。
- 如申請專利範圍第20項所述之方法,其中,形成該熱固化材料層於該蝕刻後鈍化層及該第一層之該暴露部份上方包括:沉積用於該熱固化材料層的熱固化材料以及執行加熱製程以固化用於該熱固化材料層之該熱固化材料,同時該第一層之該暴露部份位在該導電墊上。
- 如申請專利範圍第20項所述之方法,其中,形成該積層鈍化層包括:形成由在該層絕緣材料上之矽、碳及氮構成的第一層,形成由在該第一層上之二氧化矽構成的第二層,以及形成由在該第二層上之氮化矽構成的第三層。
- 如申請專利範圍第20項所述之方法,其中,在該層絕緣材料中形成該導電墊包括:在該層絕緣材料中形成由銅構成的導電墊。
- 如申請專利範圍第20項所述之方法,其中,形成該導電凸塊包括:形成由錫及銀、SnAg或SnAgCu構成的導電凸塊。
- 如申請專利範圍第20項所述之方法,其中,該熱固化材料層係由聚亞醯胺與聚苯噁唑(PBO)中之一者構成。
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TWI495067B (zh) | 2015-08-01 |
SG189636A1 (en) | 2013-05-31 |
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CN103077897A (zh) | 2013-05-01 |
US20140021604A1 (en) | 2014-01-23 |
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US8580672B2 (en) | 2013-11-12 |
US20130099372A1 (en) | 2013-04-25 |
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