201112364 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別佐士 Μ # 付别係有關於一種内置 於半導體封裝構造之中介連接器。 【先前技術】 隨著電子產業的蓬勃發展，電子 书丁座。α通常需要小型、 高效能、多功能、高速、大容量、低僧 他價格等特徵。因此201112364 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and particularly to a mediator connector that is built in a semiconductor package structure. [Prior Art] With the booming electronics industry, e-books. α usually requires features such as small size, high performance, versatility, high speed, large capacity, and low price. therefore
發展了將半導體封裝構造以多晶片模組化(Mum (叫 ModuU; MCM)的形式呈現’此種封裝構造可縮減整體 封裝構造體積並提昇電性功能，遂而成為一種封裝的主 流。其中堆疊式晶片之半導體封裝構造係在一如印刷電 路板或之晶片承載體（chip carrier)上安裝至少兩半導體 晶片，晶片的堆疊可為以垂直堆疊（stack)方式此種堆 疊式晶片之半導體封裝構造可見於美國專利第 7，166’495號、第6,861，761號以及第6,621 155號等習 知技術中。 …：而’由於晶片銲墊（chip pad)的間距較小且晶片種 類有多樣性，在進行晶片的堆疊作業時，並無法使對應 的晶片銲墊相互對齊與鄰靠，並且晶片承載體之接墊配 置無法70全符合所有晶片的打線連接要求。因此，在晶 片之間有必要設置一中介連接器（interp〇ser)，作為堆疊 晶片的晶片銲墊與晶片承載體之接墊之間的電性連接。 請參閱第1圖所示，為習知的一種堆疊式晶片之半導 體封裝構造之截面示意圖。該堆疊式晶片之半導體封裝 201112364 構造係包含一第一晶片10、一第二晶片20、一基板30 以及一中介連接器100。該些晶片10、20包括各種晶片， 例如記憶體晶片（memory chip)、非記憶體晶片（non memory chip) 、 邏 輯晶片 （logic chip) 以及類 比晶片 (analog chip)。該些晶片10、2〇之主動面朝上並垂直堆 疊在該基板30上。該中介連接器ι〇〇係設置於該第一晶 片1〇與該第二晶片20之間。該中介連接器1〇〇的上表 面係形成有一重配置線路結構120。該第一晶片1〇之複 數個第一銲墊11係藉由複數個銲線41而連接至該重配 置線路結構120，該第二晶片20之複數個第二銲墊21 係藉由複數個銲線42而連接至該重配置線路結構丨2〇， 再透過該重配置線路結構12〇與複數個銲線43電性連接 至該基板30。該重配置線路結構12〇係做為該些晶片 1〇、20將鲜線41、42連接至該基板3〇之中繼配線。並 藉由該中介連接器丨00而達成該些晶片1〇 2〇與該基板 30之電性連接。然習知之中介連接器1〇〇為一具有預定 厚度（大於150微米）之多層佈線板所構成，利用pwB(印 刷電路板）製程的增層法（build_up)或疊層法來製造。習 知中介連接器100不僅與該些晶片1〇、2〇有著熱膨脹係 數之差異更有相當厚度足以在封裝構造中產生内應力， 引發產品可靠度降低的問題。此外，該堆疊式晶片之半 導體封裝構造的尺寸與厚度亦無法進一步縮小。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 201112364 一種内置於半導體封裝構造之中介連接器，具有薄化、 供打線連接與消除封裝内應力的功效，能有效縮小半導 體封裝構造之體積，並有效降低成本。 種内置於半導體封 構可不位在習知承 脹係數不匹配導致 本發明之次一目的係在於提供一 裝構造之中介連接器，重配置線路結 載板之表面，可避免因與晶片的熱膨 脫層或趣曲之問題。The development of the semiconductor package structure in the form of multi-chip modularization (Mum (called ModuU; MCM)] This package structure can reduce the overall package construction volume and enhance the electrical function, which becomes the mainstream of a package. The semiconductor package structure of the wafer is mounted on at least two semiconductor wafers on a printed circuit board or a chip carrier, and the stack of the wafers may be a semiconductor package structure of such a stacked wafer in a vertical stacking manner. It is found in the prior art such as U.S. Patent Nos. 7,166,495, 6,861,761 and 6,621,155. ... and because of the small pitch of the chip pads and the variety of wafer types When the wafer stacking operation is performed, the corresponding wafer pads cannot be aligned and adjacent to each other, and the pad carrier configuration of the wafer carrier cannot meet the wire bonding requirements of all the wafers. Therefore, it is necessary to have a wafer between the wafers. An interposer is provided as an electrical connection between the wafer pads of the stacked wafer and the pads of the wafer carrier. 1 is a schematic cross-sectional view showing a conventional semiconductor package structure of a stacked wafer. The semiconductor package 201112364 of the stacked wafer includes a first wafer 10, a second wafer 20, a substrate 30, and an intermediate. The connector 100. The wafers 10, 20 include various wafers, such as a memory chip, a non-memory chip, a logic chip, and an analog chip. The active side faces 10 and 2 are vertically stacked on the substrate 30. The intermediate connector is disposed between the first wafer 1 and the second wafer 20. The intermediate connector 1〇〇 The top surface of the first wafer 1 is connected to the reconfiguration wiring structure 120 by a plurality of bonding wires 41, and the second wafer 20 A plurality of second pads 21 are connected to the reconfigured wiring structure 藉2〇 by a plurality of bonding wires 42, and are electrically connected to the substrate 30 through the reconfiguring wiring structure 12A and the plurality of bonding wires 43. Reconfiguration The circuit structure 12 is used as the wafers 1 and 20 to connect the fresh wires 41 and 42 to the relay wiring of the substrate 3, and the wafers 1 and 2 are realized by the interposer 丨00. The substrate 30 is electrically connected. However, the conventional interposer 1 is composed of a multilayer wiring board having a predetermined thickness (greater than 150 micrometers), and a build-up method using a pwB (printed circuit board) process or It is manufactured by a lamination method. The conventional interposer 100 not only has a difference in thermal expansion coefficient from the wafers 1 and 2, but has a considerable thickness enough to generate internal stress in the package structure, causing a problem of reduced product reliability. In addition, the size and thickness of the semiconductor package structure of the stacked wafer cannot be further reduced. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a dielectric connector built in a semiconductor package structure, which has the advantages of thinning, wire bonding, and elimination of stress in the package, and can effectively reduce the semiconductor package. Construct volume and effectively reduce costs. The second purpose of the present invention is to provide a dielectric connector with a mounting structure to reconfigure the surface of the line junction board to avoid heat due to the wafer. The problem of swelling or fun.
本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種内置於半導體封裝構造之 中介連接器，包含一底保護層、一重配置線路結構、一 表面保護層以及複數個第一電鍍接指與第二電鍍接指。 該底保護層係為整片狀並具有介於4至8微米之厚度。 該重配置線珞結構係設置於該底保護層上並具有至少一 層厚度介於4至8微米之線路層。該表面保護層係覆蓋 該重配置線珞結構與該底保護層上，該表面保護層在該 重配置線路結構上的厚度係介於5至6微米，並且該表 面保護層係具有複數個開孔。該些第一電鍍接指與第二 電鍍接指，係設置於該些開孔内而顯露在同一表面，並 經由該重配置線路結構而使對應之第一電鑛接指與第二 電鍍接指相互電性連接。其中，該底保護層、該重配置 線路結構與該表面保護層的組合厚度係不大於50微米。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的中介連接器中，該些第一電鍍接指與該些第 201112364 電鍍接指係可不突出於綠± ^ 、表面保護層。 在前述的中介連接器中， 些第一電鍵接指與 電鍍接指係可為鎳金電鐵層 興这二第 在前述的中介連接器Φ ’可另包含一承載片，以供嗜 底保護層之形成。 在前述的中介連接器Φ 中該底保護層係可具有一平挺 化的底面。 匀十太一The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses an interposer connector embedded in a semiconductor package structure, comprising a bottom protection layer, a reconfiguration line structure, a surface protection layer and a plurality of first plating fingers and second plating fingers. The bottom protective layer is monolithic and has a thickness of between 4 and 8 microns. The reconfigurable coil structure is disposed on the bottom protective layer and has at least one layer of wiring having a thickness of 4 to 8 microns. The surface protective layer covers the reconfigured coil structure and the bottom protective layer, the surface protective layer has a thickness of 5 to 6 micrometers on the reconfigured wiring structure, and the surface protective layer has a plurality of openings hole. The first electroplating fingers and the second electroplating fingers are disposed in the openings to be exposed on the same surface, and the corresponding first electrocoagulation fingers and the second plating are connected via the reconfigurable circuit structure. Refers to each other electrically connected. Wherein, the bottom protective layer, the combined layout structure and the surface protective layer have a combined thickness of no more than 50 micrometers. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing interposer, the first plated fingers and the 201112364 plated fingers may not protrude from the green ± ^, surface protective layer. In the above-mentioned intermediate connector, some of the first keying fingers and the plating fingers may be nickel-nickel electric iron layers. The intermediate connector Φ' may further include a carrier for bottom protection. Formation of layers. The bottom protective layer may have a flattened bottom surface in the aforementioned interposer Φ. Even ten
在前述的中介連接器中， 底保護層與該表面保護層完 在前述的中介連接器中， 層結構’以使該底保護層、 保護層的組合厚度係不大於 該重配置線路結構係可以該 全密封。 該重配置線路結構係可為單 該重配置線路結構與該表面 3〇微米。In the foregoing interposer, the bottom protective layer and the surface protective layer are completed in the foregoing interposer, and the layer structure is such that the combined thickness of the bottom protective layer and the protective layer is not greater than the reconfigured line structure. This is fully sealed. The reconfiguration line structure can be a single reconfigured line structure with the surface 3 microns.
在前述的中介連接器中，該些第-電鍵接指與該些第 二電鍍接指係可完全疊置於該重配置線路結構之上。 β本發明還揭示上述之中介連接器之製造方&，首先， 提供一承載片。接著，形成—底保護層於該承載片上， 該底保護層係為整片狀並具有介於4至8微米之厚度。 灸鼓置重配置線路結構於該底保護層上，該重配 置線路結構係具有至少一層厚度介於4至8微米之線路 層。之後，形成一表面保護層，係覆蓋該重配置線路結 構與該底保護層上，該表面保護層在該重配置線路結構 上的厚度係介於5至6微米，並且該表面保護層係具有 複數個開孔。最後，㉟置複數個第一電鍍接指與第二電 才a於該些開孔内而顯露在同一表面，並經由該重配 201112364 置線路結構而使對應之第一電鍍接指與第二電鍍接指相 互電性連接。其中，該底保護層的形成、該重配置線路 結構的設置與該表面保護層的形成係為半導體製程，以 使其組合厚度係不大於5 〇微米。 由以上技術方案可以看出，本發明之内置於半導體封 裝構造之中介連接器以及其製造方法，具有以下優點與 功效：In the aforementioned interposer, the first and second electro-contact fingers and the second electroplated finger can be completely superposed on the reconfigurable line structure. The present invention also discloses the above-mentioned manufacturer of the intermediate connector & first, a carrier sheet is provided. Next, a bottom protective layer is formed on the carrier sheet, the bottom protective layer being in the form of a sheet and having a thickness of 4 to 8 μm. The moxibustion drum reconfiguration line structure is on the bottom protection layer, the reconfiguration line structure having at least one wiring layer having a thickness of 4 to 8 microns. Thereafter, a surface protective layer is formed covering the reconfigured wiring structure and the bottom protective layer, the surface protective layer has a thickness of 5 to 6 micrometers on the reconfigured wiring structure, and the surface protective layer has Multiple openings. Finally, 35 a plurality of first plating fingers and a second electrode are exposed in the openings to be exposed on the same surface, and the corresponding first plating fingers and the second are provided via the reconfigurable 201112364 wiring structure. Electroplating refers to electrical connection to each other. The formation of the underlevel protection layer, the arrangement of the relocation line structure, and the formation of the surface protection layer are in a semiconductor process such that the combined thickness is no greater than 5 Å. As can be seen from the above technical solutions, the intermediate connector of the present invention built into the semiconductor package structure and the method of manufacturing the same have the following advantages and effects:
可藉由中介連接器内各元件的組合關係作為其中一 技術手段’具有薄化、供打線連接與消除封裝内應 力的功玫，故能使中介連接器之厚度相當薄化，不 會增加封裝構造之晶片堆疊高度且可縮短銲線長度 及線弧高度，而能有效縮小半導體封裝構造之體 積’並有效降低成本。 可藉由十介連接器内各元件的作為其中一技術手 段，重配置線路結構可不位在習知承載板之表面， 可避免因與晶片的熱膨脹係數不匹配導致脫層或勉 曲之問題。 三、可藉由底保護層、重配置線路結構、表面保護層上 及複數個第-電鑛接指與第二電鍵接指之特定心 關係作為其中一技術手辟，你士人* 町于奴使中介連接器相當！ 化’並可提供跳線功能而尤愛你阳。 祐而不需使用長銲墊設計的士 疊式晶片之半導體封裝構造。 【實施方式】 以下將配合所附圖示詳細說明. 飞*月本發明之實施例，然屬 201112364 ，注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之兀件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述》實際實施之數目、形狀及尺寸比例為—種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種内置於半導體封 裝構造之中介連接器舉例說明於第2至4圖，其中第2 圖為其截面示意圖，第3圖為使用該中介連接器之堆疊 式晶片之半導體封裝構造之截面示意圖、第4八至4^圖 為在製程中之元件截面示意圖。該中介連接器2〇〇主要 包含一底保護層2 1 0、一重配置線路結構22〇、一表面保 護層230以及複數個第—電鍍接指241與第二電鍍接指 242。其中，該底保護層21〇、該重配置線路結構22〇與 • 該表面保護層230的組合厚度係不大於50微米，同時具 有薄化、供打線連接與消除封裝内應力的功效故該中 介連接器200為相當薄化，不會增加封裝構造高度且可 縮短銲線長度及線弧高度，而能有效縮小半導體封裝構 造之體積，並有效降低成本。而該中介連接器2〇〇能達 成組合厚度不大於50微米的内部結構詳述如下。 請參閱第2圖所示，該底保護層21〇係為整片狀並具 有介於4至8微米之厚度。該底保護層21〇係可具有一 平坦化的底面211 ’可供將該中介連接器2〇〇設置在其 201112364 他載體上。該底保護層210係為一介電層，其材質係可 選自聚亞醯胺（Polyimide, PI)、聯二苯環丁二稀 (benzocylobutene, BCB) > ABF(Ajinomoto Build - up Film)、雙順丁醯二酸醯亞胺/三氮阱（bt，Bismaleimide triazine)、聯一本環 丁二婦（benzocylobutene, BCB)、液 晶聚合物（Liquid Crystal Polymer)、聚乙稀謎 (Poly(phenylene ether))、聚四氟乙烯（Poly(tetra — fluoroethylene))、芳香尼龍（Arainide)、環氧樹脂、以及 鲁 玻璃纖維所組成之群組之其中之一。較佳係為可為PI、 BCB等絕緣性材料，具有耐熱、耐燃、強度好、厚度薄、 電氣絕緣性佳之特性。由於該底保護層2丨〇之厚度僅有 4至8微来’利用半導體製程之沉積或蒸鍍等塗佈技術 所製造，不相同於習知軟性電路板之可撓曲載膜（厚度約 12.5微米）。 該重配置線路結構220係設置於該底保護層2 1 〇上並 • 具有至少一層厚度介於4至8微米之線路層221。該線 路層221可為任何能將電路導通之金屬，較佳為銅、錫、 鎳、鉻、鈦、銅-鉻合金以及錫-鉛合金中所組成之群組 之一者’更佳則為銅。較佳地，該重配置線路結構22〇 係能以該底保護層210與該表面保護層23 0完全密封， 以避免水氣或外來物污染。該重配置線路結構22〇係可 為單層結構，以使該底保護層210、該重配置線路結構 220與該表面保護層23〇的組合厚度係不大於3〇微米， 而具有更薄之厚度。 201112364 表面保護層230係覆蓋該重配置線路結構220與該 保護層210上，該表面保護層23〇在該重配置線路結 冓 上的厚度係介於5至ό微米，該表面保護層23 〇 之材質係可相同於該底保護I 210。具體而言，該表面 保護層230係具有複數個開孔231。該些第—電鍵接指 241與第二電鍍接指242係設置於該些開孔231内而顯 露在同一表面，並經由該重配置線路結構220而使對應 之第電鍍接指241與第二電鍍接指242相互電性連 接。詳細而言，該些第一電鍍接指241與該些第二電鍍 接242指係可不突出於該表面保護層23〇，而使該些第 電鍍接指241、該些第二電鍍接242與該表面保護層 230在同一平面，以利取放疊置並在該表面保護層a” 之上方可供設置晶片或其他元件。更細部而言該些第 電鍍接指241與該些第二電鍍接指242係可為鎳金電 鍍層。每一第一電鍍接指241係包含一層鎳層241八與 —層金層241Β’該第二電鍍接指242亦包含鎳金兩層結 構。其中鎳層241Α為下層，厚度可為3微米；金層24ιβ 為上層，厚度可為03微米，組合後厚度未超過該表面 保濩層230。並且，該些第一電鍍接指241與該些第二 電鍍接指242係可完全疊置於該重配置線路結構 上即接指之邊緣不超過該重配置線路結構22〇之外（如 第2圖所示），故能承受打線強度。 如第3圖所示，將該中介連接器2〇〇運用在一堆疊式 曰曰片之半導體封裝構造時，該半導體封裝構造的基本架 10 201112364 構與元件可與習知之第i圖結構相同，故相類似元件以 相同圖號標示。該中介連接器200係設置於該第一晶片 10與該第二晶片20之間。該中介連接器200之該重配 置線路結構220係做為該些晶片1〇、20將銲線41、42 連接至該基板30之中繼配線。並藉由該中介連接器2〇〇 而達成該些晶片10、20與該基板30之電性連接。該中 介連接器200係可提供封裝内線路傳導功能並且不需使 用長銲線設計的堆疊式晶片。並且由於該中介連接器 2〇〇不具有承載板’故厚度相當薄化，不會增加封裝構 造高度且可縮短該些銲線41、42與43長度及線弧高度， 而能有效縮小半導體封裝構造之體積，並有效降低成 本。並可避免習知之中介連接器因熱膨脹係數不匹配導 致脫層或輕曲之問題。 本發明之該中介連接器200除了可適用於第3圖之晶 片堆疊之中介物外，還可適用不同的晶片堆疊型態例 如晶片主動面上該中介連接器200與小晶片的並排方式 (Side by Side) 〇 本發明進一步揭示一種前述中介連接器之製造方 法，舉例說明於第4A至4〗圖之製程中元件截面示意圖。 首先，請參閱第4A圖所示，提供一承載片25〇。該 承載片250係可選自玻璃、矽晶片或合金之其中之一， 厚度約為50微米。該承載片25〇係可為大尺寸，如晶圓 尺寸，並具有複數個呈十字交錯之切割道2〇1，用以定 義出該中介連接器2〇〇之形成位置。 201112364 接著，再請參閱第4A圖所示，形成上述之底保護層 210於該承載片250上，可利用一半導體製程之沉積或 蒸鍍等塗佈技術而形成。 之後，請參閱第4B圖所示，形成一種子層260(seed layer)於該底保護層210上’可利用賤鑛（sputtering)方式 沉積而成。該種子層260係提供後續進行電鑛製程所需 之電流傳導路徑’以電鍍形成該重配置線路結構220。 該種子層260可為一薄金層’並全面覆蓋該底保護層 • 210。 之後’請參閱第4C圖所示，於該種子層260上以曝 光（exposing)、顯影（developing)方式形成一具有複數個 開口 5 1之光阻層5〇，且該些開口 5 1係為該重配置線路 結構220的預定形成區域。該光阻層5〇可藉由微影製程 圖案化而形成一光阻圖案》 之後’請參閱第4D圖所示’於該些開口 51上以電 φ 鑛方式設置上述之重配置線路結構220於該底保護層 210上。之後，請參閱第4E圖所示，以去光阻（ph〇t〇resist stripping)方式移除該光阻層5〇。再以蝕刻（etching)方式 移除該種子層260未被該重配置線路結構220覆蓋之外 露部份。 之後，請參閱第4F圖所示，形成上述之表面保護層 230於該重配置線路結構22〇與該底保護層21〇上再 以曝光、顯影方式形成上述之開孔23丨。該些開孔工 局部顯露該重配置線路結構22〇，其係為第一電鍍接指 12 201112364 . 241與第二電艘接指242的預定形成區域。 之後，請參閱第4G圖所示’利用電艘方式設置上述 之第一電鍍接指241與第二電鍍接指242於該些開孔 23 1内而顯露在同一表面，並經由該重配置線路結構220 而使對應之第一電鍍接指241與第二電鍍接指242相互 電性連接。該些第一電鍵接指241與該些第二電鍵接指 242係可為鎳金電鍍層，可分兩次電鍍形成《該些第一 電鍍接指241與該些第二電鍍接242的位置可依需要調 •整。 之後，請參閱第4H圖所示，在該表面保護層230之 上方貼附一研磨黟帶60’並以一磨具7〇進行研磨以移 除該承載片250’並使該底保護層210係具有該平坦化 的底面211。研磨完成之後，該承載片25〇即不存在或 僅殘留極少部分。 最後，請參閱第41圖所示，可利用The combination of the components in the interposer can be used as one of the technical means of thinning, wire bonding and eliminating the stress in the package, so that the thickness of the interposer can be made relatively thin without increasing the package. The constructed wafer stack height can shorten the wire length and the wire arc height, and can effectively reduce the volume of the semiconductor package structure and effectively reduce the cost. By using the components of the ten-connector as one of the technical means, the reconfiguration line structure may not be located on the surface of the conventional carrier board, and the problem of delamination or distortion due to mismatch with the thermal expansion coefficient of the wafer may be avoided. Third, the specific protection relationship between the bottom protective layer, the reconfiguration line structure, the surface protective layer and the plurality of first-electrical joint fingers and the second key contact finger can be used as one of the technical tricks, you Shiren* The slave makes the intermediary connector quite! And can provide jumper function and especially love you. It is not necessary to use a long pad to design a semiconductor package structure for a stacked chip. [Embodiment] The following is a detailed description with reference to the accompanying drawings. The embodiment of the present invention, which is 201112364, is to be understood as a simplified schematic diagram, and the present invention is only illustrated by way of illustration. The basic structure or implementation method, so only the components and combinations related to the case are displayed. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or Exaggerated or simplified processing to provide a clearer description "The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, an intermediate connector built into a semiconductor package structure is illustrated in FIGS. 2 to 4, wherein FIG. 2 is a schematic cross-sectional view thereof, and FIG. 3 is a stacked type using the interposer. A schematic cross-sectional view of a semiconductor package structure of a wafer, and FIGS. 4-8 to 4 are schematic cross-sectional views of components in a process. The interposer 2 〇〇 mainly includes a bottom protection layer 210, a reconfiguration line structure 22, a surface protection layer 230, and a plurality of first-plated fingers 241 and second plating fingers 242. Wherein, the bottom protective layer 21〇, the reconfigured line structure 22〇 and the surface protective layer 230 have a combined thickness of not more than 50 micrometers, and have the functions of thinning, wire bonding and eliminating internal stress of the package. The connector 200 is relatively thin, does not increase the height of the package structure, and can shorten the length of the bonding wire and the height of the wire arc, thereby effectively reducing the size of the semiconductor package structure and effectively reducing the cost. The internal structure of the interposer connector 2 which can be combined to a thickness of not more than 50 μm is detailed below. Referring to Figure 2, the bottom protective layer 21 is a full sheet and has a thickness of between 4 and 8 microns. The bottom protective layer 21 can have a flattened bottom surface 211' for the interposer connector 2 to be placed on its carrier. The bottom protective layer 210 is a dielectric layer, and the material thereof may be selected from polyimide (PI), benzocylobutene (BCB) > ABF (Ajinomoto Build - up Film) , Bis-Butaneimide triazine, Bismaleimide triazine, benzocylobutene (BCB), Liquid Crystal Polymer, Poly (Poly) One of a group consisting of phenylene ether)), poly(tetra-fluoroethylene), aromatic (Arainide), epoxy resin, and ruthenium fiber. Preferably, it is an insulating material such as PI or BCB, and has characteristics of heat resistance, flame resistance, good strength, thin thickness, and good electrical insulation. Since the thickness of the bottom protective layer 2 is only 4 to 8 micrometers, it is manufactured by a coating technique such as deposition or evaporation of a semiconductor process, and is not the same as a flexible carrier film of a conventional flexible circuit board (thickness is about 12.5 microns). The reconfiguration line structure 220 is disposed on the bottom protection layer 21 and has at least one wiring layer 221 having a thickness of 4 to 8 microns. The circuit layer 221 can be any metal that can conduct the circuit, preferably one of a group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy. . Preferably, the reconfiguration line structure 22 can be completely sealed with the surface protection layer 230 by the bottom protection layer 210 to avoid moisture or foreign matter contamination. The reconfiguration line structure 22 can be a single layer structure such that the bottom protection layer 210, the reconfiguration line structure 220 and the surface protection layer 23 are combined to have a thickness of no more than 3 〇 micron, and have a thinner thickness. 201112364 The surface protection layer 230 covers the reconfiguration line structure 220 and the protection layer 210. The surface protection layer 23 has a thickness on the crucible of the reconfiguration line between 5 and ό micrometers. The surface protection layer 23 〇 The material can be the same as the bottom protection I 210. Specifically, the surface protection layer 230 has a plurality of openings 231. The first and second bonding fingers 241 and 242 are disposed in the openings 231 to be exposed on the same surface, and the corresponding first plating fingers 241 and the second are connected via the reconfiguration circuit structure 220. The plated fingers 242 are electrically connected to each other. In detail, the first plated fingers 241 and the second plated contacts 242 may not protrude from the surface protection layer 23, and the first plated fingers 241 and the second plated contacts 242 are The surface protection layer 230 is on the same plane to facilitate stacking and disposing of the wafer or other components above the surface protection layer a". In more detail, the first plating fingers 241 and the second plating The contact finger 242 can be a nickel gold plating layer. Each of the first plating fingers 241 includes a nickel layer 241 and a gold layer 241'. The second plating finger 242 also comprises a nickel-gold two-layer structure. The layer 241 is a lower layer and has a thickness of 3 micrometers; the gold layer 24πβ is an upper layer and has a thickness of 03 micrometers, and the combined thickness does not exceed the surface protective layer 230. And, the first plating fingers 241 and the second layers The plated fingers 242 can be completely superposed on the reconfiguration line structure, that is, the edge of the finger does not exceed the reconfiguration line structure 22 (as shown in Fig. 2), so that it can withstand the wire strength. As shown in the figure, the interposer 2 is applied to a stacked cymbal In the semiconductor package structure, the basic package 10 201112364 of the semiconductor package structure can be the same as the conventional structure of the first embodiment, so similar components are denoted by the same reference numerals. The intermediate connector 200 is disposed on the first wafer 10 The reconfigurable wiring structure 220 of the interposer 200 is used as the relay wirings of the wafers 1 and 20 to connect the bonding wires 41 and 42 to the substrate 30. The interposer 2 is used to electrically connect the wafers 10, 20 to the substrate 30. The interposer 200 is a stacked wafer that provides in-package conduction functions and does not require long wire bonding designs. Moreover, since the interposer 2 does not have a carrier board, the thickness is relatively thin, the package structure height is not increased, and the lengths and arc heights of the bonding wires 41, 42 and 43 can be shortened, thereby effectively reducing the semiconductor package. The volume of the structure is formed, and the cost is effectively reduced, and the problem that the conventional intermediate connector is delaminated or lightly curved due to the mismatch of thermal expansion coefficients can be avoided. The intermediate connector 200 of the present invention is applicable not only to In addition to the interposer of the wafer stack of FIG. 3, different wafer stacking patterns, such as the side by side of the interposer connector 200 and the small wafer, may be applied. The present invention further discloses an intervening connector. The manufacturing method is exemplified by a cross-sectional view of the components in the process of Figures 4A to 4. In the first embodiment, a carrier sheet 25 is provided as shown in Fig. 4A. The carrier sheet 250 can be selected from glass, germanium wafer or One of the alloys has a thickness of about 50 microns. The carrier sheet 25 can be of a large size, such as a wafer size, and has a plurality of cross-staggered dicing streets 〇1 for defining the interposer. 2〇〇 The formation position. 201112364 Next, referring to FIG. 4A, the bottom protective layer 210 is formed on the carrier sheet 250 by a coating process such as deposition or evaporation of a semiconductor process. Thereafter, referring to FIG. 4B, a seed layer 260 is formed on the bottom protective layer 210, which can be deposited by sputtering. The seed layer 260 provides a current conducting path </ RTI> required for subsequent electrical ore processing to form the reconfigured wiring structure 220 by electroplating. The seed layer 260 can be a thin gold layer' and completely cover the bottom protective layer. Then, as shown in FIG. 4C, a photoresist layer 5 having a plurality of openings 51 is formed on the seed layer 260 by exposing and developing, and the openings 51 are The predetermined formation area of the reconfiguration line structure 220. The photoresist layer 5 can be patterned by a lithography process to form a photoresist pattern. After that, please refer to FIG. 4D to provide the above-mentioned reconfiguration line structure 220 in an electrical φ manner. On the bottom protective layer 210. After that, as shown in FIG. 4E, the photoresist layer 5 is removed by ph〇t〇resist stripping. The seed layer 260 is removed by an etching method and is not covered by the reconfigured wiring structure 220. Thereafter, as shown in Fig. 4F, the surface protective layer 230 is formed on the rearrangement line structure 22 and the bottom protective layer 21, and the opening 23 is formed by exposure and development. The reamer partially exposes the reconfiguration line structure 22A, which is a predetermined formation area of the first plating finger 12 201112364 . 241 and the second electric boat finger 242. After that, as shown in FIG. 4G, the first plating finger 241 and the second plating finger 242 are disposed on the same surface by the electric boat, and are exposed on the same surface through the reconfiguration line. The structure 220 electrically connects the corresponding first plating fingers 241 and the second plating fingers 242 to each other. The first electrical contact fingers 241 and the second electrical contact fingers 242 may be nickel-plated plating layers, and may be formed by two times to form a position of the first plating fingers 241 and the second plating contacts 242. Can be adjusted as needed. Thereafter, as shown in FIG. 4H, a polishing tape 60' is attached over the surface protection layer 230 and ground by a grinding tool 7 to remove the carrier sheet 250' and the bottom protection layer 210. The flat bottom surface 211 is provided. After the completion of the grinding, the carrier sheet 25 is absent or only a small portion remains. Finally, please refer to Figure 41, available
著該些切割道201切割而分離成單體的中介連接 200。在不同實施例中，切割之方法係可採用雷射光。 成切割之後，可撕除該切割膠帶6〇，使該些第一電鍍 指241與該些第二錢接指^顯露出，並得到如二 圖所示超薄型態(不大於50微米)且平坦 200 〇 在上述之製造方法中’該底保護層Η。的形成、該 線路結構220的設置與該表㈣護層2 為半導_ ’以使其組合厚度係不大於5〇微米，故 13 201112364 使該中介連接器200之厚度相當薄化。 在本發明之第二具體實施例中，如第5圖所示，揭示 另一種内置於半導體封裝構造之中介連接器。在該實施 例中，該中介連接器3〇〇係保留原本在第一實施例之第 4H圖中移除之承載片25〇,即不實施研磨承載片25〇之 步驟，而保留該承載片250,以使其做為該底保護層21〇 之支撐’並可增加整體之硬度。然該承載片25〇之熱膨 脹係數相同於晶片之熱膨脹係數，以消除封裝内應力。 在本發明之第三具體實施例中，揭示另一種内置於半 導體封裝構造之中介連接器，說明於第6圖之截面示意 圖，其中與第一實施例相同的主要元件將以相同符號標 示之。特別的是’該重配置線路結構220係具有雙層線 路’另包含不在同一水平面之線路層221與422，該些 線路層221與422係以該底保護層210與該表面保護層 23 0完全密封，可不受外界水氣或外來物污染。並且該 些線路層221與422可視需要而彈性配置。 以上所述’僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上’然而並非用以限定本發明，任何熟悉本項技 術者’在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾’均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖：為習知的一種堆疊式晶片之半導體封裝構造之 14 201112364 截面示意圖。 第2圖 :依據本發明之第—且 八體貫施例的一種内置於半The scribe lines 201 are cut to separate into a single intervening connection 200. In various embodiments, the method of cutting may employ laser light. After the cutting, the cutting tape 6 can be peeled off, and the first plating fingers 241 and the second money fingers are exposed, and the ultra-thin state (not more than 50 micrometers) is obtained as shown in FIG. And flat 200 ' in the above manufacturing method 'the bottom protective layer Η. The formation of the circuit structure 220 and the protective layer 2 of the table (4) are semi-conductive _' such that the combined thickness is no more than 5 〇 micrometers, so that the thickness of the interposer 200 is considerably thinner. In a second embodiment of the present invention, as shown in Fig. 5, another intermediate connector built into a semiconductor package structure is disclosed. In this embodiment, the interposer 3 retains the carrier sheet 25 that was originally removed in the fourth embodiment of the first embodiment, that is, the step of not performing the grinding of the carrier sheet 25, but retaining the carrier sheet 250, in order to make it the support of the bottom protective layer 21' and increase the overall hardness. However, the thermal expansion coefficient of the carrier sheet 25 is the same as the thermal expansion coefficient of the wafer to eliminate the stress in the package. In the third embodiment of the present invention, another intermediate connector built in a semiconductor package construction is disclosed, which is illustrated in the cross-sectional view of Fig. 6, in which the same principal elements as those of the first embodiment will be denoted by the same reference numerals. In particular, the 'relocation line structure 220 has a double layer line' and further includes circuit layers 221 and 422 which are not in the same horizontal plane. The circuit layers 221 and 422 are completely separated from the surface protection layer 230 by the bottom protection layer 210. Sealed, free from external moisture or foreign matter. And the circuit layers 221 and 422 can be flexibly configured as needed. The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and the present invention has been disclosed in the preferred embodiments. Any simple modifications, equivalent changes, and modifications made by the present invention within the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a semiconductor package structure of a stacked wafer. Figure 2: A built-in half in accordance with the first and eighth embodiments of the present invention
導體封裝構造之φ A 第3圖 中介連接器之截面示意圖。 依據本發明之第— 具體實施例的使用該中介連 接器之堆疊式晶片 半導體封裝構造之截面示 意圖。 第4A至41圖：仿擔士找π ^ 8之第一具體實施例的該中介 連接器在製㈣之元件“ 第5圖：依據本發明之第二 意圓。 道触以 、實施例的一種内置於半 導體封裝構造之中介連接器 ^ m · ^ » 之截面示意圖。 第6圖.料本發明之第三具體實 導微的一種内置於半 導體封裝構造之中介連接器 【主要元件符號說明】 哉面示意圖。 10 第一晶片 11 第一銲墊 20 第二晶片 21 第二鲜塾 30 基板 41 銲線 42 銲線 50 光阻層 51 開口 60 研磨膠帶 70 磨具 80 切割刀具 100 中介連接器 120 重配置線路結構 200 中介連接器 201 切割道 210 底保護層 211 底面 43 銲線 15 201112364 線路層 - 220重配置線路結構 221 • 230表面保護層 231開孔 241第一電鍍接指 241A鎳層 241B金層 242第二電鍍接指 250承載片 260種子層 300中介連接器 ® 400中介連接器422線路層φ A of the conductor package structure Fig. 3 Schematic diagram of the cross section of the intermediate connector. A cross-sectional view of a stacked wafer semiconductor package construction using the interposer in accordance with a first embodiment of the present invention. Figures 4A to 41: The intermediate connector of the first embodiment of the imaginary actor is found to be the component of the fourth embodiment. Figure 5: The second meaning according to the present invention. A schematic cross-sectional view of an intermediate connector ^m · ^ » built into a semiconductor package structure. Fig. 6 is a third embodiment of the present invention. A dielectric connector built into a semiconductor package structure [Major component symbol description] 10 First wafer 11 First pad 20 Second wafer 21 Second fresh glass 30 Substrate 41 Solder wire 42 Solder wire 50 Photoresist layer 51 Opening 60 Abrasive tape 70 Abrasive tool 80 Cutting tool 100 Intermediary connector 120 Heavy Configuration Line Structure 200 Interposer 201 Cutting Channel 210 Bottom Protective Layer 211 Bottom Surface 43 Bonding Wire 15 201112364 Circuit Layer - 220 Reconfiguration Line Structure 221 • 230 Surface Protection Layer 231 Opening 241 First Plating Finger 241A Nickel Layer 241B Gold Layer 242 second plated finger 250 carrier sheet 260 seed layer 300 interposer connector 400 interposer connector 422 circuit layer
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