TWI677956B - A universal transfer layer for semiconductor packaging structure - Google Patents
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Abstract
一種用於半導體封裝結構的萬用轉接電路層，其是安置在晶片上，而晶片是安置在基板上，且所述萬用轉接電路層包括延伸訊號區、至少一中繼接點區、接地區、電源區以及電氣絕緣層，其中延伸訊號區、中繼接點區、接地區及電源區是由導電材料構成而具有導電性，並位於電氣絕緣層的上表面。此外，延伸訊號區包含多個訊號線以及多個接墊，而中繼接點區包含多個中繼接點。尤其是，每個訊號線之間是平行排列，並連接至少一接墊，而接墊、中繼接點、接地區、電源區及該接腳可選擇式藉由引線而電氣連接至該基板之連接阜。A universal switching circuit layer for a semiconductor package structure is disposed on a wafer, and the chip is disposed on a substrate. The universal switching circuit layer includes an extended signal area and at least one relay contact area. , Connection area, power supply area, and electrical insulation layer, among which the extended signal area, relay contact area, connection area, and power supply area are made of conductive materials and have conductivity, and are located on the upper surface of the electrical insulation layer. In addition, the extended signal area includes multiple signal lines and multiple pads, and the relay contact area includes multiple relay contacts. In particular, each signal line is arranged in parallel and is connected to at least one pad, and the pad, the relay contact, the contact area, the power supply area, and the pin are optionally electrically connected to the substrate through a lead. It connects Fu.
Description
本發明涉及一種用於半導體封裝結構的萬用轉接電路層，尤其是利用接墊、中繼接點、接地區、電源區及接腳而依據晶片的電氣功能藉相對應的引線而電氣連接。The invention relates to a universal switching circuit layer for a semiconductor package structure, and particularly uses a pad, a relay contact, a contact area, a power supply area, and a pin to be electrically connected by corresponding leads according to the electrical function of the chip. .
在一般習知技術的封裝制程中，需要利用焊線或打線(wire bonding)以實現半導體的積體電路(IC)及導線架之間的電氣連接，而打線通常是使用金線、鋁線或銅線，將積體電路的接腳連接至導線架的引腳，最後進行灌膠固化而完成封裝。In the packaging process of the conventional technology, it is necessary to use solder wires or wire bonding to realize the electrical connection between the semiconductor integrated circuit (IC) and the lead frame. The wire is usually made of gold, aluminum or The copper wire connects the pins of the integrated circuit to the pins of the lead frame, and is finally potted and cured to complete the package.
積體電路的接腳必需隨著內部電路的設計而配置，藉以達到最佳性能，而當不同接腳與相對應引腳之間的打線發生交錯時，很容易發生短路，或者，如果接腳與引腳之間的打線距離太長，則在後續壓模處理時，焊線很容易受到過大的模流衝壓而偏移，影響電性，甚至短路而失效。The pins of the integrated circuit must be configured with the design of the internal circuit to achieve the best performance. When the wiring between different pins and corresponding pins is staggered, it is easy to short circuit, or if the pins are The distance between the wire and the lead is too long. In the subsequent die processing, the bonding wire is easily offset by excessive die current stamping, which affects electrical properties and even fails due to short circuit.
因此，很需要一種創新的用於半導體封裝結構的萬用轉接電路層，不僅可簡化打線的設計，縮短打線距離，還能避免發生交錯，藉以解決上述習知技術的問題。Therefore, there is a great need for an innovative universal switching circuit layer for a semiconductor package structure, which not only simplifies the design of the wiring, shortens the wiring distance, but also avoids interleaving, thereby solving the problems of the conventional techniques described above.
針對習知技術的不足，本發明的目的是提供一種用於半導體封裝結構的萬用轉接電路層。In view of the shortcomings of the conventional technology, an object of the present invention is to provide a universal switching circuit layer for a semiconductor package structure.
為實現以上發明目的，本發明採用了如下所述的技術方案：In order to achieve the above object of the invention, the present invention adopts the following technical solutions:
本發明揭露一種用於半導體封裝結構的萬用轉接電路層，其包括：一延伸訊號區，包含多個訊號線以及多個接墊，該等訊號線是平行排列，而每個該等訊號線系連接至少一接墊，且不同的該訊號線所連接的相對應接墊是配置成相互間隔開而不接觸；至少一中繼接點區，每個該中繼接點區包含多個中繼接點；一接地區；一電源區；以及一電氣絕緣層，具電氣絕緣性，且該延伸訊號區、該至少一中繼接點區、該接地區及該電源區是由一導電材料構成而具有導電性，並位於該電氣絕緣層的一上表面；其中該萬用轉接電路層是安置在一晶片的一上表面，且該晶片進一步安置在一基板的一上表面，該基板具有一線路圖案及多個接腳，該萬用轉接電路層之該接墊、該中繼接點、該接地區、該電源區及該接腳，可選擇式藉由引線而電氣連接至該基板之連接阜。The invention discloses a universal switching circuit layer for a semiconductor package structure, which includes: an extended signal area including a plurality of signal lines and a plurality of pads, the signal lines are arranged in parallel, and each of the signals The line is connected to at least one pad, and the corresponding pads connected to different signal lines are configured to be spaced apart from each other without contact; at least one relay contact area, each of which includes a plurality of relay contact areas. A relay contact; a connection area; a power supply area; and an electrical insulation layer having electrical insulation, and the extended signal area, the at least one relay contact area, the connection area, and the power supply area are electrically conductive The material is conductive and is located on an upper surface of the electrical insulation layer. The universal switching circuit layer is disposed on an upper surface of a wafer, and the wafer is further disposed on an upper surface of a substrate. The substrate has a circuit pattern and a plurality of pins, and the pad, the relay contact, the connection area, the power supply area, and the pin of the universal conversion circuit layer can be electrically connected by leads. To the substrate.
較佳的， 該至少一中繼接點區是配置在該萬用轉接電路層的一左側邊緣區域、一頂部邊緣區域及一右側邊緣區域。Preferably, the at least one relay contact area is disposed on a left edge area, a top edge area, and a right edge area of the universal switching circuit layer.
較佳的， 該接地區以及該電源區是配置成相鄰且不接觸。Preferably, the connection area and the power supply area are configured to be adjacent and not in contact.
較佳的， 該等訊號線所連接的該至少一接墊是配置成波浪狀排列。Preferably, the at least one pad connected to the signal lines is arranged in a wavy arrangement.
較佳的， 該等訊號線所連接的該至少一接墊是配置成平行狀排列。Preferably, the at least one pad connected to the signal lines is arranged in a parallel arrangement.
較佳的， 該接地區及該電源區為長條形。Preferably, the connection area and the power supply area are elongated.
在本發明的一實施例中， 該晶片系為一快閃記憶體。In one embodiment of the present invention, the chip is a flash memory.
較佳的， 該基板或該快閃記憶體上設有一控制器，該控制器具有多個連接墊，該萬用轉接電路層之該接墊、該中繼接點、該接地區、該電源區及該接點，可選擇式藉由引線而電氣連接至該基板之該連接阜、該快閃記憶體或該控制器之連接墊。Preferably, a controller is provided on the substrate or the flash memory, the controller has a plurality of connection pads, the pads of the universal transfer circuit layer, the relay contacts, the connection area, the The power supply area and the contact can be electrically connected to the connection module, the flash memory, or the connection pad of the controller through a lead wire.
本發明揭露另一種用於半導體封裝結構的萬用轉接電路層，其包括：一延伸訊號區，包含多個訊號線以及多個接墊，該等訊號線是平行排列，而每個該等訊號線系連接至少一接墊，且不同的該訊號線所連接的相對應接墊是配置成相互間隔開而不接觸；至少一中繼接點區，每個該中繼接點區包含多個中繼接點；一接地區；一電源區；以及一電氣絕緣層，具電氣絕緣性，且該延伸訊號區、該至少一中繼接點區、該接地區及該電源區是由一導電材料構成而具有導電性，並位於該電氣絕緣層的一上表面； 其中該萬用轉接電路層是安置在一第一晶片的一上表面，且該第一晶片進一步安置在一導線架之一承放座的一上表面，該萬用轉接電路層之該接墊、該中繼接點、該接地區、該電源區及該接腳可選擇式藉由引線而電氣連接至該導線架之一引腳。The invention discloses another universal switching circuit layer for a semiconductor package structure, which includes: an extended signal area including a plurality of signal lines and a plurality of pads, the signal lines are arranged in parallel, and each of the The signal line is connected to at least one pad, and the corresponding pads connected to different signal lines are configured to be spaced apart from each other without contact; at least one relay contact area, each of which A relay contact; a connection area; a power supply area; and an electrical insulation layer having electrical insulation, and the extended signal area, the at least one relay contact area, the connection area and the power supply area are formed by a The conductive material layer is conductive and is located on an upper surface of the electrical insulation layer; wherein the universal switching circuit layer is disposed on an upper surface of a first chip, and the first chip is further disposed on a lead frame. An upper surface of a receiving seat, the pad, the relay contact, the connection area, the power supply area, and the pin of the universal transfer circuit layer can be electrically connected to the electrical connection by wires. One lead of the lead frame.
較佳的， 該至少一中繼接點區是配置在該萬用轉接電路層的一左側邊緣區域、一頂部邊緣區域及一右側邊緣區域。Preferably, the at least one relay contact area is disposed on a left edge area, a top edge area, and a right edge area of the universal switching circuit layer.
較佳的， 該接地區以及該電源區是配置成相鄰且不接觸。Preferably, the connection area and the power supply area are configured to be adjacent and not in contact.
較佳的， 該等訊號線所連接的該至少一接墊是配置成波浪狀排列。Preferably, the at least one pad connected to the signal lines is arranged in a wavy arrangement.
較佳的， 該等訊號線所連接的該至少一接墊是配置成平行狀排列。Preferably, the at least one pad connected to the signal lines is arranged in a parallel arrangement.
較佳的， 該接地區及該電源區為長條形。Preferably, the connection area and the power supply area are elongated.
較佳的， 該第一晶片與該承放座之間設置一第二晶片，該萬用轉接電路層之該接墊、該中繼接點、該接地區、該電源區可選擇式藉由引線電氣連接該導線架之一引腳與第二晶片之連接墊。Preferably, a second chip is disposed between the first chip and the receiving seat, and the pad, the relay contact, the connection area, and the power supply area of the universal transfer circuit layer can be borrowed by a selectable borrowing method. One lead of the lead frame and the connection pad of the second chip are electrically connected by the leads.
因此，較之習知技術，本發明的優點包括：本發明的萬用轉接電路層可提供基板、晶片之間的訊號轉接功能，所以不需在基板、晶片之間直接進行打線，能大幅簡化引線的配置，提高打線良率，並縮短引線的距離，改善電氣訊號的傳輸品質，同時還能避免引線交錯，有效防止發生訊號短路而導致功能異常或甚至失效。Therefore, compared with the conventional technology, the advantages of the present invention include: The universal transfer circuit layer of the present invention can provide a signal transfer function between the substrate and the wafer, so there is no need to directly wire between the substrate and the wafer. It greatly simplifies the configuration of leads, improves the yield of wire bonding, shortens the distance of leads, improves the transmission quality of electrical signals, and can avoid lead interleaving, which effectively prevents signal short circuits from causing abnormal functions or even failure.
此外，本發明的萬用轉接電路層具較高的設計靈活性，能大幅減少開發轉接板的設計成本，尤其是並不局限於特定的晶片設計，所以本發明可運用在各種晶片上或與其搭配，因而提升應用彈性並擴大應用領域。In addition, the universal switching circuit layer of the present invention has high design flexibility, which can greatly reduce the design cost of developing the switching board, especially not limited to a specific chip design, so the present invention can be applied to various chips Or match it, thus increasing application flexibility and expanding application fields.
鑒於習知技術中的不足，本案發明人經長期研究和大量實踐，得以提出本發明的技術方案。以下結合附圖及更為具體的實施例對本發明的技術方案、其實施過程及原理等作進一步清楚、完整的解釋說明。In view of the shortcomings in the conventional technology, the inventor of the present case was able to propose the technical solution of the present invention through long-term research and a lot of practice. The technical solution, the implementation process and the principle of the present invention will be further clearly and completely explained with reference to the accompanying drawings and more specific embodiments.
以下配合圖示及元件符號對本發明之實施方式做更詳細的說明，俾使熟習該項技藝者在研讀本說明書後能據以實施。The following describes the embodiments of the present invention in more detail with illustrations and component symbols, so that those skilled in the art can implement them after studying this specification.
請參閱圖1，本發明實施例用於半導體封裝結構的萬用轉接電路層的示意圖。如圖1所示，本發明實施例的萬用轉接電路層10包括延伸訊號區11、至少一中繼接點區12、接地區13、電源區14以及電氣絕緣層15，其中延伸訊號區11、中繼接點區12、接地區13及電源區14是由導電材料構成而具有導電性，並位於電氣絕緣層15的上表面。進一步，上述的延伸訊號區11包含多個訊號線11A以及多個接墊11B，其中該等訊號線11A是平行排列，而每個訊號線11A連接至少一接墊11B，且不同的訊號線11A所連接的相對應接墊11B是配置成相互間隔開而不接觸。此外，中繼接點區12包含多個中繼接點12A，而電氣絕緣層15是具電氣絕緣性。尤其，延伸訊號區11、中繼接點區12、接地區13及電源區14是由導電材料構成而具有導電性，並位於電氣絕緣層15的上表面。Please refer to FIG. 1, which is a schematic diagram of a universal transfer circuit layer for a semiconductor package structure according to an embodiment of the present invention. As shown in FIG. 1, the universal switching circuit layer 10 according to the embodiment of the present invention includes an extended signal area 11, at least one relay contact area 12, a connection area 13, a power supply area 14, and an electrical insulation layer 15, among which the extended signal area 11. The relay contact area 12, the contact area 13, and the power supply area 14 are made of a conductive material and have conductivity, and are located on the upper surface of the electrical insulation layer 15. Further, the above-mentioned extended signal area 11 includes a plurality of signal lines 11A and a plurality of pads 11B, wherein the signal lines 11A are arranged in parallel, and each signal line 11A is connected to at least one pad 11B, and a different signal line 11A The connected corresponding pads 11B are configured to be spaced apart from each other without contact. In addition, the relay contact area 12 includes a plurality of relay contacts 12A, and the electrical insulation layer 15 is electrically insulating. In particular, the extended signal area 11, the relay contact area 12, the contact area 13 and the power supply area 14 are made of a conductive material and have conductivity, and are located on the upper surface of the electrical insulation layer 15.
更加具體而言，圖1中的萬用轉接電路層10是示範性的表示共有16個訊號線11A，且分成 4組，亦即每一組包含4個訊號線11A，其中每個訊號線11A各自連接多個接墊11B，因而很明顯的，相鄰二訊號線11A的相對應接墊11B是不在同一水平位置，而是具有高低差，所以整體上，所有訊號線11A是比如以自左而右的由上往下之排列方式而重複多次，藉以形成上下起伏的波浪狀。這種波浪狀的接墊11B可以解決晶片20在打線時發生交錯的問題。More specifically, the universal switching circuit layer 10 in FIG. 1 is an exemplary representation that there are a total of 16 signal lines 11A and are divided into 4 groups, that is, each group includes 4 signal lines 11A, and each signal line 11A is connected to a plurality of pads 11B, so it is obvious that the corresponding pads 11B of two adjacent signal lines 11A are not at the same horizontal position, but have a height difference. Therefore, as a whole, all signal lines 11A are The left-to-right arrangement from top to bottom is repeated multiple times to form a wave-like undulation. Such a wave-shaped pad 11B can solve the problem that the chip 20 is staggered during wire bonding.
此外，中繼接點區12的每個中繼接點12A都可用來轉跳線，能避免引線40的距離過長而影響打線的良率，或產生跨線的風險。再者，由於接地區13及電源區14是設計成長條形，所以在跟晶片20打線時皆不會發生交錯。整體而言，本發明可提供應用上最短的打線路徑。In addition, each relay contact 12A in the relay contact area 12 can be used to transfer jumpers, which can avoid that the distance of the lead 40 is too long, which affects the yield of the wiring or the risk of cross-line. In addition, since the connection area 13 and the power supply area 14 are designed as long bars, no interleaving will occur when wiring with the chip 20. Overall, the present invention can provide the shortest wire routing path in applications.
如圖2所示，本發明之萬用轉接電路層10之相鄰二訊號線11A及接墊11B可視電性連接需要，設計為相互平行排列，然不限於此，萬用轉接電路層為相鄰二訊號線11A及接墊11B可為規則或不規則幾何形狀的組合排列之設計。As shown in FIG. 2, the two adjacent signal lines 11A and pads 11B of the universal transfer circuit layer 10 of the present invention are designed to be arranged in parallel with each other depending on the electrical connection requirements, but are not limited to this. The universal transfer circuit layer The design is that the two adjacent signal lines 11A and the pads 11B can be arranged in a combination of regular or irregular geometric shapes.
如圖3及圖4所示，為利用本發明一典型實施例的萬用轉接電路層所完成的半導體封裝結構的上視圖與剖視圖，在此半導體封裝結構中，本發明的萬用轉接電路層10是安置在晶片20的上表面，而晶片20是進一步安置在基板30的上表面，進而由萬用轉接電路層10提供晶片20及基板30之間的電氣訊號轉接功能，使得萬用轉接電路層30之該接墊11B、該中繼接點12A、中繼接點區12之該接地區12、該電源區13可選擇式藉由引線40而電氣連接至該基板30之連接阜33。如圖3所示，基板30之連接阜33電氣連接該電源區14，系利用引線40經由同一訊號線11A上之相鄰特定距離的接墊11B，中繼電氣連接該基板30之連接阜33與該電源區14，以防止使用單一引線40過長而產生的變形，改善電氣訊號的傳輸品質，同時還能避免引線40交錯，有效防止發生訊號短路而導致功能異常或甚至失效。As shown in FIG. 3 and FIG. 4, a top view and a cross-sectional view of a semiconductor package structure completed by using a universal transfer circuit layer of a typical embodiment of the present invention. In this semiconductor package structure, the universal transfer of the present invention The circuit layer 10 is disposed on the upper surface of the wafer 20, and the wafer 20 is further disposed on the upper surface of the substrate 30. The universal switching circuit layer 10 provides an electrical signal switching function between the wafer 20 and the substrate 30, so that The contact pad 11B, the relay contact 12A, the contact area 12 of the relay contact area 12, and the power supply area 13 of the universal transfer circuit layer 30 can be electrically connected to the substrate 30 through the lead 40 optionally. Of connection Fu 33. As shown in FIG. 3, the connection between the substrate 30 and the fu 33 is electrically connected to the power supply area 14, and the lead 40 is used to relay the electrical connection to the connection fu 33 of the substrate 30 through the pad 11B at a specific distance on the same signal line 11A. With the power supply region 14, to prevent the deformation caused by the single lead 40 being too long, to improve the transmission quality of the electrical signal, and to prevent the leads 40 from interleaving, it can effectively prevent the signal short circuit from causing abnormal functions or even failure.
如圖5及圖6所示，分別為依據本發明之另一半導體封裝結構之上視圖及剖視圖，並請一併參閱圖1。此實施例中，半導體封裝結構具有導線架34，其中導線架34包括一承放座35及一引腳36。本發明之萬用轉接電路層10可安置在第一晶片20的上表面，第一晶片20是進一步安置在第二晶片21上，而第二晶片21放置於導線架34之承放座35且並可依據第一晶片20及第二晶片21的電氣功能，可選擇式將引線40分別電氣連接萬用轉接電路層10之接墊11B、中繼接點12A、接地區13、電源區14與第二晶片21之連接墊22及導線架34之引腳36、接腳32。As shown in FIG. 5 and FIG. 6, respectively, a top view and a cross-sectional view of another semiconductor package structure according to the present invention, and please refer to FIG. 1 together. In this embodiment, the semiconductor package structure has a lead frame 34, wherein the lead frame 34 includes a receiving base 35 and a pin 36. The universal switching circuit layer 10 of the present invention can be disposed on the upper surface of the first wafer 20, the first wafer 20 is further disposed on the second wafer 21, and the second wafer 21 is disposed on the receiving seat 35 of the lead frame 34. And according to the electrical functions of the first chip 20 and the second chip 21, the lead wires 40 can be electrically connected to the pads 11B, the relay contacts 12A, the connection area 13 and the power supply area of the universal transfer circuit layer 10 respectively. 14 is connected to the pad 22 of the second chip 21 and the pins 36 and 32 of the lead frame 34.
因此本發明用於半導體封裝結構的萬用轉接電路層，適用於各類半導體封裝結構，如雙線內封裝組(DIP)、塑膠附引線晶片承座(PLCC)、四角平板封裝組(QFP)、低外形四角平板封裝組(LQFP)、薄型小型外框封裝組(TSOP)、薄型四角平板封裝組(TQFP)、帶承座封裝組(TCP)、球珠格狀陣列(BGA)、晶片尺寸級封裝組(CSP)、四角平板非引線封裝組(QFN)、小型外框非引線封裝組(SON)、引線框架BGA(LF-BGA)、模組陣列封裝組型的BGA(MAP-BGA) 及記憶卡(Memory Card)等之慣用公知的半導體封裝結構。Therefore, the universal switching circuit layer used in the semiconductor packaging structure of the present invention is suitable for various types of semiconductor packaging structures, such as a two-wire inner package group (DIP), a plastic leaded chip holder (PLCC), and a quadrangular flat package group (QFP ), Low Profile Quadrangular Flat Panel Package (LQFP), Thin Small Outline Frame Package (TSOP), Thin Quad Flat Package (TQFP), Mounted Package (TCP), Ball Grid Array (BGA), Chip Dimensional package group (CSP), quad flat panel non-lead package group (QFN), small frame non-lead package group (SON), lead frame BGA (LF-BGA), module array package group type BGA (MAP-BGA) ) And memory card (Memory Card) and other conventional semiconductor package structures.
進一步參考圖7及圖8之上視圖及剖視圖，分別為利用本發明實施例萬用轉接電路層所完成的又一半導體封裝結構的示意圖，並請一併參閱圖1。此半導體封裝結構中，是包含本發明的萬用轉接電路層10、基板30、控制器60以及快閃記憶體70，其中萬用轉接電路層10是當作基板30、控制器60、快閃記憶體70之間的訊號轉接媒介，同時，利用相對應的引線41而連接。Further referring to the upper and cross-sectional views of FIG. 7 and FIG. 8, which are schematic diagrams of another semiconductor package structure completed by using the universal switching circuit layer according to the embodiment of the present invention, and please refer to FIG. 1 together. The semiconductor package structure includes the universal transfer circuit layer 10, the substrate 30, the controller 60, and the flash memory 70 of the present invention. The universal transfer circuit layer 10 is used as the substrate 30, the controller 60, The signal switching medium between the flash memories 70 is connected at the same time by corresponding leads 41.
進一步而言，快閃記憶體70是安置在基板30的上表面，且萬用轉接電路層10以及控制器60是安置在快閃記憶體70的上表面。再者，位於快閃記憶體70上控制器60包含多個連接墊62，其中萬用轉接電路層10及控制器60是分隔開而不相接觸。再者請參考如圖9之半導體封裝結構，其快閃記憶體70與控制器60可以視需要安置於基板30上，非如圖8所示快閃記憶體70與控制器60為堆疊的方式安置於基板30上。具體而言，圖8及圖9之控制器60利用相對應的引線41以打線方式而連接到萬用轉接電路層10及基板30，比如控制器60的某些連接墊62可連接到萬用轉接電路層10的相對應多個中繼接點12A，而另一些連接墊62可連接到基板30的相對應多個連接阜33，使得控制器60可經由萬用轉接電路層10的訊號轉接而電氣連接至基板30。Further, the flash memory 70 is disposed on the upper surface of the substrate 30, and the universal switching circuit layer 10 and the controller 60 are disposed on the upper surface of the flash memory 70. Furthermore, the controller 60 located on the flash memory 70 includes a plurality of connection pads 62, wherein the universal transfer circuit layer 10 and the controller 60 are separated from each other without contact. Furthermore, please refer to the semiconductor package structure shown in FIG. 9. The flash memory 70 and the controller 60 can be placed on the substrate 30 as required. The flash memory 70 and the controller 60 are not stacked as shown in FIG. 8. Placed on the substrate 30. Specifically, the controller 60 in FIG. 8 and FIG. 9 is connected to the universal switching circuit layer 10 and the substrate 30 in a wired manner by using corresponding leads 41. For example, some connection pads 62 of the controller 60 can be connected to the universal conversion circuit A plurality of relay contacts 12A corresponding to the transfer circuit layer 10 are used, while other connection pads 62 can be connected to the corresponding multiple connection contacts 33 of the substrate 30, so that the controller 60 can pass through the universal transfer circuit layer 10 The signal is transferred and electrically connected to the substrate 30.
整體而言，萬用轉接電路層10的每個接墊11B、每個中繼接點12A、接地區13、電源區14可選擇式藉是藉由相對應的引線而電氣連接基板30的連接阜33、控制器60的連接墊62或快閃記憶體70，換言之，萬用轉接電路層10的主要功效在於提供基板30、快閃記憶體70以及控制器60之間的電氣連接，使得快閃記憶體70不需直接打線到基板30、控制器60，因而可縮短打線距離，並簡化打線配置，同時避免發生打線交錯而影響電氣性能。再者，上述的半導體封裝結構很適合應用於記憶卡的封裝領域，不過並未受限於此。Generally speaking, each of the pads 11B, each relay contact 12A, the connection area 13, and the power supply area 14 of the universal transfer circuit layer 10 can be electrically connected to the substrate 30 through corresponding leads. The connection pad 62 or the flash memory 70 connecting the Fu 33 and the controller 60, in other words, the main function of the universal transfer circuit layer 10 is to provide an electrical connection between the substrate 30, the flash memory 70, and the controller 60. As a result, the flash memory 70 does not need to be wired directly to the substrate 30 and the controller 60, so that the wiring distance can be shortened, and the wiring configuration is simplified, while avoiding interleaving and affecting electrical performance. Furthermore, the above-mentioned semiconductor package structure is very suitable for application in the packaging field of memory cards, but it is not limited thereto.
綜上所述，本發明的主要特點在於利用萬用轉接電路層提供訊號轉接功能，萬用轉接電路層是藉引線而電氣連接至基板，所以不需在基板、晶片之間直接進行打線，可大幅簡化引線的配置，提高打線良率，並縮短引線的距離，改善電氣訊號的傳輸品質，同時還能避免引線交錯，有效防止發生訊號短路而導致功能異常或甚至失效。In summary, the main feature of the present invention is to provide a signal transfer function by using a universal transfer circuit layer. The universal transfer circuit layer is electrically connected to the substrate by a lead, so there is no need to directly perform the transfer between the substrate and the chip. Wire bonding can greatly simplify the configuration of leads, improve the yield of wire bonding, shorten the distance between leads, improve the transmission quality of electrical signals, and avoid lead interleaving, which can effectively prevent signal short circuits from causing abnormal functions or even failure.
本發明的另一特點在於利用萬用轉接電路層提供基板、快閃記憶體、控制器之間的電氣轉接功能，其中萬用轉接電路層、控制器是在快閃記憶體上，且快閃記憶體電氣連接至基板的線路圖案。由於整結構的引線佈局非常簡化，很適合應用於記憶卡或需要高度整合及更加輕薄短小產品的封裝處理。Another feature of the present invention is that the universal transfer circuit layer is used to provide the electrical transfer function between the substrate, the flash memory, and the controller. The universal transfer circuit layer and the controller are on the flash memory. And the flash memory is electrically connected to the circuit pattern of the substrate. Because the lead structure of the whole structure is very simplified, it is very suitable for the packaging process of memory cards or products that require high integration and thinner and shorter products.
整體而言，本發明的萬用轉接電路層能大幅減少開發轉接板的設計成本，尤其是萬用轉接電路層的設計靈活性較高，並不局限於特定的晶片設計，所以本發明可運用在各種晶片上或與其搭配，因而提升應用彈性，擴大應用領域。On the whole, the universal switching circuit layer of the present invention can greatly reduce the design cost of developing the switching board, especially the design flexibility of the universal switching circuit layer is high, and it is not limited to a specific chip design. The invention can be applied to or matched with various chips, thereby improving application flexibility and expanding application fields.
應當理解，以上較佳實施例僅用於說明本發明的內容，除此之外，本發明還有其他實施方式，但凡本領域技術人員因本發明所涉及之技術啟示，而採用等同替換或等效變形方式形成的技術方案均落在本發明的保護範圍內。It should be understood that the above preferred embodiments are only used to illustrate the content of the present invention. In addition, there are other implementations of the present invention. Those skilled in the art use equivalent replacements or the like due to the technical inspiration of the present invention. The technical solutions formed by the effective deformation method all fall within the protection scope of the present invention.
10 萬用轉接電路層 11 延伸訊號區 11A 訊號線 11B 接墊 12 中繼接點區 12A 中繼接點 13 接地區 14 電源區 15 電氣絕緣層 20 第一晶片 21 第二晶片 30 基板 32 接腳 33 連接埠 34 導線架 35 承放座 36 引腳 40、41 引線 60 控制器 62 連接墊 70 快閃記憶體10 Universal switching circuit layer 11 Extended signal area 11A Signal line 11B pad 12 Relay contact area 12A Relay contact 13 Contact area 14 Power supply area 15 Electrical insulation layer 20 First chip 21 Second chip 30 Substrate 32 Pin 33 port 34 lead frame 35 receptacle 36 pin 40, 41 lead 60 controller 62 connection pad 70 flash memory
圖1是本發明一典型實施例中用於半導體封裝結構的萬用轉接電路層的示意圖； 圖2是本發明另一典型實施例中用於半導體封裝結構的萬用轉接電路層的示意圖； 圖3是利用本發明一典型實施例的萬用轉接電路層所完成的半導體封裝結構的上視圖； 圖4為圖3中半導體封裝結構的A-A方向剖視圖； 圖5是利用本發明一典型實施例的萬用轉接電路層所完成的另一半導體封裝結構的上視圖； 圖6為圖4中半導體封裝結構的剖視圖； 圖7是利用本發明一典型實施例的萬用轉接電路層所完成的又一半導體封裝結構的上視圖； 圖8為圖7中半導體封裝結構的剖視圖；以及 圖9是利用本發明一典型實施例的萬用轉接電路層所完成的又一半導體封裝結構的剖視圖。FIG. 1 is a schematic diagram of a universal switching circuit layer for a semiconductor packaging structure in a typical embodiment of the present invention; FIG. 2 is a schematic diagram of a universal switching circuit layer for a semiconductor packaging structure in another exemplary embodiment of the present invention FIG. 3 is a top view of a semiconductor package structure completed using a universal transfer circuit layer of an exemplary embodiment of the present invention; FIG. 4 is a cross-sectional view of the semiconductor package structure in FIG. Top view of another semiconductor package structure completed by the universal switch circuit layer of the embodiment; FIG. 6 is a cross-sectional view of the semiconductor package structure in FIG. 4; Top view of another completed semiconductor package structure; ； FIG. 8 is a cross-sectional view of the semiconductor package structure in FIG. 7; and FIG. 9 is another semiconductor package structure completed using a universal transfer circuit layer of a typical embodiment of the present invention Cutaway view.
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| CN201810326389.7A CN108336056B (en) | 2018-04-12 | 2018-04-12 | Universal switching circuit layer for semiconductor packaging structure |
| ??201810326389.7 | 2018-04-12 | ||
| CN201820517801.9U CN207966971U (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
| ??201820517801.9 | 2018-04-12 |
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|---|---|---|---|---|
| TW200705620A (en) * | 2005-07-20 | 2007-02-01 | Fujitsu Ltd | Relay board and semiconductor device having the relay board |
| TW201112364A (en) * | 2009-09-28 | 2011-04-01 | Powertech Technology Inc | Interposer connector for embedding in semiconductor packages |
| TW201635453A (en) * | 2014-12-24 | 2016-10-01 | Renesas Electronics Corp | Semiconductor device |
| TWM565880U (en) * | 2018-04-12 | 2018-08-21 | 大陸商蘇州震坤科技有限公司 | Universal adapting circuit layer for semiconductor package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200705620A (en) * | 2005-07-20 | 2007-02-01 | Fujitsu Ltd | Relay board and semiconductor device having the relay board |
| TW201112364A (en) * | 2009-09-28 | 2011-04-01 | Powertech Technology Inc | Interposer connector for embedding in semiconductor packages |
| TW201635453A (en) * | 2014-12-24 | 2016-10-01 | Renesas Electronics Corp | Semiconductor device |
| TWM565880U (en) * | 2018-04-12 | 2018-08-21 | 大陸商蘇州震坤科技有限公司 | Universal adapting circuit layer for semiconductor package structure |
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