TWI399839B - Interposer connector for embedding in semiconductor packages - Google Patents
Interposer connector for embedding in semiconductor packages Download PDFInfo
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- TWI399839B TWI399839B TW098132790A TW98132790A TWI399839B TW I399839 B TWI399839 B TW I399839B TW 098132790 A TW098132790 A TW 098132790A TW 98132790 A TW98132790 A TW 98132790A TW I399839 B TWI399839 B TW I399839B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
Description
本發明係有關於半導體裝置，特別係有關於一種內置於半導體封裝構造之中介連接器。The present invention relates to a semiconductor device, and more particularly to an interposer connector built into a semiconductor package structure.
隨著電子產業的蓬勃發展，電子產品通常需要小型、高效能、多功能、高速、大容量、低價格等特徵。因此發展了將半導體封裝構造以多晶片模組化(Multi Chip Module；MCM)的形式呈現，此種封裝構造可縮減整體封裝構造體積並提昇電性功能，遂而成為一種封裝的主流。其中堆疊式晶片之半導體封裝構造係在一如印刷電路板或之晶片承載體(chip carrier)上安裝至少兩半導體晶片，晶片的堆疊可為以垂直堆疊(stack)方式，此種堆疊式晶片之半導體封裝構造可見於美國專利第7,166,495號、第6,861,761號以及第6,621,155號等習知技術中。With the booming electronics industry, electronic products often require features such as small size, high efficiency, versatility, high speed, large capacity, and low price. Therefore, the development of the semiconductor package structure in the form of a multi-chip module (MCM) has been developed, which can reduce the overall package structure volume and enhance the electrical function, thereby becoming a mainstream of the package. The semiconductor package structure of the stacked wafers is mounted on at least two semiconductor wafers on a printed circuit board or a chip carrier. The stacking of the wafers may be in a vertical stacking manner. Semiconductor package constructions are found in the prior art, such as U.S. Patent Nos. 7,166,495, 6,861,761, and 6,621,155.
然而，由於晶片銲墊(chip pad)的間距較小且晶片種類有多樣性，在進行晶片的堆疊作業時，並無法使對應的晶片銲墊相互對齊與鄰靠，並且晶片承載體之接墊配置無法完全符合所有晶片的打線連接要求。因此，在晶片之間有必要設置一中介連接器(interposer)，作為堆疊晶片的晶片銲墊與晶片承載體之接墊之間的電性連接。However, due to the small pitch of the chip pads and the variety of wafer types, the wafer pads cannot be aligned and adjacent to each other during the stacking operation of the wafers, and the pads of the wafer carriers are supported. The configuration does not fully match the wire bonding requirements of all wafers. Therefore, it is necessary to provide an interposer between the wafers as an electrical connection between the wafer pads of the stacked wafers and the pads of the wafer carrier.
請參閱第1圖所示，為習知的一種堆疊式晶片之半導體封裝構造之截面示意圖。該堆疊式晶片之半導體封裝構造係包含一第一晶片10、一第二晶片20、一基板30以及一中介連接器100。該些晶片10、20包括各種晶片，例如記憶體晶片(memory chip)、非記憶體晶片(non-memory chip)、邏輯晶片(logic chip)以及類比晶片(analog chip)。該些晶片10、20之主動面朝上並垂直堆疊在該基板30上。該中介連接器100係設置於該第一晶片10與該第二晶片20之間。該中介連接器100的上表面係形成有一重配置線路結構120。該第一晶片10之複數個第一銲墊11係藉由複數個銲線41而連接至該重配置線路結構120，該第二晶片20之複數個第二銲墊21係藉由複數個銲線42而連接至該重配置線路結構120，再透過該重配置線路結構120與複數個銲線43電性連接至該基板30。該重配置線路結構120係做為該些晶片10、20將銲線41、42連接至該基板30之中繼配線。並藉由該中介連接器100而達成該些晶片10、20與該基板30之電性連接。然習知之中介連接器100為一具有預定厚度(大於150微米)之多層佈線板所構成，利用PWB(印刷電路板)製程的增層法(build-up)或疊層法來製造。習知中介連接器100不僅與該些晶片10、20有著熱膨脹係數之差異更有相當厚度足以在封裝構造中產生內應力，引發產品可靠度降低的問題。此外，該堆疊式晶片之半導體封裝構造的尺寸與厚度亦無法進一步縮小。Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional semiconductor package structure of a stacked wafer. The semiconductor package structure of the stacked wafer includes a first wafer 10, a second wafer 20, a substrate 30, and an intermediate connector 100. The wafers 10, 20 include various wafers such as a memory chip, a non-memory chip, a logic chip, and an analog chip. The active faces of the wafers 10, 20 face up and are vertically stacked on the substrate 30. The interposer 100 is disposed between the first wafer 10 and the second wafer 20. The upper surface of the interposer connector 100 is formed with a reconfiguration line structure 120. The plurality of first pads 11 of the first wafer 10 are connected to the relocation line structure 120 by a plurality of bonding wires 41. The plurality of second pads 21 of the second wafer 20 are processed by a plurality of soldering pads 21 The line 42 is connected to the reconfiguration line structure 120, and is electrically connected to the substrate 30 through the reconfiguration line structure 120 and a plurality of bonding wires 43. The reconfiguration line structure 120 is used as the relay wiring for connecting the bonding wires 41, 42 to the substrate 30 as the wafers 10, 20. The electrical connection between the wafers 10 and 20 and the substrate 30 is achieved by the interposer 100. However, the conventional interposer 100 is constructed of a multilayer wiring board having a predetermined thickness (greater than 150 μm) and is manufactured by a build-up or lamination method using a PWB (printed circuit board) process. The conventional interposer 100 not only has a difference in thermal expansion coefficient from the wafers 10, 20 but also has a considerable thickness sufficient to generate internal stress in the package structure, causing a problem of reduced product reliability. In addition, the size and thickness of the semiconductor package structure of the stacked wafer cannot be further reduced.
為了解決上述之問題，本發明之主要目的係在於提供一種內置於半導體封裝構造之中介連接器，具有薄化、供打線連接與消除封裝內應力的功效，能有效縮小半導體封裝構造之體積，並有效降低成本。In order to solve the above problems, the main object of the present invention is to provide an intermediate connector built in a semiconductor package structure, which has the advantages of thinning, wire bonding, and elimination of stress in the package, and can effectively reduce the size of the semiconductor package structure, and Effectively reduce costs.
本發明之次一目的係在於提供一種內置於半導體封裝構造之中介連接器，重配置線路結構可不位在習知承載板之表面，可避免因與晶片的熱膨脹係數不匹配導致脫層或翹曲之問題。A second object of the present invention is to provide an intermediate connector built in a semiconductor package structure, and the reconfiguration line structure can be omitted from the surface of a conventional carrier board to avoid delamination or warpage due to mismatch with the thermal expansion coefficient of the wafer. The problem.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種內置於半導體封裝構造之中介連接器，包含一底保護層、一重配置線路結構、一表面保護層以及複數個第一電鍍接指與第二電鍍接指。該底保護層係為整片狀並具有介於4至8微米之厚度。該重配置線路結構係設置於該底保護層上並具有至少一層厚度介於4至8微米之線路層。該表面保護層係覆蓋該重配置線路結構與該底保護層上，該表面保護層在該重配置線路結構上的厚度係介於5至6微米，並且該表面保護層係具有複數個開孔。該些第一電鍍接指與第二電鍍接指，係設置於該些開孔內而顯露在同一表面，並經由該重配置線路結構而使對應之第一電鍍接指與第二電鍍接指相互電性連接。其中，該底保護層、該重配置線路結構與該表面保護層的組合厚度係不大於50微米。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses an intermediate connector built in a semiconductor package structure, comprising a bottom protection layer, a reconfiguration line structure, a surface protection layer and a plurality of first plating fingers and second plating fingers. The bottom protective layer is monolithic and has a thickness of between 4 and 8 microns. The reconfigured wiring structure is disposed on the bottom protective layer and has at least one wiring layer having a thickness of 4 to 8 micrometers. The surface protective layer covers the reconfigured wiring structure and the bottom protective layer, the surface protective layer has a thickness of 5 to 6 micrometers on the reconfigured wiring structure, and the surface protective layer has a plurality of openings . The first plated fingers and the second plated fingers are disposed in the openings to be exposed on the same surface, and the corresponding first plated fingers and the second plated fingers are connected via the reconfigured line structure. Electrically connected to each other. Wherein, the bottom protective layer, the combined layout structure and the surface protective layer have a combined thickness of no more than 50 micrometers.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述的中介連接器中，該些第一電鍍接指與該些第二電鍍接指係可不突出於該表面保護層。In the foregoing interposer, the first plating fingers and the second plating fingers may not protrude from the surface protection layer.
在前述的中介連接器中，該些第一電鍍接指與該些第二電鍍接指係可為鎳金電鍍層。In the foregoing interposer, the first plating fingers and the second plating fingers may be nickel gold plating layers.
在前述的中介連接器中，可另包含一承載片，以供該底保護層之形成。In the foregoing interposer, a carrier sheet may be further included for the formation of the underlayer.
在前述的中介連接器中，該底保護層係可具有一平坦化的底面。In the aforementioned interposer, the bottom protective layer may have a flattened bottom surface.
在前述的中介連接器中，該重配置線路結構係可以該底保護層與該表面保護層完全密封。In the aforementioned interposer, the reconfiguration line structure can be completely sealed from the surface protection layer by the bottom protection layer.
在前述的中介連接器中，該重配置線路結構係可為單層結構，以使該底保護層、該重配置線路結構與該表面保護層的組合厚度係不大於30微米。In the foregoing interposer, the reconfiguration line structure may be a single layer structure such that the bottom protection layer, the reconfiguration line structure and the surface protection layer have a combined thickness of no more than 30 microns.
在前述的中介連接器中，該些第一電鍍接指與該些第二電鍍接指係可完全疊置於該重配置線路結構之上。In the aforementioned interposer, the first plated fingers and the second plated fingers may be completely superposed on the reconfigurable line structure.
本發明還揭示上述之中介連接器之製造方法，首先，提供一承載片。接著，形成一底保護層於該承載片上，該底保護層係為整片狀並具有介於4至8微米之厚度。之後，設置一重配置線路結構於該底保護層上，該重配置線路結構係具有至少一層厚度介於4至8微米之線路層。之後，形成一表面保護層，係覆蓋該重配置線路結構與該底保護層上，該表面保護層在該重配置線路結構上的厚度係介於5至6微米，並且該表面保護層係具有複數個開孔。最後，設置複數個第一電鍍接指與第二電鍍接指於該些開孔內而顯露在同一表面，並經由該重配置線路結構而使對應之第一電鍍接指與第二電鍍接指相互電性連接。其中，該底保護層的形成、該重配置線路結構的設置與該表面保護層的形成係為半導體製程，以使其組合厚度係不大於50微米。The present invention also discloses a method of manufacturing the above-described intermediate connector. First, a carrier sheet is provided. Next, a bottom protective layer is formed on the carrier sheet, the bottom protective layer being monolithic and having a thickness of between 4 and 8 microns. Thereafter, a reconfiguration line structure is disposed on the bottom protection layer, the reconfiguration line structure having at least one layer of circuitry having a thickness between 4 and 8 microns. Thereafter, a surface protective layer is formed covering the reconfigured wiring structure and the bottom protective layer, the surface protective layer has a thickness of 5 to 6 micrometers on the reconfigured wiring structure, and the surface protective layer has Multiple openings. Finally, a plurality of first plating fingers and a second plating plate are disposed in the openings to be exposed on the same surface, and the corresponding first plating fingers and the second plating fingers are connected via the reconfiguring circuit structure. Electrically connected to each other. Wherein, the formation of the bottom protective layer, the arrangement of the rearrangement line structure and the formation of the surface protective layer are in a semiconductor process such that the combined thickness is no more than 50 micrometers.
由以上技術方案可以看出，本發明之內置於半導體封裝構造之中介連接器以及其製造方法，具有以下優點與功效：It can be seen from the above technical solutions that the intermediate connector of the present invention embedded in the semiconductor package structure and the manufacturing method thereof have the following advantages and effects:
一、可藉由中介連接器內各元件的組合關係作為其中一技術手段，具有薄化、供打線連接與消除封裝內應力的功效，故能使中介連接器之厚度相當薄化，不會增加封裝構造之晶片堆疊高度且可縮短銲線長度及線弧高度，而能有效縮小半導體封裝構造之體積，並有效降低成本。1. The combination relationship of the components in the interposer can be used as one of the technical means, which has the functions of thinning, wire bonding and eliminating the stress in the package, so that the thickness of the interposer is relatively thin and does not increase. The wafer stack height of the package structure can shorten the wire length and the wire arc height, and can effectively reduce the volume of the semiconductor package structure and effectively reduce the cost.
二、可藉由中介連接器內各元件的作為其中一技術手段，重配置線路結構可不位在習知承載板之表面，可避免因與晶片的熱膨脹係數不匹配導致脫層或翹曲之問題。2. By using the components in the interposer as one of the technical means, the reconfiguration circuit structure may not be located on the surface of the conventional carrier board, and the problem of delamination or warpage due to mismatch with the thermal expansion coefficient of the wafer may be avoided. .
三、可藉由底保護層、重配置線路結構、表面保護層以及複數個第一電鍍接指與第二電鍍接指之特定組合關係作為其中一技術手段，使中介連接器相當薄化，並可提供跳線功能而不需使用長銲墊設計的堆疊式晶片之半導體封裝構造。Third, the bottom protection layer, the reconfiguration line structure, the surface protection layer, and the specific combination relationship of the plurality of first plating fingers and the second plating finger are used as one of the technical means to make the intermediate connector relatively thin, and A semiconductor package construction that provides a jumper function without the use of a long pad design.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例，一種內置於半導體封裝構造之中介連接器舉例說明於第2至4圖，其中第2圖為其截面示意圖，第3圖為使用該中介連接器之堆疊式晶片之半導體封裝構造之截面示意圖、第4A至4H圖為在製程中之元件截面示意圖。該中介連接器200主要包含一底保護層210、一重配置線路結構220、一表面保護層230以及複數個第一電鍍接指241與第二電鍍接指242。其中，該底保護層210、該重配置線路結構220與該表面保護層230的組合厚度係不大於50微米，同時具有薄化、供打線連接與消除封裝內應力的功效，故該中介連接器200為相當薄化，不會增加封裝構造高度且可縮短銲線長度及線弧高度，而能有效縮小半導體封裝構造之體積，並有效降低成本。而該中介連接器200能達成組合厚度不大於50微米的內部結構詳述如下。According to a first embodiment of the present invention, an intermediate connector built into a semiconductor package structure is illustrated in FIGS. 2 to 4, wherein FIG. 2 is a schematic cross-sectional view thereof, and FIG. 3 is a stacked type using the interposer. A schematic cross-sectional view of a semiconductor package structure of a wafer, and FIGS. 4A to 4H are schematic cross-sectional views of elements in a process. The interposer 200 includes a bottom protection layer 210, a reconfiguration line structure 220, a surface protection layer 230, and a plurality of first plating fingers 241 and second plating fingers 242. Wherein, the bottom protective layer 210, the reconfigured line structure 220 and the surface protective layer 230 have a combined thickness of not more than 50 micrometers, and have the functions of thinning, wire bonding and eliminating internal stress of the package, so the intermediate connector The 200 is relatively thin, does not increase the height of the package structure, and can shorten the length of the bonding wire and the height of the wire arc, thereby effectively reducing the volume of the semiconductor package structure and effectively reducing the cost. The interposer 200 can achieve an internal structure having a combined thickness of no more than 50 microns as detailed below.
請參閱第2圖所示，該底保護層210係為整片狀並具有介於4至8微米之厚度。該底保護層210係可具有一平坦化的底面211，可供將該中介連接器200設置在其他載體上。該底保護層210係為一介電層，其材質係可選自聚亞醯胺(Polyimide,PI)、聯二苯環丁二烯(benzocylobutene,BCB)、ABF(Ajinomoto Build-up Film)、雙順丁醯二酸醯亞按/三氮阱(BT,Bismaleimide triazine)、聯二苯環丁二烯(benzocylobutene,BCB)、液晶聚合物(Liquid Crystal Polymer)、聚乙烯醚(Poly(phenylene ether))、聚四氟乙烯(Poly(tetra-fluoroethylene))、芳香尼龍(Aramide)、環氧樹脂、以及玻璃纖維所組成之群組之其中之一。較佳係為可為PI、BCB等絕緣性材料，具有耐熱、耐燃、強度好、厚度薄、電氣絕緣性佳之特性。由於該底保護層210之厚度僅有4至8微米，利用半導體製程之沉積或蒸鍍等塗佈技術所製造，不相同於習知軟性電路板之可撓曲載膜(厚度約12.5微米)。Referring to Figure 2, the bottom protective layer 210 is monolithic and has a thickness of between 4 and 8 microns. The bottom protective layer 210 can have a planarized bottom surface 211 for the interposer 200 to be disposed on other carriers. The bottom protective layer 210 is a dielectric layer, and the material thereof may be selected from the group consisting of polyimide (PI), benzocylobutene (BCB), ABF (Ajinomoto Build-up Film), Bis-butyl bismuth bismuth suboxide/Bismaleimide triazine, benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal Polymer), polyvinyl ether (Poly (phenylene ether) )), one of a group consisting of poly(tetra-fluoroethylene), aromatic polyamide (Aramide), epoxy resin, and glass fiber. Preferably, it is an insulating material such as PI or BCB, and has characteristics of heat resistance, flame resistance, good strength, thin thickness, and good electrical insulation. Since the thickness of the bottom protective layer 210 is only 4 to 8 micrometers, it is manufactured by a coating technique such as deposition or evaporation of a semiconductor process, and is different from a flexible carrier film of a conventional flexible circuit board (thickness of about 12.5 micrometers). .
該重配置線路結構220係設置於該底保護層210上並具有至少一層厚度介於4至8微米之線路層221。該線路層221可為任何能將電路導通之金屬，較佳為銅、錫、鎳、鉻、鈦、銅-鉻合金以及錫-鉛合金中所組成之群組之一者，更佳則為銅。較佳地，該重配置線路結構220係能以該底保護層210與該表面保護層230完全密封，以避免水氣或外來物污染。該重配置線路結構220係可為單層結構，以使該底保護層210、該重配置線路結構220與該表面保護層230的組合厚度係不大於30微米，而具有更薄之厚度。The reconfiguration line structure 220 is disposed on the bottom protection layer 210 and has at least one circuit layer 221 having a thickness of 4 to 8 microns. The circuit layer 221 can be any metal that can conduct the circuit, preferably one of a group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy, and more preferably copper. . Preferably, the reconfiguration line structure 220 can be completely sealed with the surface protection layer 230 by the bottom protection layer 210 to avoid moisture or foreign matter contamination. The reconfiguration line structure 220 can be a single layer structure such that the bottom protection layer 210, the reconfiguration line structure 220, and the surface protection layer 230 have a combined thickness of no more than 30 microns and a thinner thickness.
該表面保護層230係覆蓋該重配置線路結構220與該底保護層210上，該表面保護層230在該重配置線路結構220上的厚度係介於5至6微米，該表面保護層230之材質係可相同於該底保護層210。具體而言，該表面保護層230係具有複數個開孔231。該些第一電鍍接指241與第二電鍍接指242係設置於該些開孔231內而顯露在同一表面，並經由該重配置線路結構220而使對應之第一電鍍接指241與第二電鍍接指242相互電性連接。詳細而言，該些第一電鍍接指241與該些第二電鍍接242指係可不突出於該表面保護層230，而使該些第一電鍍接指241、該些第二電鍍接242與該表面保護層230在同一平面，以利取放疊置，並在該表面保護層230之上方可供設置晶片或其他元件。更細部而言，該些第一電鍍接指241與該些第二電鍍接指242係可為鎳金電鍍層。每一第一電鍍接指241係包含一層鎳層241A與一層金層241B，該第二電鍍接指242亦包含鎳金兩層結構。其中鎳層241A為下層，厚度可為3微米；金層241B為上層，厚度可為0.3微米，組合後厚度未超過該表面保護層230。並且，該些第一電鍍接指241與該些第二電鍍接指242係可完全疊置於該重配置線路結構220上，即接指之邊緣不超過該重配置線路結構220之外(如第2圖所示)，故能承受打線強度。The surface protection layer 230 covers the reconfiguration line structure 220 and the bottom protection layer 210. The surface protection layer 230 has a thickness of 5 to 6 micrometers on the reconfiguration line structure 220. The surface protection layer 230 The material can be the same as the bottom protective layer 210. Specifically, the surface protection layer 230 has a plurality of openings 231. The first plating fingers 241 and the second plating fingers 242 are disposed in the openings 231 to be exposed on the same surface, and the corresponding first plating fingers 241 and the second through the reconfiguration line structure 220 The two plating fingers 242 are electrically connected to each other. In detail, the first plated fingers 241 and the second plated contacts 242 may not protrude from the surface protection layer 230, and the first plated fingers 241 and the second plated contacts 242 are The surface protection layer 230 is on the same plane to facilitate stacking, and a wafer or other component can be disposed above the surface protection layer 230. In more detail, the first plating fingers 241 and the second plating fingers 242 may be nickel gold plating layers. Each of the first plating fingers 241 includes a nickel layer 241A and a gold layer 241B. The second plating fingers 242 also comprise a nickel-gold two-layer structure. The nickel layer 241A is a lower layer and has a thickness of 3 micrometers; the gold layer 241B is an upper layer and has a thickness of 0.3 micrometers, and the combined thickness does not exceed the surface protective layer 230. Moreover, the first plated fingers 241 and the second plated fingers 242 can be completely stacked on the reconfiguration line structure 220, that is, the edge of the finger does not exceed the reconfiguration line structure 220 (eg, Figure 2), so it can withstand the strength of the wire.
如第3圖所示，將該中介連接器200運用在一堆疊式晶片之半導體封裝構造時，該半導體封裝構造的基本架構與元件可與習知之第1圖結構相同，故相類似元件以相同圖號標示。該中介連接器200係設置於該第一晶片10與該第二晶片20之間。該中介連接器200之該重配置線路結構220係做為該些晶片10、20將銲線41、42連接至該基板30之中繼配線。並藉由該中介連接器200而達成該些晶片10、20與該基板30之電性連接。該中介連接器200係可提供封裝內線路傳導功能並且不需使用長銲線設計的堆疊式晶片。並且由於該中介連接器200不具有承載板，故厚度相當薄化，不會增加封裝構造高度且可縮短該些銲線41、42與43長度及線弧高度，而能有效縮小半導體封裝構造之體積，並有效降低成本。並可避免習知之中介連接器因熱膨脹係數不匹配導致脫層或翹曲之問題。As shown in FIG. 3, when the interposer connector 200 is applied to a semiconductor package structure of a stacked wafer, the basic structure and components of the semiconductor package structure can be the same as those of the conventional FIG. 1, so that similar components are identical. The figure number is indicated. The interposer connector 200 is disposed between the first wafer 10 and the second wafer 20. The reconfigurable line structure 220 of the interposer 200 is used as the relay wiring for connecting the bonding wires 41, 42 to the substrate 30. The electrical connection between the wafers 10 and 20 and the substrate 30 is achieved by the interposer connector 200. The interposer connector 200 is a stacked wafer that provides in-package line conduction functionality and does not require long wire bond design. Moreover, since the interposer 200 does not have a carrier board, the thickness is relatively thin, the package structure height is not increased, and the lengths of the bonding wires 41, 42 and 43 and the line arc height can be shortened, and the semiconductor package structure can be effectively reduced. Volume and effective cost reduction. It can also avoid the problem that the conventional intermediate connector causes delamination or warpage due to mismatch of thermal expansion coefficients.
本發明之該中介連接器200除了可適用於第3圖之晶片堆疊之中介物外，還可適用不同的晶片堆疊型態，例如晶片主動面上該中介連接器200與小晶片的並排方式(Side by Side)。The interposer connector 200 of the present invention can be applied to different wafer stacking types in addition to the interposer applicable to the wafer stack of FIG. 3, such as the side-by-side arrangement of the interposer connector 200 and the small wafer on the active side of the wafer ( Side by Side).
本發明進一步揭示一種前述中介連接器之製造方法，舉例說明於第4A至4I圖之製程中元件截面示意圖。The present invention further discloses a method of fabricating the aforementioned interposer, and exemplifies a cross-sectional view of the components in the process of FIGS. 4A to 4I.
首先，請參閱第4A圖所示，提供一承載片250。該承載片250係可選自玻璃、矽晶片或合金之其中之一，厚度約為50微米。該承載片250係可為大尺寸，如晶圓尺寸，並具有複數個呈十字交錯之切割道201，用以定義出該中介連接器200之形成位置。First, as shown in FIG. 4A, a carrier sheet 250 is provided. The carrier sheet 250 can be selected from one of glass, tantalum wafers or alloys having a thickness of about 50 microns. The carrier sheet 250 can be of a large size, such as a wafer size, and has a plurality of cross-staggered dicing streets 201 for defining the location of the interposer connector 200.
接著，再請參閱第4A圖所示，形成上述之底保護層210於該承載片250上，可利用一半導體製程之沉積或蒸鍍等塗佈技術而形成。Next, referring to FIG. 4A, the bottom protective layer 210 is formed on the carrier sheet 250 by a coating technique such as deposition or vapor deposition of a semiconductor process.
之後，請參閱第4B圖所示，形成一種子層260(seed layer)於該底保護層210上，可利用濺鍍(sputtering)方式沉積而成。該種子層260係提供後續進行電鍍製程所需之電流傳導路徑，以電鍍形成該重配置線路結構220。該種子層260可為一薄金層，並全面覆蓋該底保護層210。Thereafter, referring to FIG. 4B, a seed layer 260 is formed on the bottom protective layer 210, and can be deposited by sputtering. The seed layer 260 provides a current conducting path required for subsequent electroplating processes to form the reconfigured wiring structure 220 by electroplating. The seed layer 260 can be a thin gold layer and completely cover the bottom protective layer 210.
之後，請參閱第4C圖所示，於該種子層260上以曝光(exposing)、顯影(developing)方式形成一具有複數個開口51之光阻層50，且該些開口51係為該重配置線路結構220的預定形成區域。該光阻層50可藉由微影製程圖案化而形成一光阻圖案。Then, as shown in FIG. 4C, a photoresist layer 50 having a plurality of openings 51 is formed on the seed layer 260 by exposing and developing, and the openings 51 are the reconfigurations. A predetermined formation area of the line structure 220. The photoresist layer 50 can be patterned by a lithography process to form a photoresist pattern.
之後，請參閱第4D圖所示，於該些開口51上以電鍍方式設置上述之重配置線路結構220於該底保護層210上。之後，請參閱第4E圖所示，以去光阻(photoresist stripping)方式移除該光阻層50。再以蝕刻(etching)方式移除該種子層260未被該重配置線路結構220覆蓋之外露部份。Thereafter, as shown in FIG. 4D, the above-described reconfiguration wiring structure 220 is disposed on the bottom protection layer 210 by electroplating on the openings 51. Thereafter, as shown in FIG. 4E, the photoresist layer 50 is removed by photoresist stripping. The seed layer 260 is removed by etching to cover the exposed portion of the reconfigured line structure 220.
之後，請參閱第4F圖所示，形成上述之表面保護層230於該重配置線路結構220與該底保護層210上，再以曝光、顯影方式形成上述之開孔231。該些開孔231局部顯露該重配置線路結構220，其係為第一電鍍接指241與第二電鍍接指242的預定形成區域。Then, as shown in FIG. 4F, the surface protection layer 230 is formed on the rearrangement line structure 220 and the bottom protection layer 210, and the opening 231 is formed by exposure and development. The openings 231 partially expose the reconfiguration line structure 220 as a predetermined formation area of the first plating fingers 241 and the second plating fingers 242.
之後，請參閱第4G圖所示，利用電鍍方式設置上述之第一電鍍接指241與第二電鍍接指242於該些開孔231內而顯露在同一表面，並經由該重配置線路結構220而使對應之第一電鍍接指241與第二電鍍接指242相互電性連接。該些第一電鍍接指241與該些第二電鍍接指242係可為鎳金電鍍層，可分兩次電鍍形成。該些第一電鍍接指241與該些第二電鍍接242的位置可依需要調整。After that, as shown in FIG. 4G, the first plated fingers 241 and the second plated fingers 242 are disposed on the same surface by electroplating, and the reconfigured line structure 220 is disposed through the reconfigured line structure 220. The corresponding first plating fingers 241 and the second plating fingers 242 are electrically connected to each other. The first plating fingers 241 and the second plating fingers 242 may be nickel gold plating layers, which may be formed by two electroplating. The positions of the first plated fingers 241 and the second plated joints 242 can be adjusted as needed.
之後，請參閱第4H圖所示，在該表面保護層230之上方貼附一研磨膠帶60，並以一磨具70進行研磨以移除該承載片250，並使該底保護層210係具有該平坦化的底面211。研磨完成之後，該承載片250即不存在或僅殘留極少部分。Thereafter, as shown in FIG. 4H, a polishing tape 60 is attached over the surface protection layer 230, and is ground by a grinding tool 70 to remove the carrier sheet 250, and the bottom protection layer 210 is provided. The flattened bottom surface 211. After the grinding is completed, the carrier sheet 250 does not exist or only a few portions remain.
最後，請參閱第4I圖所示，可利用一切割刀具80沿著該些切割道201切割而分離成單體的中介連接器200。在不同實施例中，切割之方法係可採用雷射光。完成切割之後，可撕除該切割膠帶60，使該些第一電鍍接指241與該些第二電鍍接指242顯露出，並得到如第2圖所示超薄型態(不大於50微米)且平坦之中介連接器200。Finally, as shown in FIG. 4I, a cutting tool 80 can be cut along the cutting lanes 201 to separate into a single interposer 200. In various embodiments, the method of cutting may employ laser light. After the cutting is completed, the cutting tape 60 can be peeled off, and the first plating fingers 241 and the second plating fingers 242 are exposed, and the ultra-thin type (not more than 50 micrometers) as shown in FIG. 2 is obtained. And a flat interposer 200.
在上述之製造方法中，該底保護層210的形成、該重配置線路結構220的設置與該表面保護層230的形成係為半導體製程，以使其組合厚度係不大於50微米，故能使該中介連接器200之厚度相當薄化。In the above manufacturing method, the formation of the bottom protective layer 210, the arrangement of the rearrangement line structure 220, and the formation of the surface protective layer 230 are performed in a semiconductor process so that the combined thickness is not more than 50 micrometers, so that The thickness of the interposer connector 200 is quite thin.
在本發明之第二具體實施例中，如第5圖所示，揭示另一種內置於半導體封裝構造之中介連接器。在該實施例中，該中介連接器300係保留原本在第一實施例之第4H圖中移除之承載片250，即不實施研磨承載片250之步驟，而保留該承載片250，以使其做為該底保護層210之支撐，並可增加整體之硬度。然該承載片250之熱膨脹係數相同於晶片之熱膨脹係數，以消除封裝內應力。In a second embodiment of the present invention, as shown in FIG. 5, another intermediate connector built into a semiconductor package structure is disclosed. In this embodiment, the interposer 300 retains the carrier sheet 250 that was originally removed in the fourth embodiment of the first embodiment, that is, the step of not performing the grinding of the carrier sheet 250, while retaining the carrier sheet 250, so that It serves as a support for the bottom protective layer 210 and can increase the overall hardness. However, the carrier sheet 250 has a thermal expansion coefficient equal to that of the wafer to eliminate stress in the package.
在本發明之第三具體實施例中，揭示另一種內置於半導體封裝構造之中介連接器，說明於第6圖之截面示意圖，其中與第一實施例相同的主要元件將以相同符號標示之。特別的是，該重配置線路結構220係具有雙層線路，另包含不在同一水平面之線路層221與422，該些線路層221與422係以該底保護層210與該表面保護層230完全密封，可不受外界水氣或外來物污染。並且該些線路層221與422可視需要而彈性配置。In the third embodiment of the present invention, another intermediate connector built into the semiconductor package structure is disclosed. The cross-sectional view of FIG. 6 is illustrated in the same manner as the first embodiment, and the same components as those in the first embodiment will be denoted by the same reference numerals. In particular, the reconfiguration line structure 220 has a double layer circuit, and further includes circuit layers 221 and 422 that are not in the same horizontal plane. The circuit layers 221 and 422 are completely sealed by the bottom protection layer 210 and the surface protection layer 230. It can be free from external moisture or foreign matter. And the circuit layers 221 and 422 can be flexibly configured as needed.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
10．．．第一晶片10. . . First wafer
11．．．第一銲墊11. . . First pad
20．．．第二晶片20. . . Second chip
21．．．第二銲墊twenty one. . . Second pad
30．．．基板30. . . Substrate
41．．．銲線41. . . Welding wire
42．．．銲線42. . . Welding wire
43．．．銲線43. . . Welding wire
50．．．光阻層50. . . Photoresist layer
51．．．開口51. . . Opening
60．．．研磨膠帶60. . . Grinding tape
70．．．磨具70. . . Abrasives
80．．．切割刀具80. . . Cutting tool
100．．．中介連接器100. . . Mediation connector
120．．．重配置線路結構120. . . Reconfiguration line structure
200．．．中介連接器200. . . Mediation connector
201．．．切割道201. . . cutting line
210．．．底保護層210. . . Bottom protection layer
211．．．底面211. . . Bottom
220．．．重配置線路結構220. . . Reconfiguration line structure
221．．．線路層221. . . Circuit layer
230．．．表面保護層230. . . Surface protection layer
231．．．開孔231. . . Opening
241．．．第一電鍍接指241. . . First plating finger
241A．．．鎳層241A. . . Nickel layer
241B．．．金層241B. . . Gold layer
242．．．第二電鍍接指242. . . Second plating joint
250．．．承載片250. . . Carrier sheet
260．．．種子層260. . . Seed layer
300．．．中介連接器300. . . Mediation connector
400．．．中介連接器400. . . Mediation connector
422．．．線路層422. . . Circuit layer
第1圖：為習知的一種堆疊式晶片之半導體封裝構造之截面示意圖。Figure 1 is a cross-sectional view showing a conventional semiconductor package structure of a stacked wafer.
第2圖：依據本發明之第一具體實施例的一種內置於半導體封裝構造之中介連接器之截面示意圖。2 is a schematic cross-sectional view of an interposer mounted in a semiconductor package structure in accordance with a first embodiment of the present invention.
第3圖：依據本發明之第一具體實施例的使用該中介連接器之堆疊式晶片之半導體封裝構造之截面示意圖。Figure 3 is a cross-sectional view showing a semiconductor package structure of a stacked wafer using the interposer according to a first embodiment of the present invention.
第4A至4I圖：依據本發明之第一具體實施例的該中介連接器在製程中之元件截面示意圖。4A to 4I are cross-sectional views showing the components of the interposer in the process according to the first embodiment of the present invention.
第5圖：依據本發明之第二具體實施例的一種內置於半導體封裝構造之中介連接器之截面示意圖。Figure 5 is a cross-sectional view showing an intermediate connector built into a semiconductor package structure in accordance with a second embodiment of the present invention.
第6圖：依據本發明之第三具體實施例的一種內置於半導體封裝構造之中介連接器之截面示意圖。Figure 6 is a cross-sectional view showing an intermediate connector built into a semiconductor package structure in accordance with a third embodiment of the present invention.
200．．．中介連接器200. . . Mediation connector
210．．．底保護層210. . . Bottom protection layer
220．．．重配置線路結構220. . . Reconfiguration line structure
221．．．線路層221. . . Circuit layer
230．．．表面保護層230. . . Surface protection layer
231．．．開孔231. . . Opening
241．．．第一電鍍接指241. . . First plating finger
241A．．．鎳層241A. . . Nickel layer
241B．．．金層241B. . . Gold layer
242．．．第二電鍍接指242. . . Second plating joint
260．．．種子層260. . . Seed layer
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW098132790A TWI399839B (en) | 2009-09-28 | 2009-09-28 | Interposer connector for embedding in semiconductor packages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW098132790A TWI399839B (en) | 2009-09-28 | 2009-09-28 | Interposer connector for embedding in semiconductor packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201112364A TW201112364A (en) | 2011-04-01 |
| TWI399839B true TWI399839B (en) | 2013-06-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW098132790A TWI399839B (en) | 2009-09-28 | 2009-09-28 | Interposer connector for embedding in semiconductor packages |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWM565880U (en) * | 2018-04-12 | 2018-08-21 | 大陸商蘇州震坤科技有限公司 | Universal adapting circuit layer for semiconductor package structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308252A (en) * | 1992-12-24 | 1994-05-03 | The Whitaker Corporation | Interposer connector and contact element therefore |
| TW366608B (en) * | 1995-06-07 | 1999-08-11 | Cooper Ind Inc | Loadbreak separable connector |
| JP2002170820A (en) * | 2000-11-30 | 2002-06-14 | Sharp Corp | Method for manufacturing thin-film transistor and plasma-processing apparatus used for it |
| JP2003347475A (en) * | 2003-05-12 | 2003-12-05 | Oki Electric Ind Co Ltd | Semiconductor |
| TW200410362A (en) * | 2002-12-12 | 2004-06-16 | Solidlite Corp | Method and device for micro-connecter |
| TWI220460B (en) * | 2002-08-06 | 2004-08-21 | Advanced Semiconductor Eng | Connector for testing semiconductor device |
| US7241680B2 (en) * | 2004-04-30 | 2007-07-10 | Intel Corporation | Electronic packaging using conductive interposer connector |
| JP2008227241A (en) * | 2007-03-14 | 2008-09-25 | Seiko Epson Corp | Electronic device and its manufacturing method |
| JP2009164607A (en) * | 2008-01-04 | 2009-07-23 | Samsung Electronics Co Ltd | Bonding pad structure, manufacturing method thereof, and semiconductor package including bonding pad structure |
-
2009
- 2009-09-28 TW TW098132790A patent/TWI399839B/en active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308252A (en) * | 1992-12-24 | 1994-05-03 | The Whitaker Corporation | Interposer connector and contact element therefore |
| TW366608B (en) * | 1995-06-07 | 1999-08-11 | Cooper Ind Inc | Loadbreak separable connector |
| JP2002170820A (en) * | 2000-11-30 | 2002-06-14 | Sharp Corp | Method for manufacturing thin-film transistor and plasma-processing apparatus used for it |
| TWI220460B (en) * | 2002-08-06 | 2004-08-21 | Advanced Semiconductor Eng | Connector for testing semiconductor device |
| TW200410362A (en) * | 2002-12-12 | 2004-06-16 | Solidlite Corp | Method and device for micro-connecter |
| JP2003347475A (en) * | 2003-05-12 | 2003-12-05 | Oki Electric Ind Co Ltd | Semiconductor |
| US7241680B2 (en) * | 2004-04-30 | 2007-07-10 | Intel Corporation | Electronic packaging using conductive interposer connector |
| JP2008227241A (en) * | 2007-03-14 | 2008-09-25 | Seiko Epson Corp | Electronic device and its manufacturing method |
| JP2009164607A (en) * | 2008-01-04 | 2009-07-23 | Samsung Electronics Co Ltd | Bonding pad structure, manufacturing method thereof, and semiconductor package including bonding pad structure |
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| TW201112364A (en) | 2011-04-01 |
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