200937609 九、發明說明： 【發明所屬之技術領域】 本發明係有關於—種半導艘裝置，特別係 種片在基板之間（Chip 稱CBS)的半導體封裝構造及其製造方法。 【先前技術】 隨著微小化以及高運作速度需求的增加， 會整合在一封裝構造内，以達到兩倍以上之容 功能之需求’例如在以往的多晶片堆疊構造中 多個晶片堆疊並電性連接至一基板，再封膠在 料内。在每一個晶片設置之後都須經過一道的 以形成銲線，以使晶片電性連接至基板，故習 堆疊封裝之電性連接的製程週期時間會隨著 之數量增加而拉長jt且，銲線會隨著堆疊的 加打線長度，故容易產生沖線而電性短路。此 晶片數量的增加，導致半導體封裝構造容易產 問題。 s青參閱第1圖所开，一種半導體封裝構造 一基板110、一第〆晶片12〇、複數個第二晶 一封膠體150、複數個外接元件160、複數個 181以及複數個第二銲線182。該基板110之 1Π係提供該第一晶片120之設置’而該些第二 係堆疊在該第一晶片120上。該基板110之 112係供植接該些外接元件160。該第一晶片 有關於一 ，以下簡 多個晶片 量或更多 ’其係將 一封裝材 打線步驟 知多晶片 堆疊晶片 局度而增 外，堆疊 生翹曲的 100包含 片 130、 第一銲線 —内表面 -晶片1 3 〇 一外表面 uo係具BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure, and particularly to a semiconductor package structure between a substrate (Chip called CBS) and a method of fabricating the same. [Prior Art] With the increase in miniaturization and high operational speed requirements, it will be integrated into a package structure to achieve more than twice the capacity of the function. For example, in the conventional multi-wafer stack configuration, multiple wafers are stacked and charged. It is connected to a substrate and then sealed in the material. After each wafer is disposed, it must pass through one to form a bonding wire to electrically connect the wafer to the substrate. Therefore, the process cycle time of the electrical connection of the stacked package may be extended by the amount and the soldering is extended. The line will be easily twisted and electrically shorted with the length of the stacked wire. This increase in the number of wafers has led to problems in semiconductor package construction. Referring to FIG. 1 , a semiconductor package structure includes a substrate 110 , a second wafer 12 , a plurality of second crystals 150 , a plurality of external components 160 , a plurality of 181 , and a plurality of second bonding wires . 182. The substrate 110 is provided with the arrangement of the first wafer 120 and the second structures are stacked on the first wafer 120. 112 of the substrate 110 is for implanting the external components 160. The first wafer has a plurality of wafers or more, which is increased by a plurality of wafers, and the stacking warp 100 includes a sheet 130 and a first bonding wire. - inner surface - wafer 1 3 〇 an outer surface uo tie
200937609 有複數個篦_ # 第 電極121。在第一黏晶過程 一 輝 181電性連接該些第一電極 110。再琢_ , —地該些第二晶片130係疊設 120上’每_笛一 $ —晶片130係具有複數個； —日 一曰曰片Uo堆疊之後，方可藉由 1 8 2分別電性 連接該些第二電極131至該 封膠體150係來由从 &成於該基板110之該内表 封該第一晶Η Ί 1 片120、該些第二晶片130、 181與該也第-經 —乐一銲線182。因此，習知半 1 0 0的電性遠垃 $接之製程週期時間無法有效 此外’在該些晶片1 2 0與1 3 0之間係 190以避免上方晶片觸壓下方銲線，會 之增加，使得封裝翹曲問題更嚴重。請再 不，該些第二銲線182會隨著該些第二晶 间度增加而拉長，除了會有訊號延遲的探 封膠體1 5 0時容易產生沖線之問題。 【發明内容】 本發明之主要目的係在於提供一種晶 的半導體封裝構造及其製造方法，經由第 能使第一晶片與第二晶片電性連接至具 一基板，相對於習知打線連接的逐條形成 合每一晶片需一农覆晶接合操作方式，更 叠ΒΒ片至基板的電性連接的製程週期時f 具備有降低多晶片封裝構造的翹曲度與 之後，藉由該 1 2 1至該基板 於該第一晶片 客二電極131。 該些第二銲線 基板1 1 0。該 面111上並密 該些第一銲線 導體封裝構造 縮短。 設有一間隔片 造成封裝厚度 參閱第1圖所 片1 3 0之堆養 題，在形成該 片在基板之間 -一基板的設置 有外接端之第 與習知覆晶接 能縮短多個堆 3。此外，同時 縮小封裝尺寸 7 200937609 之功效。 本發明之次一目的係在於提供一種晶片在基板之間 的半導體封裝構造及其製造方法，可以解決習知多晶片 堆疊中連接越上層堆疊晶片的打線銲線越長導致的訊 號延遲與電性短路之問題。 本發明之另一目的係在於提供一種晶片在基板之間 的半導體封裝構造及其製造方法，第二基板壓合在第一 基板上的方式可沿用習知的覆晶接合設備，以降低設備 ® 成本。 本發明之另一目的係在於提供一種晶片在基板之間 的半導體封裝構造及其製造方法，能方便定位兩夾合晶 片之基板並確保基板與其間晶片之電性連接品質。 本發明之另一目的係在於提供一種晶片在基板之間 的半導體封裝構造及其製造方法，能穩固地電性導通該 第一基板與該第二基板，在封膠時不會斷裂。 A 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種晶片在基板之間 的半導體封裝構造，主要包含一第一基板、一第一晶 片、至少一第二晶片以及一第二基板。該第一基板係具 有一第一内表面與一外表面，該第一内表面係設有複數 個第一内接端，該外表面係設有複數個外接端。該第一 晶片係設於該第一基板之該第一内表面並具有複數個 第一電極。該第二晶片係設於該第一晶片上並具有複數 個第二電極。該第二基板係設於該第一基板上，以使該 8 200937609 第一晶片與該第二晶片被夾合在該第一基板與該第二 基板之間，該第二基板係具有一朝向該第一内表面之第 二内表面’該第二内表面係設有複數個第二内接端、複 數個第一電極接點以及複數個第二電極接點，其中該些 第二内接端係接合至該些第一内接端，該些第一電極接 點係接合至第一電極，該些第二電極接點係接合至第二 電極°此外，另揭示前述晶片在基板之間的半導體封裝 構造之製造方法。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之半導體封裝構造中，該些第一電極接點與該 些第二電極接點係可包含有複數個導通柱。 在前述之半導體封裝構造中，該些第一電極與該些第 二電極係可具有複數個定位孔，該些導通柱係插接至該 些定位孔。 在則述之半導體封裝構造中，該些定位孔内係可形成 有導電材料。 在前述之半導體封裝構造中，該些第一内接端係可包 含複數個插座，該些第二内接端係包含複數個插柱，以 使該些第一内接端與該些第二内接端相互鑲嵌。 在前述之半導體封裝構造中’該些插座内係可形成有 導電材料。 在剛述之半導體封裝構造中’該些第一内接端與該些 第二内接端之鑲嵌高度係町概約相同於該第一晶片與 9 200937609 §玄第一晶片之堆疊高度。 在刖述之半導體封裝構造中’可另包含有一封膠體， 係形成在該第一基板與該第二基板之間並密封該第一 晶片與該第二晶片。 在前述之半導體封裝構造中，該封膠體係可更密封該 第二基板之一外表面。 在前述之半導體封裝構造中，可另包含有複數個外接 元件，係設置於該些外接端。 β 在前述之半導體封裝構造中，該第一基板與該第二基 板係可具有相同厚度與相同熱膨脹係數。 【實施方式】 依據本發明之第一具體實施例，揭示一種晶片在基 板之間的半導體封裝構造。請參閱第2圖所示，一種晶 片在基板之間（CBS)的半導體封裝構造2〇〇主要包含一 第一基板210、一第一晶片220、至少一第二晶片230 φ 以及一第二基板240。該第一基板210係具有一第一内 表面211與一外表面212，該第一内表面211係設有複 數個第一内接端213，該外表面212係設有複數個外接 端214。該第一内表面211係以供該第一晶片220與該 第二晶片230之設置。在本實施例中，該些第一内接端 2 1 3係為插座，其係突出於該第一内表面2 11並可排列 在該第一晶片220之周邊，其中突出之高度係可概約等 於該第一晶片 220之厚度，或不相等。而該些外接端 2 1 4係為金屬塾，可為矩陣排列或多排周邊排列，以供 10 200937609 對外接合。具體而言，該第一基板210更具有一線路層 215，其係電性連接該些第一内接端213與該些外接端 214。通常該第一基板210係為一種具有線路結構之妨 4絕 緣基板，如印刷電路板、陶瓷基板或預模導線架 (pre-mold leadframe)，而與該第一晶片220内含之半導 體材質之熱膨脹係數稍有差異。 該第一晶片220係設於該第一基板210之該第—内 表面211上並具有複數個第一電極221。該些第一電極 © 221係遠離該第一基板210之該第一内表面211，並排 列於該第一晶片220之邊緣。通常該些第一電極221係 形成於該第一晶片220之主動表面並電性連接至該第 一晶片220内積體電路。在一黏晶過程中，利用一黏晶 層270之黏貼，使該第一晶片220之背面貼設在t亥第— 基板210上。 該第二晶片230係設於該第一晶片220上並具有複 ❹ 數個第二電極231。該第二晶片230係以該些第二電極 23 1朝上之方式疊設在該第一晶片220上。而該第二晶 片230在該第一晶片220上的設置方式係以不覆蓋該第 一晶片220之該些第一電極221為原則。例如’謗第二 晶片230之尺寸係可小於該第一晶片220之尺寸，針對 同晶片尺寸之實施例下，該第二晶片23 0可相對於該第 一晶片220產生位偏移或是角度旋轉，該第一晶片22〇 之該些第一電極221顯露在該第二晶片230之外。 請參閱第2圖所示，該第二基板240係設於該第一 11 200937609 基板210上，以使該第一晶片220與該第二晶片230被 夾合在該第一基板210與該第二基板24〇之間，該第二 基板24 0係具有一朝向該第一内表面211之第二内表面 241，該第二内表面241係設有複數個第二内接端242、 複數個第一電極接點243以及複數個第二電極接點 244。其中’該些第二内接端242係接合至該些第一内 接端213，該些第一電極接點243係接合至第一電極 221’該些第一電極接點244係接合至第二電極231。 ® 在本實施例中’該些第二内接端242、該些第一電極接 點243以及該些第二電極接點244皆係突出於該第二内 表面241’其中該些第二内接端242與該第一電極接點 243突出於該第二内表面241之高度係可概等於該第二 晶片23 0之厚度。具體而言，該第二基板24〇更具有一 線路層245’其係電性連接該些第二内接端242、該些 第一電極接點243以及該些第二電極接點2 44。在本實 ❿ 施例中，該第一基板210與該第二基板24〇係可具有相 同厚度與相同熱膨脹係數’達成上下層應力平衡，可降 低該半導體封裝構造200在封膠時與運算時的翹曲度。 因此，該第二基板240之接合能使該第一晶片22〇 與該第二晶片230電性連接至具有該些外接端214之該 第一基板210’取代習知之打線銲線，不會有越上層晶 片打線長度越長的問題’解決習知銲線不一致造成的訊 號延遲與電性短路之問題’並可縮小該半導體封裝構造 2 00之表面接合尺寸。並且，該第二基板24〇可平衡該 12 200937609 第一基板210之應力’使該半導體封裝構造200同時具 有受熱不易翹曲之功效。此外，以該第二基板240之一 次壓合達成多個晶片220與230電性連接至該第一基板 210之技術’相對於習知打線連接的逐條銲線形成與習 知覆晶接合每一晶片需一次覆晶接合操作方式，更能縮 短多晶片至基板的電性連接的製程週期時間。並且，藉 由該第二基板240能在不使用銲線的條件下達到多晶 片與基板之間的電性連接，故可降低製造成本。 在本實施例中，該第二晶片2 3 0係可直接設置於該 第一晶片220上，相對於習知在晶片之間設置間隔片， 更能降低該半導體封裝構造200之晶片堆疊厚度。 請再參閱第2圖所示，在本實施例中，該些第一電 極接點243與該些第二電極接點244係可分別包含有複 數個第一導通柱246以及複數個第二導通柱247，故該 第一基板240的壓合方式可沿用習知的覆晶接合設 備。較佳地，該些第一電極221與該些第二電極231係 可分別具有複數個第一定位孔222以及複數個第二定 位孔232，該些第一導通柱246係插接至該些第一定位 孔222，而該些第二導通柱247係插接至該些第二定位 孔232’方便定位該第二基板240並確保電性連接品 質。具體而言，該些第一定位孔222與該些第二定位孔 232内係可分別形成有導電材料223與233，例如導電 膠或銲料，以結合該些第一導通柱246與該些第二導通 柱247。較佳地，該些第一内接端213係可包含複數個 13 200937609 插座216’而該些第二内接端2 42係可包含複數個插柱 248’以使該些第一内接端213與該些第二内接端242 相互鎮欲’故能穩固地電性導通該第一基板210與該第 一基板240’在封膠時不會斷裂。在本實施例中，該些 插座216内係可形成有導電材料217，例如導電膠或銲 料’以結合該些插柱248。再如第2圖所示，該些第一 内接端213與該些第二内接端242之鑲嵌高度係可概約 相同於該第一晶片22〇與該第二晶片23〇之堆疊高度。 該半導體封裝構造200可另包含有一封膠體250， 其係形成在該第一基板21〇之該第一内表面211與該第 二基板240之第二内表面241之間並密封該第一晶片 220與該第二晶片230，以避免受外界污染物污染。在 本實施例中，該封膠體250係可進一步密封該第二基板 240之一外表面，甚至完全密封該第二基板24〇，以使 該半導體封裝構造20 0無法單由外觀目視得知具有多 ❹ 基板之結構，達到基板隱藏之效果。具體而言，該半導 體封裝構造200可另包含有複數個外接元件260，例如 銲球’其係設置於該些外接端214，故該半導體封裝構 造200可藉由該些外接元件260接合至一外部印刷電路 板（圖中未繪出）。 第3A至3F圖係用以具體說明一種前述半導體封裝 構造200之製造方法。首先，請參閱第3A圖所示，提 供該第一基板210，該第一内表面211係設有該些第一 内接端213’該外表面212係設有該些外接端214。該 14 200937609 第一基板210之線路層215係電性連接該些第一内接端 213與該些外接端214。在本實施例中，該些第一内接 端213係可包含複數個插座216，該些第一内接端213 係可突出於該第一内表面211，該些插座216内係可形 成有導電材料217« 之後’請參閱第3B圖所示，可利用一黏晶層270 黏著該第一晶片220之背面，將該第一晶片220設置於 該第一基板210之該第一内表面211。該第一晶片220 係以該些第一電極221朝上遠離該第一基板210的方式 設置在該第一基板210上。在本實施例中，該些第一電 極221係可具有複數個第一定位孔222，該些第一定位 孔222内係可形成有導電材料223。 接著’請參閱第3C圖所示，設置至少一之該第二晶 片230於該第一晶片22〇上，該第二晶片23〇之該些第 二電極23 1亦朝上的方式而遠離該第一基板210。在本 實施例中，該第二晶片230之尺寸係可小於該第一晶片 220之尺寸’以在堆疊時不遮蓋該第一晶片22〇之該些 第一電極221。在本實施例中，該些第二電極231係可 具有複數個第二定位孔232，該些第二定位孔232内係 可形成有導電材料233。 最後’請參閱第3D圖所示，利用熱壓合方式將該第 二基板240設置於該第一基板21〇上，以使該第一晶片 220與該第二晶片23〇被夾合在該第一基板21〇與該第 二基板240之間，該第二基板240係具有一朝向該第一 15 200937609 内表面211之第二内表面241。在壓合時，可同時使得 該第二基板240之該些第二内接端242係接合至該些第 一内接端213、該些第一電極接點243係接合至第一電 極221、該些第一電極接點244係接合至第二電極231。 在本實施例中’該些第一電極接點243與該些第二電極 接點244係可分別包含有複數個第一導通柱246與第二 導通柱247’其係分別插接至該些第一定位孔222與該 些第二定位孔232 ’並利用熱固化或回焊使導電材料 223與233結合該些第一導通柱246與該些第二導通柱 247。該些第二内接端242係可包含複數個插柱248， 可結合至該些插座216，以使在設置該第二基板24〇之 步驟中該些第一内接端213與該些第二内接端242達到 相互鑲嵌。 具體而言’請參閱第3E圖所示，該製造方法可另包 含一封膠步驟，例如模封方法，使該封膠體25〇形成在 該第一基板210之該第一内表面211與該第二基板24〇 之該第二内表面241之間’並密封該第一晶片22〇與該 第一晶片230。較佳地’該封膠體25〇可更覆蓋至該第 一基板240之一外表面。此外，請參閱第3F圖所示， 可利用焊球回焊技術，將複數個外接元件26〇設置於該 些外接端2 1 4。 在本發明之第二具體實施例中第4圖揭示另一種 晶片在基板之間的多晶片封裝構造之截面示意圖，其基 本架構係與第一具體實施例相同，但可堆疊更多晶 16 200937609 片。請參閱第4圖所示，該半導體封裝構造300主要 包含一第一基板310、一第一晶片32〇、至少一第二晶 片330以及一第二基板3 4〇。該第一基板310係具有 一第一内表面311與一外表面312，該第一内表面311 係設有複數個第一内接端313，可為貫穿或非貫穿之 導通孔。該外表面312係設有複數個外接端314，可 為金屬墊’以供植接複數個外接元件36〇。該些第一 内接端313係位於該第一基板310之周邊。在本實施 例中’該些第一内接端3 1 3係為貫穿以形成複數個定 位孔3 1 7。該第一晶片3 2 0係設於該第一基板3 1 0之 該第一内表面311並具有複數個第一電極321。請參 閱第4圖所示，該第二晶片330係設於該第一晶片320 上並具有複數個第二電極331。 該第二基板340係設於該第一基板310上，以使該 第一晶片320與該第二晶片330被夾合在該第一基板 310與該第二基板340之間，該第二基板340係具有 一朝向該第一内表面311之第二内表面341，該第二 内表面341係設有複數個第二内接端342、複數個第 一電極接點343以及複數個第二電極接點344，其中 該些第二内接端342係接合至該些第一内接端313， 該些第一電極接點343係接合至第一電極321，該些 第二電極接點344係接合至第二電極331。在本實施 例中，該些第二内接端342係可為導電插柱，其係穿 設於該第一基板310之該些定位孔317並與該些第一 17 200937609 内接端3 13電性連接。請參閱第4圖所示，該 電極接點343與該些第二電極接點344係可為 性之插針，以提供適當電性連接的彈性收縮。該 板340係具有一導電層345，電性連接該些第一 點3 43與該些第二電極接點344至對應之該些 一内接端342。在本實施例中，該半導體封裝構 另包含一支撐塊3 80’其係設置於該第二基板 較上層之第二晶片330之間，用以控制該第一基 與該第二基板3 4 0之間隙。 因此’利用該第二基板3 40與該些晶片320、 組合關係，該半導體封裝構造300能縮短該 320、330至該第一基板310的電性連接的製程 間。此外’同時具備有降低該半導體封裝構造 翹曲度與縮小該半導體封裝構造300之封裝尺 效0 以上所述’僅是本發明的較佳實施例而已， 本發明作任何形式上的限制，本發明技術方案範 所附申請專利範圍為準。任何熟悉本專業的技術 利用上述揭示的技術内容作出些許更動或修飾 變化的等效實施例，但凡是未脫離本發明技術方 容’依據本發明的技術實質對以上實施例所作的 單修改、等同變化與修飾，均仍屬於本發明技術 範圍内。 【圖式簡單說明】 些第一 具有彈 第二基 電極接 該些第 造300 340與 板310 330之 些晶片 週期時 300的 寸之功 並非對 圍當依 人員可 為等同 案的内 任何簡 方案的 18 200937609 第1圖： 習知晶片在基板上 意圖。 之半導體封裝構造之截面示 第2圖：依據本發明之第_ , 瑕貫施例，一種晶 板之間的半導體封裝構Ό讲種阳片在基 筮3A 構化之截面示意圖。 第3A至3F圖：依據本發 由 乐 具體實施例，在該 +導體封裝構造之遒起Λ ^ 4 ® 4- 中一基板截面示意圖。 第4圖.依據本發明之第二具 固 、體實施例，另一種半導體200937609 There are a plurality of 篦_# first electrodes 121. The first electrodes 110 are electrically connected to the first electrode 110 in the first die bonding process. Then, the second wafers 130 are stacked on the top of each of the two wafers 130. Each of the wafers 130 has a plurality of wafers; after the stack of Uo is stacked, the battery can be separated by 1 8 2 The second electrode 131 is connected to the encapsulant 150 to seal the first wafer 1 , the second wafer 130 , 181 from the substrate 110 . The first-pass-le-weld wire 182. Therefore, it is not known that the process cycle time of the semiconductor is not effective. In addition, the 190 is between the wafers 120 and 130 to prevent the upper wafer from being pressed under the bonding wire. The increase makes the package warpage problem more serious. Otherwise, the second bonding wires 182 are elongated as the second inter-crystallinity increases, and the problem of the tying is prone to occur in addition to the signal-delayed encapsulant 150. SUMMARY OF THE INVENTION The main object of the present invention is to provide a crystalline semiconductor package structure and a method of fabricating the same, which can electrically connect a first wafer and a second wafer to a substrate, which is connected to a conventional wire bonding. The strip forming method requires a flip-chip bonding operation mode, and the process period of the electrical connection of the stacked sheets to the substrate f is reduced to reduce the warpage of the multi-chip package structure, and thereafter, by the 1 2 1 The substrate is applied to the first wafer guest electrode 131. The second wire bonding substrates 1 10 . The first wire bond conductor package structure on the face 111 is shortened. A spacer is provided to make the package thickness. Referring to the stacking problem of Fig. 1 in Fig. 1, the formation of the sheet between the substrates - a substrate provided with an external end and a conventional flip chip can shorten multiple stacks 3. In addition, the size of the package size 7 200937609 is also reduced. A second object of the present invention is to provide a semiconductor package structure between a substrate and a manufacturing method thereof, which can solve the problem of signal delay and electrical short circuit caused by the longer wire bonding wire connecting the upper stack wafer in the conventional multi-chip stack. The problem. Another object of the present invention is to provide a semiconductor package structure of a wafer between substrates and a method of fabricating the same, and the second substrate can be bonded to the first substrate by a conventional flip chip bonding apparatus to reduce the device®. cost. Another object of the present invention is to provide a semiconductor package structure of a wafer between substrates and a method of fabricating the same, which can facilitate positioning of the substrates of the two bonded wafers and ensure the electrical connection quality of the substrates between the substrates. Another object of the present invention is to provide a semiconductor package structure of a wafer between substrates and a method of manufacturing the same, which can stably electrically conduct the first substrate and the second substrate without being broken during sealing. A. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The semiconductor package structure of the wafer between the substrates according to the present invention mainly includes a first substrate, a first wafer, at least a second wafer, and a second substrate. The first substrate has a first inner surface and an outer surface, and the first inner surface is provided with a plurality of first inner ends, and the outer surface is provided with a plurality of external ends. The first chip is disposed on the first inner surface of the first substrate and has a plurality of first electrodes. The second wafer is disposed on the first wafer and has a plurality of second electrodes. The second substrate is disposed on the first substrate such that the first substrate and the second wafer are sandwiched between the first substrate and the second substrate, and the second substrate has an orientation The second inner surface of the first inner surface is provided with a plurality of second inner ends, a plurality of first electrode contacts and a plurality of second electrode contacts, wherein the second inner contacts The end is bonded to the first inscribed ends, the first electrode contacts are bonded to the first electrode, and the second electrode contacts are bonded to the second electrode. Further, the aforementioned wafer is between the substrates Manufacturing method of semiconductor package structure. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package structure, the first electrode contacts and the second electrode contacts may include a plurality of conductive posts. In the foregoing semiconductor package structure, the first electrodes and the second electrode systems may have a plurality of positioning holes, and the conductive posts are plugged into the positioning holes. In the semiconductor package structure described above, the positioning holes may be formed with a conductive material. In the foregoing semiconductor package structure, the first inner terminals may include a plurality of sockets, and the second inner ends comprise a plurality of posts, so that the first inner ends and the second ends The internal ends are inlaid with each other. In the aforementioned semiconductor package construction, the sockets may be formed with a conductive material. In the semiconductor package construction just described, the first inscribed end and the second inscribed end are approximately the same as the stacking height of the first wafer and the first wafer. In the semiconductor package structure described above, a colloid may be further included between the first substrate and the second substrate to seal the first wafer and the second wafer. In the aforementioned semiconductor package construction, the encapsulation system can more seal one of the outer surfaces of the second substrate. In the foregoing semiconductor package structure, a plurality of external components may be further included and disposed on the external terminals. In the semiconductor package construction described above, the first substrate and the second substrate may have the same thickness and the same coefficient of thermal expansion. [Embodiment] According to a first embodiment of the present invention, a semiconductor package structure of a wafer between substrates is disclosed. Referring to FIG. 2, a semiconductor package structure 2 between a substrate (CBS) mainly includes a first substrate 210, a first wafer 220, at least a second wafer 230 φ, and a second substrate. 240. The first substrate 210 has a first inner surface 211 and an outer surface 212. The first inner surface 211 is provided with a plurality of first inner ends 213, and the outer surface 212 is provided with a plurality of external ends 214. The first inner surface 211 is provided for the first wafer 220 and the second wafer 230. In this embodiment, the first inner terminals 2 1 3 are sockets protruding from the first inner surface 2 11 and arranged around the first wafer 220, wherein the height of the protrusion is It is approximately equal to the thickness of the first wafer 220, or is not equal. The external terminals 2 1 4 are metal crucibles, which may be arranged in a matrix or in a plurality of rows to be externally joined by 10 200937609. Specifically, the first substrate 210 further has a circuit layer 215 electrically connected to the first inner ends 213 and the external ends 214. Generally, the first substrate 210 is a 4 insulating substrate having a line structure, such as a printed circuit board, a ceramic substrate or a pre-mold lead frame, and a semiconductor material contained in the first wafer 220. The coefficient of thermal expansion is slightly different. The first wafer 220 is disposed on the first inner surface 211 of the first substrate 210 and has a plurality of first electrodes 221. The first electrodes © 221 are away from the first inner surface 211 of the first substrate 210 and are arranged at the edge of the first wafer 220. Generally, the first electrodes 221 are formed on the active surface of the first wafer 220 and electrically connected to the integrated circuit in the first wafer 220. In a die bonding process, the back side of the first wafer 220 is attached to the substrate 12 by a bonding of a bonding layer 270. The second wafer 230 is disposed on the first wafer 220 and has a plurality of second electrodes 231. The second wafer 230 is stacked on the first wafer 220 with the second electrodes 23 1 facing upward. The second wafer 230 is disposed on the first wafer 220 in such a manner as not to cover the first electrodes 221 of the first wafer 220. For example, the size of the second wafer 230 can be smaller than the size of the first wafer 220. For the same wafer size embodiment, the second wafer 230 can be shifted or angled relative to the first wafer 220. Rotating, the first electrodes 221 of the first wafer 22 are exposed outside the second wafer 230. As shown in FIG. 2 , the second substrate 240 is disposed on the first 11 200937609 substrate 210 such that the first wafer 220 and the second wafer 230 are sandwiched between the first substrate 210 and the first substrate 210 . The second substrate 205 has a second inner surface 241 facing the first inner surface 211, and the second inner surface 241 is provided with a plurality of second inner ends 242 and a plurality of The first electrode contact 243 and the plurality of second electrode contacts 244. Wherein the second inscribed ends 242 are bonded to the first inscribed ends 213, the first electrode contacts 243 are bonded to the first electrodes 221'. The first electrode contacts 244 are bonded to the first Two electrodes 231. In the present embodiment, the second inner terminals 242, the first electrode contacts 243, and the second electrode contacts 244 protrude from the second inner surface 241' The height at which the terminal 242 and the first electrode contact 243 protrude from the second inner surface 241 may be substantially equal to the thickness of the second wafer 230. Specifically, the second substrate 24 is further provided with a circuit layer 245' electrically connected to the second internal terminals 242, the first electrode contacts 243, and the second electrode contacts 2 44. In this embodiment, the first substrate 210 and the second substrate 24 can have the same thickness and the same thermal expansion coefficient 'to achieve upper and lower layer stress balance, which can reduce the semiconductor package structure 200 during sealing and operation. Warpage. Therefore, the bonding of the second substrate 240 enables the first wafer 22 and the second wafer 230 to be electrically connected to the first substrate 210 ′ having the external terminals 214 instead of the conventional bonding wire. The longer the length of the upper layer wafer is, the longer the problem of the signal delay and the electrical short circuit caused by the inconsistency of the conventional solder wire, and the surface joint size of the semiconductor package structure 200 can be reduced. Moreover, the second substrate 24 〇 can balance the stress of the first substrate 210 of the 12 200937609 so that the semiconductor package structure 200 has the effect of being less susceptible to warpage by heat. In addition, the technique of electrically connecting the plurality of wafers 220 and 230 to the first substrate 210 by the first pressing of the second substrate 240 is formed by a conventional wire bonding connection with a conventional wire bonding connection. A wafer requires a flip-chip bonding operation, which further shortens the process cycle time of the electrical connection of the multi-chip to the substrate. Moreover, the second substrate 240 can achieve electrical connection between the polycrystalline wafer and the substrate without using a bonding wire, so that the manufacturing cost can be reduced. In this embodiment, the second wafer 230 can be directly disposed on the first wafer 220. The spacer stack is disposed between the wafers to reduce the thickness of the wafer stack of the semiconductor package structure 200. Referring to FIG. 2 again, in the embodiment, the first electrode contacts 243 and the second electrode contacts 244 respectively include a plurality of first conductive posts 246 and a plurality of second conductive contacts. The pillars 247, so that the first substrate 240 can be pressed together by a conventional flip chip bonding apparatus. Preferably, the first electrodes 221 and the second electrodes 231 respectively have a plurality of first positioning holes 222 and a plurality of second positioning holes 232, and the first conductive posts 246 are plugged into the The first positioning holes 222 are inserted into the second positioning holes 232 ′ to facilitate positioning of the second substrate 240 and ensure electrical connection quality. Specifically, the first positioning holes 222 and the second positioning holes 232 are respectively formed with conductive materials 223 and 233, such as conductive glue or solder, to combine the first conductive posts 246 and the first Two conductive posts 247. Preferably, the first inscribed ends 213 can include a plurality of 13 200937609 sockets 216 ′ and the second inscribed ends 2 42 can include a plurality of posts 248 ′ to enable the first inscribed ends The 213 and the second interconnecting ends 242 are mutually accommodating, so that the first substrate 210 and the first substrate 240' can be stably electrically turned off without being broken at the time of sealing. In the present embodiment, the sockets 216 may be formed with a conductive material 217, such as a conductive paste or solder, to bond the posts 248. As shown in FIG. 2, the inlay heights of the first inner end 213 and the second inner ends 242 may be substantially the same as the stack height of the first wafer 22 and the second wafer 23 . The semiconductor package structure 200 can further include a glue body 250 formed between the first inner surface 211 of the first substrate 21 and the second inner surface 241 of the second substrate 240 and sealing the first wafer. 220 and the second wafer 230 to avoid contamination by external pollutants. In this embodiment, the encapsulant 250 can further seal the outer surface of the second substrate 240, or even completely seal the second substrate 24, so that the semiconductor package structure 20 cannot be visually recognized by the appearance. The structure of the substrate is multi-layered to achieve the effect of hiding the substrate. In particular, the semiconductor package structure 200 can further include a plurality of external components 260, such as solder balls, which are disposed on the external terminals 214. Therefore, the semiconductor package structure 200 can be bonded to the external component 260. External printed circuit board (not shown). 3A to 3F are views for specifically explaining a method of manufacturing the aforementioned semiconductor package structure 200. First, as shown in FIG. 3A, the first substrate 210 is provided. The first inner surface 211 is provided with the first inner ends 213'. The outer surface 212 is provided with the external ends 214. The circuit layer 215 of the first substrate 210 is electrically connected to the first inner terminals 213 and the external terminals 214. In this embodiment, the first inscribed end 213 can include a plurality of sockets 216, and the first inscribed ends 213 can protrude from the first inner surface 211, and the sockets 216 can be formed therein. The conductive material 217 « subsequent ', as shown in FIG. 3B , a back surface of the first wafer 220 may be adhered by a bonding layer 270 , and the first wafer 220 is disposed on the first inner surface 211 of the first substrate 210 . . The first wafer 220 is disposed on the first substrate 210 such that the first electrodes 221 face away from the first substrate 210. In this embodiment, the first electrodes 221 can have a plurality of first positioning holes 222, and the first positioning holes 222 can be formed with a conductive material 223. Then, as shown in FIG. 3C, at least one of the second wafers 230 is disposed on the first wafer 22, and the second electrodes 23 1 of the second wafer 23 are also facing away from the The first substrate 210. In this embodiment, the size of the second wafer 230 can be smaller than the size of the first wafer 220 to cover the first electrodes 221 of the first wafer 22 when stacked. In this embodiment, the second electrodes 231 can have a plurality of second positioning holes 232, and the second positioning holes 232 can be formed with a conductive material 233. Finally, please refer to FIG. 3D, the second substrate 240 is disposed on the first substrate 21 by thermocompression bonding, so that the first wafer 220 and the second wafer 23 are sandwiched. Between the first substrate 21A and the second substrate 240, the second substrate 240 has a second inner surface 241 facing the inner surface 211 of the first 15200937609. At the same time, the second inscribed ends 242 of the second substrate 240 are simultaneously bonded to the first inscribed ends 213, and the first electrode contacts 243 are bonded to the first electrodes 221, The first electrode contacts 244 are bonded to the second electrode 231. In the present embodiment, the first electrode contacts 243 and the second electrode contacts 244 may respectively include a plurality of first conductive pillars 246 and second conductive pillars 247 ′ respectively The first positioning holes 222 and the second positioning holes 232 ′ are used to bond the conductive materials 223 and 233 to the first conductive pillars 246 and the second conductive pillars 247 by thermal curing or reflow. The second inscribed ends 242 can include a plurality of posts 248 that can be coupled to the sockets 216 such that the first inscribed ends 213 and the first portions are disposed in the step of disposing the second substrate 24 The two inner ends 242 are inlaid with each other. Specifically, as shown in FIG. 3E , the manufacturing method may further include a glue step, such as a molding method, such that the sealant 25 is formed on the first inner surface 211 of the first substrate 210 and the The second substrate 24 is between the second inner surface 241 and seals the first wafer 22 and the first wafer 230. Preferably, the encapsulant 25 更 covers the outer surface of one of the first substrates 240. In addition, as shown in Fig. 3F, a plurality of external components 26 can be disposed on the external terminals 2 14 by solder ball reflow technology. In a second embodiment of the present invention, FIG. 4 is a cross-sectional view showing a multi-chip package structure of another wafer between substrates, the basic structure of which is the same as that of the first embodiment, but more crystals can be stacked 16 200937609 sheet. Referring to FIG. 4, the semiconductor package structure 300 mainly includes a first substrate 310, a first wafer 32, at least a second wafer 330, and a second substrate 34. The first substrate 310 has a first inner surface 311 and an outer surface 312. The first inner surface 311 is provided with a plurality of first inner ends 313, which may be through or non-penetrating through holes. The outer surface 312 is provided with a plurality of external ends 314 which may be metal pads for planting a plurality of external components 36. The first inner terminals 313 are located at the periphery of the first substrate 310. In the present embodiment, the first intermeshing ends 3 1 3 are penetrated to form a plurality of positioning holes 3 17 . The first wafer 320 is disposed on the first inner surface 311 of the first substrate 310 and has a plurality of first electrodes 321. Referring to FIG. 4, the second wafer 330 is disposed on the first wafer 320 and has a plurality of second electrodes 331. The second substrate 340 is disposed on the first substrate 310 such that the first wafer 320 and the second wafer 330 are sandwiched between the first substrate 310 and the second substrate 340. The second substrate The 340 has a second inner surface 341 facing the first inner surface 311. The second inner surface 341 is provided with a plurality of second inner ends 342, a plurality of first electrode contacts 343, and a plurality of second electrodes. a contact 344, wherein the second inner ends 342 are coupled to the first inner ends 313, the first electrode contacts 343 are bonded to the first electrodes 321 , and the second electrode contacts 344 are Bonded to the second electrode 331. In this embodiment, the second inscribed ends 342 can be electrically conductive posts, and are disposed through the positioning holes 317 of the first substrate 310 and the first 17 200937609 internal terminals 3 13 Electrical connection. Referring to Figure 4, the electrode contacts 343 and the second electrode contacts 344 are sexual pins to provide elastic contraction of a suitable electrical connection. The board 340 has a conductive layer 345 electrically connected to the first point 343 and the second electrode contacts 344 to the corresponding inner ends 342. In this embodiment, the semiconductor package further includes a support block 380' disposed between the second wafer 330 of the upper layer of the second substrate for controlling the first substrate and the second substrate 34. 0 gap. Therefore, by using the second substrate 340 and the wafers 320 in combination, the semiconductor package structure 300 can shorten the process of electrically connecting the 320, 330 to the first substrate 310. In addition, the invention has the advantages of reducing the warpage of the semiconductor package structure and reducing the package size of the semiconductor package structure 300. The above description is merely a preferred embodiment of the present invention, and the present invention imposes any form limitation. The scope of the patent application attached to the invention is subject to the scope of the patent application. Any of the equivalents of the above-described embodiments may be modified or modified in accordance with the technical scope of the present invention without any departure from the technical scope of the present invention. Variations and modifications are still within the technical scope of the present invention. [Simplified description of the drawing] The first inch of the second base electrode is connected to the chip 300 340 and the plate 310 330 of the chip cycle is not the right one. Scheme 18 200937609 Figure 1: Conventional wafer on the substrate intended. Cross section of the semiconductor package structure Fig. 2: According to the invention, a semiconductor package structure between the crystal plates is a schematic cross-sectional view of the green sheet at the base 3A. 3A to 3F are schematic cross-sectional views of a substrate in the +conductor package structure according to the embodiment of the present invention. Figure 4 is a second embodiment of the present invention, another semiconductor
、裝構造之截面示意圖。 【主要元件符號說明】Schematic diagram of the structure of the installation. [Main component symbol description]
100半導體封裝構造 110 基板 111 内表面 120 第一 晶片 121 第- -電極 130 第二 晶片 131 第二 =電極 150 封膠體 160 外接元件 181 第一 銲線 182 第二 二銲線 200 半導體封装構 造 210 第一 基板 211 第- -内表面 213 第一 内接端 214 外接端 216 插座 217 導電材料 220 第一 晶片 221 第- 一電極 223 導電 材料 230第二晶片 233導電材料 240第二基板 231第二電極 241第二内表面 11 2外表面 190間隔片 2 12外表面 215線路層 222第一定位孔 2 3 2第二定位孔 242第二内接端 19 200937609 243 第一電極接點 244 第二電極接點 245 線路層 246 第一導通柱 247 第二導通柱 248 插柱 250 封膠體 260 外接元件 270 黏晶層 300 半導體封裝構造 310 第一基板 311 第一内表面 312 外表面 313 第一内接端 314 外接端 317 定位孔 320 第一晶片 321 第一電極 330 第二晶片 331 第二電極 340 第二基板 341 第二内表面 342 第二内接端 343 第一電極接點 344 第二電極接點 345 線路層 360 外接元件 380 支撐塊 ⑩ 20100 semiconductor package structure 110 substrate 111 inner surface 120 first wafer 121 first - electrode 130 second wafer 131 second = electrode 150 encapsulant 160 external component 181 first bonding wire 182 second two bonding wire 200 semiconductor package structure 210 A substrate 211 first - inner surface 213 first inner end 214 external end 216 socket 217 conductive material 220 first wafer 221 first electrode 223 conductive material 230 second wafer 233 conductive material 240 second substrate 231 second electrode 241 Second inner surface 11 2 outer surface 190 spacer 2 12 outer surface 215 circuit layer 222 first positioning hole 2 3 2 second positioning hole 242 second inner end 19 200937609 243 first electrode contact 244 second electrode contact 245 circuit layer 246 first conductive pillar 247 second conductive pillar 248 plug 250 sealing body 260 external component 270 adhesive layer 300 semiconductor package structure 310 first substrate 311 first inner surface 312 outer surface 313 first inner end 314 external End 317 positioning hole 320 first wafer 321 first electrode 330 second wafer 331 second electrode 340 second substrate 341 second inner surface 342 second inner end 343 first electrode contact 344 second electrode contact 345 circuit layer 360 external component 380 support block 10 20