6〇»77 * 九、發明說明： 【所屬之技術領域】 窗口本型發半明導係體？於半導體裝置，特別係有闕於一種可㈣ 丰導體封裝構造及其堆疊結構。 【无别技術】 曰電路载板越來越小時，其 面積亦縮小。目，古u 其表面可供女裝元件的 ^ Μ ^ ^ 月 提出可以將多個窗口型半導體封 装構造相互縱向堆疊 訂 以即^佔據在印刷電路板上的面 積’具係在夕個習知窗 湖锃#桃^ !牛導體封裝構造之間以複數 個t球縱向電性連接該些窗口型半導體封裝構造。而採 用銲球除了會有斷裂問題外，銲球必須變大才可提供足 夠堆疊間隔，除了會有掉球之問題，並且該窗口型半導 礞封裝構造並無法達到高密度端子數之要求。此外，在 迴銲銲球（Solder Reflow)以進行時封裝堆疊時，易有封 装位移偏斜的問題。 請參閱第1圖所示，一種習知窗口型半導體封裝構 造100係包含一基板Π0、一晶片120、複數個電性連 接元件130、一模封膠體140以及複數個銲球15〇。該 基板110係具·有一上表面111、一下表面112以及一槽 孔113。該晶片120係設置於該基板110之該上表面in 並具有複數個銲墊123。藉由該些電性連接元件130通 過該槽孔113以電性連接該些銲墊123至該基板i 1〇之 該下表面112。該模封膠體140係局部覆篕該基板n〇 之該上表面111以密封該晶片120’並且該模封膠體140 Γ360877 更填入該槽孔113並突出於該基板11〇之該下表面il2 以密封該些電性連接元件130。該些銲球150係設置於 該基板110之該下表面112，以供該窗口型半導體封褒 構造1〇〇可接合至一電路載板（圖未繪出）或是堆疊接合 至另一固口型半導體封裝構造100之基板11〇之上表面 1 1 1(如第2圖所示）。 請參閱第2圖所示，多個習知窗口型半導體封裝構 造100係相互堆疊並藉由該些銲球15〇電性連接位於較 下方之窗口型半導體封裝構造1〇〇。在進行封裝堆叠 時’該些銲球150需經過一道迴銲（Refl〇w)步驟才可銲 接至另 ® 口型半導體封裝構造100。然而，在迴銲過 程中，該些if•球150會溶融’而造成位於上方之窗口型 半導體封裝構造1〇〇產生位移或是歪斜之情況，當位移 或傾斜之角度過大時，會導致部分銲球被拉長變形而無 法確實連接位於下方之窗口型半導體封裝構造1〇〇，甚 至會造成位於上方之窗口型半導體封裝構造1〇〇發生 掉球之情況，而導致電性連接不良或斷路等問題，進而 降低產品之可靠性。 【發明内容】 本發明之主要目的係在於提供一種可堆疊窗口型半導體 封裝構造及其堆疊結構’達到貫穿在模封膠體之上下電性導 通’符合高密度端子數與穩固的封裝堆疊。並能取代習知窗 口型半導體封裝構造之銲球進行封裝堆疊而不會有掉球與 歪斜的問題。 ' 本發明之次—目的係在於提供一種可堆疊窗口型半導體 封裝構造及其堆疊結構，可符合高密度端子數封裝堆疊之需 求並且不需要增加元件以達到水平穩固，以控制在-較為準 確之封裝堆疊厚度。 —本發月的目的及解決其技術問題是採用以下技術方案來 :現：。依據本發明之一種可堆疊窗口型半導體封裝構造， 主要包含《板、—晶片、複數個電性連接元件、一模封 體以及複數個導體柱。該基板係具有一上表面、一下表面、 -槽孔以及複數個周邊外接塾。該晶片係設置於該基板之該 上表面並具有複數個銲墊。該些電性連接元件係通過該槽孔 ^使該晶k料料€㈣接至該純之該㈣邊外接 。該模封膠體係主要形成於該基板之該上表面，並具有突 出於該下表面之—* φ φ 44- 中央封膠條以及複數個側封膠體，其中該 央封膝條係覆蓋該槽孔並密封該些電性連減件，該些側 谱膠體係覆蓋該些周邊外接堅。該些導體柱係對準於該些周 邊：外接墊並貫穿# 員芽該模封膠體在該基板之該上表面上的部 、該基板以及該些側封膠體。 體 述之可堆疊囪口型半導體封裝構造中，該些側封膠 糸可具有與該中央封膠條大致為共平面之疊置表面。 在别述之可堆疊窗口型半導體封裝構造中，該些側封谬 體係可包含複數個絕緣凸塊。 體係述之可堆疊齒口型半導體封裝構造中，該些側封膠 體係可為條狀並與該中央封膠條大致平行配置。 在别述之可堆疊窗口型半導體封裝構造中，該些電性連 1.360877 接元件係可包含複數個銲線，其中該些銲線之弧高係不 超過該中央封膠條。 在前述之可堆疊窗口型半導體封裝構造中，該模封膠體 係可完全密封該晶片。 、 在刖述之可堆疊窗口型半導體封裝構造中，該晶片係可 具有顯露於該模封膠體之一背面。 【實施方式】 依本發明之第一具體實施例，配合參閱第3至5圖揭示 一種可堆疊窗口型半導體封裝構造。請參閲第3圖所示，一 種可堆疊窗口型半導體封裝構造2〇〇主要包含一基板21〇、 b曰片220複數個電性連接元件230、一模封膠體240以 及複數個導體柱250。該基板210係具有一上表面211、— 下表面212、一槽孔213以及複數個周邊外接墊214 ◊該基 板210係可適用於「晶片在基板上」之窗口型封裝型態，藉 由該貫穿該上表面211與該下表面212之槽孔213，以供如 • 打線連接等方式達到該晶片220與該基板210之電性連接。 該些周邊外接墊214係位於該基板21〇之該下表面212之周 邊’可位於兩相對側邊或四周側邊。 請參閲第3圖所示，該晶片22〇係設置於該基板21〇之 該上表面211。該晶片220係可為高頻記憶體晶片或其他積 體電路晶片。該晶片220係具有一主動面221與一相對之背 面222並具有複數個銲墊223,該些銲墊223係位於該主動 之中央區域並可為雙排銲塾，但亦可為單排排列。通 常係以—黏晶層260,例如雙面黏著膠帶或B階膠體，將該 Γ360877 晶片220之該主動面22 i黏貼至該基板210之該上表面 211 ’並使該些銲墊223係對準於該槽孔213内，以供後續 電性連接。6〇»77 * IX. Description of the invention: [Technical field] The window type is a semi-conscious system? In the semiconductor device, in particular, it is suitable for a (four) conductor package structure and a stacked structure thereof. [No other technology] 曰 The circuit board is getting smaller and smaller, and its area is also reduced.目 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,窗湖锃#桃^! The plurality of t-balls are electrically connected to the window-type semiconductor package structures in a longitudinal direction between the cow conductor package structures. In addition to the problem of cracking in the use of solder balls, the solder balls must be enlarged to provide sufficient stacking intervals, in addition to the problem of falling balls, and the window type semi-conductive package structure cannot meet the requirements of the number of high-density terminals. In addition, when the solder ball (Solder Reflow) is packaged for stacking, there is a problem that the package displacement is skewed. Referring to FIG. 1, a conventional window type semiconductor package structure 100 includes a substrate Π0, a wafer 120, a plurality of electrical connection elements 130, a molding compound 140, and a plurality of solder balls 15A. The substrate 110 has an upper surface 111, a lower surface 112, and a slot 113. The wafer 120 is disposed on the upper surface in the substrate 110 and has a plurality of pads 123. The pads 123 are electrically connected to the lower surface 112 of the substrate i 1 through the slots 113. The molding compound 140 partially covers the upper surface 111 of the substrate n to seal the wafer 120' and the molding compound 140 Γ 360877 is further filled into the slot 113 and protrudes from the lower surface il2 of the substrate 11 To seal the electrical connection elements 130. The solder balls 150 are disposed on the lower surface 112 of the substrate 110 for the window-type semiconductor package structure 1 to be bonded to a circuit carrier (not shown) or stacked to another solid The upper surface 11 1 of the substrate 11 of the die-type semiconductor package structure 100 (as shown in FIG. 2). Referring to FIG. 2, a plurality of conventional window type semiconductor package structures 100 are stacked on each other and electrically connected to the lower window semiconductor package structure 1 by the solder balls 15A. When the package is stacked, the solder balls 150 are subjected to a reflow process to be soldered to the other-port semiconductor package structure 100. However, during the reflow process, the if balls 150 will melt and cause the displacement or skew of the window-type semiconductor package structure located above. When the angle of displacement or tilt is too large, it will cause a part. The solder ball is elongated and deformed and cannot be reliably connected to the window-type semiconductor package structure located below, and may even cause the ball-type semiconductor package structure 1 above to drop the ball, resulting in poor electrical connection or open circuit. And other issues, which in turn reduces the reliability of the product. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a stackable window-type semiconductor package structure and a stacked structure thereof that achieve electrical conduction through a high-density terminal and a stable package stack. It can replace the solder ball of the conventional window type semiconductor package structure for package stacking without the problem of ball drop and skew. The second aspect of the present invention is to provide a stackable window type semiconductor package structure and a stack structure thereof, which can meet the requirements of high-density terminal number package stacking and does not need to add components to achieve water-stable solidity, so as to control - more accurate Package thickness. - The purpose of this month and the resolution of its technical problems are to use the following technical solutions: A stackable window type semiconductor package structure according to the present invention mainly comprises a board, a wafer, a plurality of electrical connecting elements, a mold sealing body and a plurality of conductor columns. The substrate has an upper surface, a lower surface, a slot, and a plurality of peripheral lands. The wafer is disposed on the upper surface of the substrate and has a plurality of pads. The electrical connecting elements pass through the slot to connect the crystal k material (4) to the pure (four) side. The molding compound system is mainly formed on the upper surface of the substrate, and has a **φ φ 44- central sealing strip protruding from the lower surface and a plurality of side sealing gels, wherein the central sealing knee strip covers the groove The holes are sealed and the electrical connecting members are sealed, and the side spectral adhesive systems cover the peripheral external joints. The conductor posts are aligned with the periphery: an circumscribing pad and a portion of the molding compound on the upper surface of the substrate, the substrate, and the side sealants. In the stackable dome-type semiconductor package construction, the side seals may have a substantially coplanar overlapping surface with the central sealant. In a stackable window type semiconductor package construction, the side seal system may include a plurality of insulating bumps. In the stackable bevel type semiconductor package construction described in the system, the side sealant systems may be strip-shaped and disposed substantially parallel to the central sealant strip. In an alternative stackable window type semiconductor package structure, the electrical connection 1.360877 connection component may comprise a plurality of bonding wires, wherein the bonding wires have an arc height not exceeding the central sealing strip. In the aforementioned stackable window type semiconductor package construction, the mold sealant can completely seal the wafer. In the above-described stackable window type semiconductor package structure, the wafer system may have a back surface exposed on one of the mold sealing bodies. [Embodiment] According to a first embodiment of the present invention, a stackable window type semiconductor package structure is disclosed with reference to Figures 3 to 5. Referring to FIG. 3 , a stackable window type semiconductor package structure 2 〇〇 mainly includes a substrate 21 , a plurality of electrical connection elements 230 , a mold sealing body 240 , and a plurality of conductor columns 250 . . The substrate 210 has an upper surface 211, a lower surface 212, a slot 213, and a plurality of peripheral ferrules 214. The substrate 210 is applicable to a window-type package type of "wafer on the substrate". The through hole 213 of the upper surface 211 and the lower surface 212 is connected to the substrate 220 to be electrically connected to the substrate 210. The peripheral ferrules 214 are located on the periphery of the lower surface 212 of the substrate 21, and may be located on opposite sides or sides. Referring to Fig. 3, the wafer 22 is disposed on the upper surface 211 of the substrate 21A. The wafer 220 can be a high frequency memory chip or other integrated circuit chip. The wafer 220 has an active surface 221 and an opposite back surface 222 and has a plurality of solder pads 223. The solder pads 223 are located in the active central region and may be double-row solder pads, but may also be arranged in a single row. . Generally, the active layer 22 i of the Γ360877 wafer 220 is adhered to the upper surface 211 ′ of the substrate 210 by using a viscous layer 260, such as a double-sided adhesive tape or a B-stage colloid, and the pads 223 are paired. It is within the slot 213 for subsequent electrical connection.
該些電性連接元件230係通過該槽孔213以使該晶片220 之該些銲塾223電性連接至該基板21〇之該些周邊外接墊 214。具體而言，該些銲墊223係藉由該些電性連接元件23〇 連接至該基板210之該下表面212之接指（圖未繪出），再經 由該基板210本身之内線路層將電訊傳導至該些周邊外接墊 214達到該晶片220與該基板21〇之電性互連。 請參閱第3圖所示，該模封膠體24〇係主要形成於該基 板210之該上表面211，並具有突出於該下表面212之一中 央封膠條241以及複數個側封膠體242，其中該中央封膠條 241係覆蓋該槽孔213並密‘該些電性連接元件23〇，該些 側封膠體242係覆蓋該些周邊外接墊川。#由該些側封膜 體242使該模封膠體24〇係完全覆蓋該基板2ι〇之該下表面 之侧邊’以提供封裝堆疊之兩側支撐，以在封裝堆疊時 維持較佳的水平面，此外亦有助於兩側模流平衡，避免在填 充該槽孔213以形成該中央封膠條241時產生中央模流速度 過决而導致溢膝。在本實施例中，該模封膠體_係可完全 密封該晶片220。再如第3圖所示，該 係可包含複數個銲線，其中兮此^ 、甲。二知線之弧1¾係不超過該中央 兮膠條241 ’以避免該些銲線外露造成電性短路。較佳地， 孩些側封膠體242係可且丄 八有”該中央封膠條241大致為共平 面之疊置表面（如第3圖之水 叫〜％十虛線所不），以避免因堆叠歪 1360877 斜所導致電性連接不完整之問題。請參閱第4圖所示，該些 側封谬體242係可包含複數個絕緣凸塊，該些側封膠體242 係不遮蓋該些導體柱250,故可藉由該些導體柱25〇在該可 . 堆疊窗口型半導體封裝構造200與堆疊於另一可堆疊窗口型 半導體封裝構造200之間提供縱向的電性連接（如第5圖所 示）。 請再參閱第3圖所示，該些導體柱250係對準於該些周 籲 邊外接墊214並貫穿該模封膠體240在該基板210之該上表 面211上的部位、該基板21〇以及該些側封膠體242，達到 貫穿在該模封膠體240之上下電性導通。該些導體柱25〇之 材質係可為具有良好導電性與導熱性較佳的金屬，例如銅。 因此，該些導體柱250不僅能達到貫穿在該模封膠體24〇之 上下電性導通以符合高密度端子數之封裝堆疊之需求，配合 該些侧封膠體242能取代習知窗口型半導體封裝構造之銲球 進行封裝堆疊而不會有掉球與歪斜的問題。由於本發明之該 • 可堆疊窗口型半導體封裝構造200不需使用習知銲球之迴銲 步驟以達到電性連接之目的，於封裝堆疊時將具有較佳的水 平面與穩固性（如第5圖所示），更可控制在一較為準確之封 裝堆疊厚度。此外，如第4圖所示，在該基板21〇之該下表 面212無需設置球墊，故即使該模封膠體24〇產生溢膠也不 會影響電性連接之品質。 本發明進一步揭示一種前述之可堆疊窗口型半導體封裳 構造200之堆疊結構。請參閱第5圖所示，該堆疊結構主要 包含複數個如前所述之可堆疊窗口型半導體封裝構造2〇〇、 1360877 =路載板】G以及複數個外接端子2Q。該電路載板ι〇係具 頂面11以及-相對之底面12，該頂面n係形成有複數 j接塾13,該些接塾13係位於該電路載板1〇之兩相對側。 請參閱第5®所示’該些可堆疊窗口型半導體封裝構造綱 Μ㈣該電㈣板1G之該頂面u並藉由該些導體柱25〇 ，性導通至該電路载板1G之該些接塾13，以達到該些可堆 豎窗口型半導體封裝構造2〇〇與該電路载板ι〇之電性互 連。該些可堆疊窗口型半導體封裝構造彻係為縱向堆疊， 位於較下方之可堆疊窗口型半導體封裝構造㈣係藉由該些 導體柱250與位於較上方之可堆疊窗口型半導體封裝構造 =〇之該些導體柱25G電性連接，亦可與位於下方之可堆疊 "型半導體封裝構造之該些導體柱25Q電性連接或與 該電路載板10之該些接墊13連接。具體而論，每一可堆疊 窗口型半導體封裝構造可另包含㈣著材料3G，其係形 成於該中央封膠條241與該些側封膠體242之間，以黏接下 方的另一可堆疊窗口型半導體封裝構& 2〇〇或該電路載板 10。該些外接端子20係設置於該電路載板1〇之該底面。。 由上述可知，該些可堆疊窗口型半導體封裝構造200在 封裝堆疊過程中，藉由該些導體柱25()與被貫穿之側封膠體 242取代f知銲球。位於較上方之可堆疊窗口型半導體封裝 2造200之該些導體柱25〇係直接連接位於較下方之可堆疊 固口型半導體封裝構造·，符合高密度端子數與穩固的封 裝堆疊°因此’能取代習知窗π型半導體封裝構造之辉球進 行封裝堆疊而不會有掉球與歪斜的問題，亦可縮短該些可堆 1360877 叠窗口型半導體封裝構造200之間電氣連接的長度，以降低 該些可堆疊窗口型半導體封裝構造200之間因訊號傳遞路徑 太長而導致延遲的現象。 在本發明之第二具體實施例中’請參閱第6圖所示，揭 不另一種可堆疊窗口型半導體封裝構造300主要包含一基板 3 1 〇 Μ片320、複數個電性連接元件330、一模封夥體340 以及複數個導體柱350。該基板310係具有一上表面311、The electrical connection elements 230 pass through the slots 213 to electrically connect the solder pads 223 of the wafer 220 to the peripheral external pads 214 of the substrate 21 . Specifically, the pads 223 are connected to the contacts (not shown) of the lower surface 212 of the substrate 210 by the electrical connecting elements 23, and then through the circuit layer of the substrate 210 itself. Telecommunications are conducted to the peripheral external pads 214 to electrically interconnect the wafer 220 with the substrate 21A. Referring to FIG. 3, the molding compound 24 is mainly formed on the upper surface 211 of the substrate 210, and has a central sealing strip 241 protruding from the lower surface 212 and a plurality of side sealing bodies 242. The central sealing strip 241 covers the slot 213 and closes the electrical connecting elements 23, and the side sealing bodies 242 cover the peripheral circumflex pads. The side seals 24 are completely covered by the side seal film body 242 to completely cover the side edges of the lower surface of the substrate 2 ι to provide support on both sides of the package stack to maintain a better horizontal level during package stacking. In addition, it also contributes to the balance of the mold flow on both sides, and avoids the occurrence of a central mold flow speed overshoot when the slot 213 is filled to form the central sealant strip 241, resulting in an overflow of the knee. In this embodiment, the molding compound can completely seal the wafer 220. As shown in Fig. 3, the system can include a plurality of bonding wires, wherein the ^, A. The arc of the two wires does not exceed the central rubber strip 241' to avoid electrical shorting caused by the exposed wires. Preferably, the side sealant 242 is configurable and has a substantially coplanar superposed surface (as shown in Figure 3, the water is called ~% of the dotted line) to avoid Stacking 歪 1360877 obliquely causes incomplete electrical connection. Referring to Figure 4, the side sealing bodies 242 can include a plurality of insulating bumps, and the side sealing bodies 242 do not cover the conductors. The post 250 can provide a longitudinal electrical connection between the stackable window-type semiconductor package structure 200 and another stackable window-type semiconductor package structure 200 by the conductor posts 25 (eg, Figure 5) As shown in FIG. 3, the conductor posts 250 are aligned with the peripheral outer pads 214 and penetrate the portion of the molding compound 240 on the upper surface 211 of the substrate 210, The substrate 21A and the side seals 242 are electrically connected to the mold encapsulation body 240. The conductive pillars 25 are made of a metal having good conductivity and thermal conductivity, for example, Therefore, the conductor posts 250 can not only reach through The sealing body 24 下 is electrically connected to meet the requirements of the package stack of the high-density terminal number, and the side sealing body 242 can replace the solder ball of the conventional window-type semiconductor package structure for package stacking without dropping the ball and The problem of skewing. Since the stackable window type semiconductor package structure 200 of the present invention does not require the use of a conventional solder ball reflow step for electrical connection, it will have better horizontal and stable properties when packaged and stacked. (As shown in Fig. 5), it is more controllable in a more accurate package stack thickness. Further, as shown in Fig. 4, the lower surface 212 of the substrate 21 is not required to be provided with a ball pad, so even the mold seal The colloid 24 does not affect the quality of the electrical connection. The present invention further discloses a stack structure of the aforementioned stackable window type semiconductor package structure 200. Referring to FIG. 5, the stacked structure mainly includes plural The stackable window type semiconductor package structure 2 〇〇, 1360877 = road carrier board G and a plurality of external terminals 2Q as described above. The circuit board 〇 〇 top surface 11 and - In contrast to the bottom surface 12, the top surface n is formed with a plurality of terminals 13 which are located on opposite sides of the circuit board 1 请. See the 5® shown in the stackable window type The semiconductor package structure outline (4) the top surface u of the electric (four) board 1G is electrically connected to the plurality of contacts 13 of the circuit carrier 1G by the conductor posts 25 to achieve the stackable vertical window type semiconductor The package structure 2 is electrically interconnected with the circuit carrier ι. The stackable window-type semiconductor package structures are longitudinally stacked, and the lower stackable window-type semiconductor package structure (4) is The conductor post 250 is electrically connected to the conductive pillars 25G of the upper stackable window type semiconductor package structure ,, or may be electrically connected to the conductor pillars 25Q of the stackable " semiconductor package structure located below Or connected to the pads 13 of the circuit carrier 10. In particular, each of the stackable window-type semiconductor package structures may further comprise (4) a material 3G formed between the central sealant strip 241 and the side sealant bodies 242 to adhere another stackable underneath. A window type semiconductor package & 2 or the circuit carrier 10. The external terminals 20 are disposed on the bottom surface of the circuit carrier 1 . . As can be seen from the above, the stackable window type semiconductor package structure 200 replaces the solder balls by the conductor posts 25 () and the side sealants 242 that are penetrated during the package stacking process. The conductor pillars 25 of the stackable window type semiconductor package 2 located at the upper side are directly connected to the lower stackable fixed-package semiconductor package structure, conforming to the high-density terminal number and the stable package stack. It can replace the glow ball of the conventional window π-type semiconductor package structure for package stacking without the problem of ball drop and skew, and can shorten the length of electrical connection between the stackable 1360877 stacked window type semiconductor package structures 200, The phenomenon of delay between the stackable window type semiconductor package structures 200 due to the signal transmission path being too long is reduced. In the second embodiment of the present invention, please refer to FIG. 6 , and another stackable window type semiconductor package structure 300 mainly includes a substrate 3 1 and a plurality of electrical connecting elements 330 . A die body 340 and a plurality of conductor posts 350. The substrate 310 has an upper surface 311,
一下表面312' —槽孔313以及複數個周邊外接墊314。該 晶片320係設置於該基板31〇之該上表面311並具有複數個 鲜塾323 °該些銲墊323係形成於該晶片320之一主動面 321，且對準於該基板31〇之該槽孔313内，而例如銲線之 該些電性連接元件330係通過該槽孔313以使該晶片之 該二銲墊323電性連接至該基板31〇，並經由該基板31〇之 線路電性連接至該些周邊外接墊314。在本實施例中，該晶 片320係可具有顯露於該模封膠體34〇之一背面π〕，故該 模封膠體340係不完全密該晶片32〇，以增加散熱。該模封 膠體340係主要形成於該基板31〇之該上表面η〗，並具有 突出於該下表面312之-中央封膠條341以及複數個側封黎 體342 ’其中該中央封膠條341係覆蓋該槽孔⑴並密封該 些電性連接元件33G，該些侧封膠體342係覆蓋該些周邊外 接塾314。請參閱第7圖所示，在本實施例中，該些側封藤 體342係可為條狀並與該中央封膠條341大致平行配置，以 增進模流填充。該些側封膠體342之寬度係可小於該中央 膠條341之寬度。 'The lower surface 312' is a slot 313 and a plurality of peripheral ferrules 314. The wafer 320 is disposed on the upper surface 311 of the substrate 31 and has a plurality of slabs 323. The pads 323 are formed on one of the active surfaces 321 of the wafer 320, and are aligned with the substrate 31. In the slot 313, the electrical connecting component 330, such as a bonding wire, passes through the slot 313 to electrically connect the two pads 323 of the die to the substrate 31 and pass through the substrate 31. Electrically connected to the peripheral outer pads 314. In this embodiment, the wafer 320 may have a surface π] exposed on one of the molding pastes 34, so that the molding compound 340 is not completely dense with the wafer 32 to increase heat dissipation. The molding compound 340 is mainly formed on the upper surface η of the substrate 31, and has a central sealing strip 341 protruding from the lower surface 312 and a plurality of side sealing bodies 342 'where the central sealing strip The 341 series covers the slot (1) and seals the electrical connecting elements 33G, and the side sealing bodies 342 cover the peripheral external ports 314. Referring to Fig. 7, in the present embodiment, the side sealing cane 342 can be strip-shaped and disposed substantially parallel to the central sealing strip 341 to enhance mold flow filling. The width of the side sealant 342 may be less than the width of the central strip 341. '
13 1360877 請參閱第6圖所示，該可堆疊窗口型半導體封裝構造3〇〇 更具有複數個貫通孔370，其係對準於該些周邊外接墊314 並貫穿該於該模封膠體340在該基板31〇之該上表面311的 部位、該基板310以及該些側封膠體342。該些貫通孔37〇 之形成方式係可選用雷射鑽孔或是反應性離子蝕刻 (Reactive I〇n Etching，RIE)。請參閱第7圖所示，較佳地， 該些貫通孔370係可為交錯排列，以符合高密度端子之周邊 排列。請參閱第8圖所示，該些導體柱35〇係穿設於該些貫 通孔370内，更詳細地說，該些導體柱35〇係對準於該些周 邊外接墊3 14並貫穿該模封膠體34〇在該基板3ι〇之該上表 面311上的部位、該基板31〇以及該些側封膠體Μ]。因此， 該可堆疊窗π型半導體封裝構造能達到貫穿在該模封膜 體340之上下電性導通並取代習知窗口型半導體封㈣造之 銲球進行封f堆疊而不會有掉球與歪斜的問題，藉以控制在 一厚度較薄'較準確與更為水平的封裝堆疊。 該可堆疊窗口型半導體封裝構造3⑽能作為多個可堆疊 窗口型半導體封裝構造堆㈣之縱向堆疊之要求。請參閱= 8圖所示’該些可堆疊窗口型半導體封裝構造3⑽係疊設於 -電路載板40之頂面41，每一可堆疊窗口型半導體封襄構 造則係可另包含有黏著材料5G’其係、形成於該中央封膠條 ⑷與該些侧封膠體342之間，以黏接下方的另一可堆疊窗 口型半導體封裝構造3GG或該電路載板·其中，該電路 板40係具有複數個結合孔43,可為貫穿或半貫卜以供該 接導體柱350之插接。而該些結合孔43之位置係對準^ 1360877 一可堆疊窗口型封裝構造之該些貫通孔37〇。該些可堆疊窗 口型半導體封裝構造3 00係藉由該些導體柱3 5〇電性導通至 該電路載板40,以使該些可堆疊窗口型半導體封裝構造3〇〇 與該電路載板40能相互電性連接。在本實施例中，該些可 堆疊窗口型半導體封裝構造300中垂直對應之該些導體柱 3 50係可為一體連接。在封裝疊堆疊時可以先行定位與黏著 複數個可堆疊窗口型半導體封裝構造3〇〇，再以該些導體柱 350同時穿設於每-可堆疊f 口型半導體封裝構造3⑽之該 些貫通孔370至該電路載板4〇之該些結合孔43。該些導體 柱3 50係可突出於該電路載板4〇之該底自，以供對外接 少八丄尸/]通 . ^〜W U，业并對本， 作任何形式上的限制，本發明技術方案範圍當依所附申言 利範圍為準。任何熟悉本專業的技術人員可利用上述⑽ 、技術内容作出些許更動或修飾為等同變化的等效實次 術實St:離本發明技術方案的内容，依據本發_ ^實^^上實施例所作的任何簡單修改、等同變化與修 句仍屬於本發明技術方案的範圍内。 【圖式簡單說明】 第1圖:；種習知可堆疊窗口型半導體封裝構造之截面 不意圖。 第2圖：複數個習知可堆 堆疊之截面示意圖。㈣體封裝構造縱向 第3圖：依據本發明之第一具體實施例，—種可堆叠窗口13 1360877 Please refer to FIG. 6 , the stackable window type semiconductor package structure 3 further has a plurality of through holes 370 aligned with the peripheral outer pads 314 and extending through the mold sealing body 340 The substrate 31 has a portion of the upper surface 311, the substrate 310, and the side seals 342. The through holes 37 are formed by laser drilling or reactive ion etching (RIE). Referring to Figure 7, preferably, the through holes 370 are staggered to conform to the peripheral arrangement of the high density terminals. Referring to FIG. 8 , the conductor posts 35 are bored in the through holes 370 . In more detail, the conductor posts 35 are aligned with the peripheral outer pads 3 14 and penetrate the The portion of the molding compound 34 on the upper surface 311 of the substrate 3 ι, the substrate 31 〇 and the side seal Μ]. Therefore, the stackable window π-type semiconductor package structure can achieve electrical conduction through the solder-on-film body 340 and replace the solder ball formed by the conventional window-type semiconductor package (4) without failing to drop the ball and The problem of skewing is to control a thinner 'more accurate and more horizontal package stack. The stackable window type semiconductor package construction 3 (10) can serve as a vertical stacking requirement for a plurality of stackable window type semiconductor package construction stacks (4). Referring to FIG. 8 , the stackable window type semiconductor package structures 3 ( 10 ) are stacked on the top surface 41 of the circuit carrier 40 , and each stackable window type semiconductor package structure may further comprise an adhesive material. 5G' is formed between the central sealant strip (4) and the side sealant 342 to adhere to another stackable window type semiconductor package structure 3GG or the circuit carrier underneath, wherein the circuit board 40 There are a plurality of bonding holes 43, which may be through or half-through for the plugging of the connecting post 350. The positions of the bonding holes 43 are aligned with the through holes 37 of the stackable window type package structure. The stackable window type semiconductor package structure 300 is electrically conducted to the circuit carrier 40 by the conductor posts 35 to make the stackable window type semiconductor package structure 3 and the circuit carrier 40 can be electrically connected to each other. In this embodiment, the plurality of conductor pillars 50 in the stackable window type semiconductor package structure 300 may be integrally connected. In the package stacking, a plurality of stackable window-type semiconductor package structures can be positioned and adhered, and the conductive pillars 350 are simultaneously disposed in the through-holes of each of the stackable f-type semiconductor package structures 3 (10). 370 to the circuit board 4 of the plurality of bonding holes 43. The conductor posts 3 50 can protrude from the bottom of the circuit carrier 4 to be externally connected to the lower body of the corpse /] pass. ^~WU, and the present, any form of limitation, the present invention The scope of the technical solution is subject to the scope of the attached statement. Any person skilled in the art can use the above (10), the technical content to make some changes or modify the equivalent real-time practice St: the content of the technical solution of the present invention, according to the embodiment of the present invention Any simple modifications, equivalent changes, and repairs made are still within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional stackable window type semiconductor package structure. Figure 2: Schematic diagram of a plurality of conventional stackable stacks. (4) Body package structure longitudinal direction FIG. 3: According to the first embodiment of the present invention, a stackable window
15 S υουδ/y15 S υουδ/y
半導體封裝構造之截面示意 第4圖：依據本發明之第-具體實施例， 半導體封裝構造之基板下表面 第5 ® :依據本發明之第-具體實施例 口型半導體封裝構造縱向堆導 載板之截面示意圖。 :依據本發明之第二具體實施例 口型半導體封裝構造之截面^ :依據本發明之第二具體實施例 半導體封裝構造之基板下表a 第8圖：依據本發明之第二具體實施例 第6圖 第7圖 【主要元件符號說明】FIG. 4 is a cross-sectional view of a semiconductor package structure. According to a first embodiment of the present invention, a lower surface of a substrate of a semiconductor package structure is 5 ′′: a longitudinal stack guide carrier according to a first embodiment of the present invention. A schematic cross section. A cross section of a die-type semiconductor package structure according to a second embodiment of the present invention: a substrate of a semiconductor package structure according to a second embodiment of the present invention, a table below: FIG. 8: a second embodiment according to the present invention 6Fig. 7 [Description of main component symbols]
型半導體封裝構造縱向堆疊j 板之截面示意圖。 10 電路載板 11 頂面 13 接墊 20 外接端子 40 電路載板 41 頂面 43 結合孔 50 黏著材料 100 窗口型半導體封裝構造 110 基板 111 上表面 113 槽孔 120 晶片 130 電性連接元件140 模封膠體 200 可堆疊窗 口型半導體封裝構造 210 基板 211 上表面 圖。 該可堆疊窗α型 I示意圖。 ，複數個可堆疊窗 ΐ並接合至一電路 ，另一種可堆疊窗 ^意圖。 ，該可堆疊窗口型 δ示意圖。 ，多個可堆疊窗口 i接合至一電路载 12 底面 30 黏著材料 42 底面 112下表面 123銲墊 150銲球 212下表面 1360877 213 槽 孔 214 周 邊外接墊 220 晶 片 221 主 動面 222 背 面 223 銲 墊 230 電 性連接元 件 240 模 封 膠 體 241 中 央封膠條 242 側 封 膠 體 250 導 體 柱 260 黏 晶層 300 可 堆 疊 窗σ 型半導: 瞪封裝構造 310 基板 311 上 表面 312 下 表 面 313 槽 孔 314 周 邊外接墊 320 晶 片 321 主 動面 322 背 面 323 銲 墊 330 電 性連接元 件 340 模 封 膠 體 341 中 央封膠條 342 側 封 膠 體 350 導 體 柱 370 貝 通孔A schematic cross-sectional view of a longitudinally stacked j-plate of a semiconductor package structure. 10 circuit carrier 11 top surface 13 pad 20 external terminal 40 circuit carrier 41 top surface 43 bonding hole 50 adhesive material 100 window type semiconductor package structure 110 substrate 111 upper surface 113 slot 120 wafer 130 electrical connection component 140 Colloid 200 Stackable Window Type Semiconductor Package Construction 210 Substrate 211 Upper Surface View. The stackable window is a type I schematic. , a plurality of stackable windows ΐ and joined to a circuit, another stackable window ^ intent. , the stackable window type δ schematic. , a plurality of stackable windows i are bonded to a circuit carrier 12 bottom surface 30 adhesive material 42 bottom surface 112 lower surface 123 solder pad 150 solder ball 212 lower surface 1360877 213 slot 214 peripheral external pad 220 wafer 221 active surface 222 back 223 solder pad 230 Electrical connection element 240 mold encapsulant 241 central seal strip 242 side sealant 250 conductor post 260 adhesive layer 300 stackable window σ-type semi-conductor: 瞪 package structure 310 substrate 311 upper surface 312 lower surface 313 slot 314 peripheral external Pad 320 Wafer 321 Active Surface 322 Back 323 Pad 330 Electrical Connection Element 340 Mold Seal 341 Central Sealing Strip 342 Side Sealing Colloid 350 Conductor Post 370 Beacon
1717