TW201007909A - Ball grid array package without solder balls - Google Patents

Ball grid array package without solder balls Download PDF

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Publication number
TW201007909A
TW201007909A TW97130894A TW97130894A TW201007909A TW 201007909 A TW201007909 A TW 201007909A TW 97130894 A TW97130894 A TW 97130894A TW 97130894 A TW97130894 A TW 97130894A TW 201007909 A TW201007909 A TW 201007909A
Authority
TW
Taiwan
Prior art keywords
ball
substrate
grid array
array package
ball grid
Prior art date
Application number
TW97130894A
Other languages
Chinese (zh)
Inventor
Ming-Yao Chen
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW97130894A priority Critical patent/TW201007909A/en
Publication of TW201007909A publication Critical patent/TW201007909A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

Disclosed is a ball grid array (BGA) package, primarily comprising a substrate, at least a chip on the substrate, and a molding compound. The substrate has a plurality of socket holes, a plurality of traces and a plurality of shell electrodes where the shell electrodes are aligned with and connected to the socket holes, further protruded from a bottom surface of the substrate. The chip is electrically connected to the traces. The molding compound is formed on the substrate and fills in the internal spaces of the shell electrodes through the socket holes to form a plurality of insulating bumps connected as a whole. Accordingly, the shell electrodes filled with the molding compound inside are configured as integrally ball terminals of the package to replace solder balls to eliminate the conventional problems of ball crack or ball dropping. And also, it can save the step of disposing solder balls in conventional BGA packaging processes.

Description

% %201007909 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導趙裝置，特別 種免用銲球之球柵陣列封裝構造。 ； 【先前技術】 球柵陣列（遍，Ball Grid Array)封裝為—種 進之半導趙封裝技術’使用—基板以供設置晶片並在 晶片被封膠之後於基板之下表面植設複數個矩陣型離 排列之銲球，例如錫鉛材質之銲球係以迴焊方式固著= 基板之球塾，再經表面接合可使一球柵陣列封裝構：： 接電性連接至外部印刷電路板或其他電子產品上。 如第1圖所示，一種習知球栅陣列封裝構造^㈧， 係為窗口型球柵陣列封裝類型，以一具有内部電性連接 通道117之基板ι10做為晶片載體與内部電性傳遞媒 介。該内部電性連接通道117係為一長槽孔並連通該基 板110之上表面lU與下表面112。利用一黏晶層14〇 之黏貼，使一晶片120之一主動面121貼設在該基板 110之該上表面1U。該晶片120之一背面122係相對 遠離該基板110。該晶片120係具有複數個在該主動面 之銲墊123，其係對準顯露於該内部電性連接通道117 _。並以複數個銲線16〇穿過該内部電性連接通道 以電性連接該晶片12〇之該些銲墊123至該基板11〇。 一封膠體130同時形成在該基板110之該上表面^丨丨與 該内部電性連接通道117，以密封該晶片120與該些銲 201007909 線16〇,複數個銲球170係設置於該基板u〇之該下表 面112的球墊，以作為對外焊接端點。以下的製造流程 說明該些銲球170係設置在該封膠體i 3〇形成之後，該 基板110之球墊易受到該封膠體13〇的溢膠污染，導致 該些銲球170無法確實焊接於該基板11〇而形成假焊現 象’易有銲球斷裂或掉球的問題。 習知窗口型球栅陣列封裝構造1〇〇之製造流程如第 ❿ 2A至2D圖所示。首先，如第2A圖所示，提供該基 板110’係具有線路結構（圖未繪出）。該内部電性連接 通道117係貫穿該基板no並約位於該基板11〇之一 中央位置。預先形成一膠帶或是可塗佈黏膠之黏晶層 140在該基板11〇之該上表面m，以供後續黏晶使 用。如第2B圖所示，在黏晶步驟中，利用該黏晶層 140黏貼該晶片120之該主動面12ι於該基板11()之 該上表面111’如第2C圖所示’該些銲線160係形成 Φ 在打線步驟中’通過該内部電性連接通道117以將該 晶片120之該些銲墊123電性連接至該基板11〇。如 第2D圖所示’該封膠體130係形成在模封步驟中，以 密封該晶片120以及該些銲線16〇，在模封步驟中尚 未設置銲球’以使該基板110之該下表面112可平貼 於一下模板。最後，如第1圖所示，再將該些銲球17〇 設置於該基板110之該下表面112，以構成球柵陣列 封裝構造（BGA package)。習知銲球170須經過高溫回 焊步驟後，使銲球170再熔化成球狀並焊接於該基板 201007909 110之球墊。一旦該封膠 * ^ t, 130在該基板1 10之該下 17。易二產二溢膠便可能污染到球塾，使得該些銲球 =二裂或脫落，影響封裝之可靠性。 【發明内容】 有赛於此，本發明之主要 趙请▲ 要目的係在於提供一種免用 銲球之球栅陣列封裝構造， ..施此 無項在封膠之後另行設置銲 Φ Φ 陵’"與外界褒置達成電性連接，並能解決習知球栅 陣列封裝構造的銲球斷裂或掉落之問題。 本發明的目的及解決Α枯t A 鮮決其技術問題是採用以下技術方 案來實現的。依據本發明 _ 揭不之一種免用銲球之球柵 陣列封裝構造，主要包会一 ^ 3 基板、至少一晶片以及一封 膠體。該基板係具有一卜志& ^ 上表面、一下表面、複數個端點 通孔複數個跡線以及複數個連接該些跡線之殼型電 極办其中該些殼型電極係對準並連通至該些端點通孔， 更犬出於該下表面°該晶片係設置於該基板之該上表 面該曰曰片之一主動面係具有複數個銲墊，該些銲墊係 電性連接至該些跡線。該封膠體係形成於該基板之該上 表面並通過該些端點通孔填入至該些殼型電極之内部 空間。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述球柵陣列封裝構造中，該些殼型電極與該些 跡線係可一體連接於一線路層。 在前述球柵陣列封裝構造中，該線路層係可形成於 該線路層係可形 該些殼型電極係 該封膠體在該些 201007909 該基板之該下表面。 在刖述球拇陣歹ij 1 卞封骏構造中 該基板之該上表面。 在前述球栅陣列封裝構造中 平面覆蓋該些端點通孔之一端。 在前述球柵陣列封裝構造+ — 電極之内部空間# ’係了形成為複數個一體互連之絕 塊0 在前述球栅陣列封骏構造中，可另包含有一圖 黏晶>f係黏著該晶片與該基板該圖案化黏晶層 密閉該些端m福了丨 ~ .，通孔’以使該些絕緣凸塊一體互連。 在則述球拇陣列封裝構造中，該些殼型電極係 有圓弧形截面。 在前述球柵陣列封裝構造中，該些殼型電極係 有方形條截面。 在則述球栅陣列封裝構造中，可另包含一金屬 層’包此覆該些殼型電極之外露表面。 在前述球栅陣列封裝構造中，該封膠體係可完 封該晶片。 在前述球栅陣列封裝構造中，該基板係可具有 部電性連接通道，其係貫穿該上表面至該下表面， 晶片之該主動面貼附於該基板之該上表面，以使該 不覆蓋該些銲墊。 在前述球柵陣列封裝構造中，該些跡線係可延 成於 可非 殼型 緣凸 案化 係不 可具 可具 接合 全密 一内 當該 基板 伸至 201007909 該内部電性連接通道内 艰巧並直接接合至該些銲墊〇 在前述球柵陳兩丨44· Η*, 封裝構造中，可另包含複數個銲 線，係通過該内部雷姓 電14連接通道以電性連接該些銲墊與 該些跡線。 在前述球拇陣兩丨i、Α 1 t 1 J封裝構造中’該封膠體係可更填入 該内部電性連接通道。 在前述球柵陣列封裝構造中，該内部電性連接通道 係可為一中央狹長槽孔。 在前述球柵陣列封裝構造中該晶片係可具有一相 對於該主動面之—背面，該背面係貼附於該基板之該上 面該长栅陣列封震構造係另包含複數個銲線’係電 性連接該些銲墊與該些跡線。 ’J述泉栅陣列封裝構造中，該些殼型電極係可為 金屬墊並經引腳結合（lead bQnd)方式變形形成。 由以上技術方案可以看出，本發明之免用銲球之球 一 p列封裝構造，具有以下優點與功效： J用封膠體填入至殼型電極之内部空間，可作為一 體化外接球端，以取代銲球作為對外接合之輸入/ 輸出端，不會增力封裝步驟也不需要附加_球，製 :中能省略習知封膠之後的銲球設置步驟，在結構 一 能消除習知銲球斷裂或掉落之問題。 藉由封膠艘填入殼型電極之内冑空間而形成一趙互 一連之絕緣凸塊’以防止殼型電極變形或位移。 使用低成本具有單面線路層之基板同時提供殼型電 可省略封裝元件與製 理，更省略習知銲球 201007909 極與跡線在同一線路層， 驟’並提高訊號高速化處 作成本。 四、以金屬#合層包覆殼型電極之外露表面可做 強電極，增加殼型電極之結構強度。 【實施方式】 ί 以下將配〇所附圖示詳細說明本發明之實施例 ❹冑/主意的疋該些圖示均為簡化之示意圖，僅以示 法來說明本發明之基本架構或實施方法故僅顯示 案有關之兀件，且所顯示之元件並非以實際實施 目形狀、尺寸比例繪製，某些尺寸比例與其他相 寸比例已經被修飾放大或是簡化，以提供更清楚 述’實際實施之數目、形狀及尺寸比例為一種選置 設計’且詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種免用銲球 |❹栅陣列封裝構造舉例說明於第3圖之截面示意圖。 栅陣列封裝構造200主要包含一基板21〇、至少一 220以及一封膠體23〇。 該基板210係為一晶片栽體，可用於承載與電 接該晶片220。該基板210係具有一上表面211與 表面212’該上表面211作為晶片設置面，而該下 212則為外接表面。該基板21〇係更具有複數個端 孔213、複數個跡線214以及複數個連接該些跡錦 之殼型電極215，其中該些殼型電極215係對準並 程步 之製 為補 意方 與本 之數 關尺 的描 性之 之球 該球 晶片 性轉 一下 表面 點通 214 連通 10 201007909 至該些端點通孔213，更突出於該下表面212〇該些跡 線214係為該基板21〇内部線路層之一部份而非外加的 元件’通常係為銅線路。在基板製作中，該些跡線214 係由一銅箔經曝光（exposing)、顯影（devel〇ping)、蝕刻 (etching)等製程而圖案化（patterning)以形成。較佳地， 該些殼型電極215與該些跡線214係可一體連接於一線 路層216，使上述兩者在同一層線路結構以簡化線路 ❹ 層數，達到降低基板成本與免用銲球之功效。在本實施 例中，該線路層2 16係可形成於該基板21〇之該下表面 212»該基板210可選用一種具有單面線路層之電路基 板，例如印刷電路板、陶瓷線路板或電路薄膜，該基板 210利用該線路層216同時形成該些殼型電極215與該 些跡線214可省去兩面線路佈局與鍍通孔之複雜度與 製程困擾’並可提高訊號之高速化處理。而該些殼型電 極2 1 5係可取代習知之銲球，作為與外界裝置電性連接 • 之輸入/輸出（inPut/outPut，1/〇)端，並且與該封膠體230 一體連接不會脫落（容後詳述）。 此外’該基板210係可具有一内部電性連接通道 217’其係貫穿該基板210之該上表面21 1A主琢下录面 2 12 ’該晶片220之該主動面221係貼附於該基板21〇 之該上表面2U’該些鲜塾223係對準顯露於/該内部電 性連接通道217,以使該基板210不覆蓋該些鲜塾223。 該些跡線2 1 4係可延伸至該内部電性遠挺、s a 疋钱通道217内並 直接接合至該些銲墊223。並可以該封膠體23〇填入該 11 201007909 内部電性連接通道217。較佳地，如第3圖所示，該基 板210可另包含一防焊層218，其係覆蓋該線路層216 但顯露該些殼型電極215，以提供表面絕緣保護，避免 外界水氣或塵埃污染。該防焊層2 1 8係為一種低成本絕 緣性油墨，可調整其稠度以控制形成厚度《由於該基板 210可以僅具有單面線路層216，以降低基板成本與省 略鲜球。 如第3圖所示，該晶片220係設置於該基板210之 該上表面211，該晶片220係包含有一主動面221與相 對之一背面222。該主動面221係具有複數個銲墊223, 例如銘墊’該些銲墊223係電性連接至該些跡線214。 其中’電性連接方法可以是引腳接合（lead bond)也可以 是打線接合（wire bonding)。 該封膠體230係形成於該基板21〇之該上表面211 並通過該些端點通孔213填入至該些殼型電極215之内% %201007909 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor semiconductor device, and in particular to a solder ball ball grid array package structure. [Prior Art] Ball grid array (Ball Grid Array) is packaged into a semi-conductive semiconductor package technology. The substrate is used to set the wafer and after the wafer is encapsulated, a plurality of substrates are implanted on the lower surface of the substrate. Matrix-arranged solder balls, such as tin-lead solder balls, are soldered to the ballast of the substrate, and then bonded to the surface to form a ball grid array package:: Electrically connected to the external printed circuit Board or other electronic products. As shown in Fig. 1, a conventional ball grid array package structure (8) is a window type ball grid array package type, and a substrate 10 having an internal electrical connection channel 117 is used as a wafer carrier and an internal electrical transfer medium. The internal electrical connection channel 117 is a long slot and communicates with the upper surface 11U and the lower surface 112 of the substrate 110. An active surface 121 of a wafer 120 is attached to the upper surface 1U of the substrate 110 by adhesion of a bonding layer 14A. One of the back faces 122 of the wafer 120 is relatively far from the substrate 110. The wafer 120 has a plurality of pads 123 on the active surface, the alignment of which is exposed to the internal electrical connection channel 117_. And the plurality of bonding wires 16 〇 pass through the internal electrical connection channel to electrically connect the pads 123 of the wafer 12 to the substrate 11 〇. A colloid 130 is formed on the upper surface of the substrate 110 and the internal electrical connection channel 117 to seal the wafer 120 and the solder lines 201007909, and a plurality of solder balls 170 are disposed on the substrate. The ball pad of the lower surface 112 is used as the outer soldering end point. The following manufacturing process shows that the solder balls 170 are disposed after the encapsulant i 3 is formed, and the ball pads of the substrate 110 are easily contaminated by the gel of the encapsulant 13 , so that the solder balls 170 cannot be soldered. The substrate 11 is bent to form a false soldering phenomenon, which is problematic in that the solder ball is broken or dropped. The manufacturing process of the conventional window type ball grid array package structure is as shown in Figs. 2A to 2D. First, as shown in Fig. 2A, the substrate 110' is provided to have a wiring structure (not shown). The internal electrical connection channel 117 extends through the substrate no and is located approximately at a central location of the substrate 11'. A tape or a layer of adhesive-coated adhesive layer 140 is preliminarily formed on the upper surface m of the substrate 11 for subsequent adhesion. As shown in FIG. 2B, in the bonding step, the active surface 12 of the wafer 120 is adhered to the upper surface 111' of the substrate 11 by the bonding layer 140, as shown in FIG. 2C. The line 160 is formed to be Φ. In the wire bonding step, the pads 123 of the wafer 120 are electrically connected to the substrate 11 through the internal electrical connection channel 117. As shown in FIG. 2D, the encapsulant 130 is formed in a molding step to seal the wafer 120 and the bonding wires 16 , and no solder balls are disposed in the molding step to make the substrate 110 Surface 112 can be tiled to the next template. Finally, as shown in Fig. 1, the solder balls 17 are placed on the lower surface 112 of the substrate 110 to form a ball grid array package structure (BGA package). The solder ball 170 is subjected to a high temperature reflow step to re-melt the solder ball 170 into a spherical shape and soldered to the ball pad of the substrate 201007909 110. Once the sealant * ^ t, 130 is at the bottom of the substrate 1 10 . Easily produced two spills of glue may contaminate the ball, making the solder balls = split or fall off, affecting the reliability of the package. [Summary of the Invention] In this case, the main purpose of the present invention is to provide a ball grid array package structure that is free of solder balls, and that is not required to be separately set after the sealing of the glue Φ LING "An electrical connection with the external device, and can solve the problem of the solder ball breaking or falling in the conventional ball grid array package structure. The object of the present invention and the solution to the problem are the following technical solutions. According to the present invention, a solder ball ball grid array package structure is disclosed, which mainly comprises a substrate, at least one wafer, and a gel. The substrate has a top surface, a lower surface, a plurality of end vias, a plurality of traces, and a plurality of shell electrodes connecting the traces, wherein the shell electrodes are aligned and connected To the end vias, the dog is disposed on the lower surface of the substrate. The active surface of the wafer has a plurality of pads, and the pads are electrically connected. To these traces. The encapsulation system is formed on the upper surface of the substrate and filled into the inner spaces of the shell-type electrodes through the end vias. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the ball grid array package configuration described above, the shell electrodes and the traces are integrally connected to a wiring layer. In the ball grid array package structure described above, the wiring layer can be formed on the wiring layer to form the shell-type electrode system. The encapsulant is on the lower surface of the substrate of the 201007909. This upper surface of the substrate is described in the structure of the ball 拇 1 1 卞 骏 。. In the ball grid array package configuration described above, one of the end vias is planarly covered. In the foregoing ball grid array package structure + - the internal space of the electrode is formed as a plurality of integral interconnections. In the ball grid array sealing structure, the image may additionally include a picture of a sticky crystal > The patterned and die-bonded layer of the wafer and the substrate are sealed to form the vias to interconnect the insulating bumps. In the spherical thumb array package structure, the shell-shaped electrodes have a circular arc-shaped cross section. In the ball grid array package construction described above, the shell electrodes have a square strip cross section. In the ball grid array package construction described above, a metal layer may be further included to cover the exposed surfaces of the shell electrodes. In the ball grid array package construction described above, the encapsulation system can seal the wafer. In the foregoing ball grid array package structure, the substrate may have a partial electrical connection channel extending through the upper surface to the lower surface, and the active surface of the wafer is attached to the upper surface of the substrate to enable the Cover the pads. In the ball grid array package structure described above, the traces can be extended to a non-shell type edge-forming system, and the substrate can be extended to 201007909. In the package structure, the plurality of bonding wires may be further connected to the soldering pads, and the plurality of bonding wires may be further connected through the internal lightning circuit 14 connecting channels to electrically connect the wires. Solder pads and the traces. In the above-mentioned ball-and-buckle array, the encapsulation system can be further filled with the internal electrical connection channel. In the ball grid array package construction described above, the internal electrical connection channel can be a central elongated slot. In the ball grid array package structure, the wafer system may have a back surface opposite to the active surface, and the back surface is attached to the upper surface of the substrate. The long gate array sealing structure further includes a plurality of bonding wires. The pads and the traces are electrically connected. In the case of the J-spring array package structure, the shell-type electrode systems may be metal pads and deformed by a lead bQnd method. It can be seen from the above technical solution that the ball-free package structure of the solder ball of the present invention has the following advantages and effects: J is filled with the sealing body into the inner space of the shell electrode, and can be used as an integrated external ball end. In place of the solder ball as the input/output terminal for external bonding, there is no need to increase the force of the packaging step and no additional ball is required. In the system: the solder ball setting step after the conventional sealing can be omitted, and the structure can be eliminated. The problem of the solder ball breaking or falling. An insulating bump is formed by filling the inner space of the shell electrode by the sealant to prevent deformation or displacement of the shell electrode. Using a low-cost substrate with a single-sided wiring layer while providing a shell-type power can omit the package components and the process, and omitting the conventional solder ball 201007909. The pole and the trace are on the same circuit layer, and the cost of the signal is increased. 4. The exposed surface of the shell-shaped electrode coated with metal # can be used as a strong electrode to increase the structural strength of the shell electrode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a simplified illustration of the embodiments of the present invention, which are merely illustrative of the basic architecture or implementation of the present invention. Therefore, only the relevant parts of the case are displayed, and the components displayed are not drawn in the actual implementation shape and size ratio. Some size ratios and other ratios have been modified or simplified to provide a clearer description of the actual implementation. The number, shape and size ratios are an alternative design' and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a spare solder ball | ❹ grid array package structure is illustrated in a cross-sectional view of FIG. The gate array package structure 200 mainly includes a substrate 21 〇, at least one 220, and a colloid 23 〇. The substrate 210 is a wafer carrier that can be used to carry and electrically connect the wafer 220. The substrate 210 has an upper surface 211 and a surface 212' which serves as a wafer mounting surface, and the lower portion 212 is an external surface. The substrate 21 further includes a plurality of end holes 213, a plurality of traces 214, and a plurality of shell electrodes 215 connected to the traces, wherein the shell electrodes 215 are aligned and stepped to complement each other. The ball of the characterization of the ball is turned to the surface point 214 to connect 10 201007909 to the end holes 213, more prominently on the lower surface 212, the traces 214 are the substrate One of the 21 〇 internal circuit layers, rather than the additional components, is usually a copper line. In the fabrication of the substrate, the traces 214 are patterned by a copper foil by exposing, develping, etching, or the like. Preferably, the shell electrodes 215 and the traces 214 are integrally connected to a circuit layer 216, so that the two layers are in the same layer structure to simplify the number of layers, thereby reducing substrate cost and free soldering. The effect of the ball. In this embodiment, the circuit layer 2 16 may be formed on the lower surface 212 of the substrate 21 . The substrate 210 may be a circuit substrate having a single-sided circuit layer, such as a printed circuit board, a ceramic circuit board, or a circuit. The thin film, the substrate 210 can form the shell electrodes 215 by using the circuit layer 216, and the traces 214 can eliminate the complexity of the two-sided circuit layout and the plated through holes and the process troubles, and can improve the speed of the signal. The shell electrode 2 15 can replace the conventional solder ball as an input/output (inPut/outPut, 1/〇) end electrically connected to the external device, and is not integrated with the sealant 230. Shedding (detailed later). In addition, the substrate 210 can have an internal electrical connection channel 217' extending through the upper surface 21 of the substrate 210. The main lower surface of the substrate 210 is attached to the substrate. The upper surface 2U' of the upper surface 2U' is aligned with the internal electrical connection channel 217 so that the substrate 210 does not cover the fresh slabs 223. The traces 2 1 4 can extend into the internal electrical extension, s a money channel 217 and are directly bonded to the pads 223. The sealant 23 can be filled into the 11 201007909 internal electrical connection channel 217. Preferably, as shown in FIG. 3, the substrate 210 may further include a solder resist layer 218 covering the circuit layer 216 but exposing the shell electrodes 215 to provide surface insulation protection to avoid external moisture or Dust pollution. The solder resist layer 2 18 is a low-cost insulating ink that can be adjusted in thickness to control the thickness of the substrate. Since the substrate 210 can have only a single-sided wiring layer 216, the substrate cost can be reduced and the fresh balls can be saved. As shown in FIG. 3, the wafer 220 is disposed on the upper surface 211 of the substrate 210. The wafer 220 includes an active surface 221 and a corresponding back surface 222. The active surface 221 has a plurality of pads 223, such as pads 223 electrically connected to the traces 214. The electrical connection method may be a lead bond or a wire bond. The encapsulant 230 is formed on the upper surface 211 of the substrate 21 and is filled into the shell electrodes 215 through the end vias 213.

極215 2 00可另包含有一圖案化黏晶 丨，可強化該殼型電極21 215產生變形或位移。 該球柵陣列封裝構造2〇 12 201007909The pole 215 2 00 may further comprise a patterned doped germanium which reinforces deformation or displacement of the shell electrode 21 215. The ball grid array package structure 2〇 12 201007909

層240，其係黏著該晶H 片220與該基板210，該圖案化 黏晶層 240係不密閉却& 端點通孔213(如第5圖所 不）’以使該些絕緣△掩。 鬼231與該封膠艎230 —體互連。 較佳地，該球栅陣列封裝構造2〇〇可另包含一金屬 接σ層250其係包覆該些殼型電極之外露表面， 較佳地，該金屬接合層25〇之厚度係可大於該殼型電極 2之厚度以作為補強電極，能增加該些殼型電極215 之結構強度。 〇 依據本發明之第一具體實施例，該球柵陣列封裝構 造200之製造方法，舉例說明於第4A至4D圖之在製 程中元件的截面示意圖以及第5圖之基板上表面之俯 視圖。 如第4A圖所示，首先提供一基板21〇，該基板21〇 係作為該球栅陣列封裝構造2〇〇之晶片載體，可預先 裁切成所需尺寸，或是複數個矩陣排列並一艎形成於一 ❿ 基板條，在封裝之後再切割成個別之半導體封裝構造。 該基板210之該下表面212係設有該線路層216，並以 該防焊層218覆蓋該線路層216，但不覆蓋該些端點通 孔2 1 3之相對位置，以供後續在該些位置形成該些殼型 電極215。具體而言，該些端點通孔213係可以雷射、 機械鑽孔或是反應性離子蝕刻等等方法形成，並且不切 斷該線路層216。其中，該些端點通孔213係對應於該 球柵陣列封裝構造200之腳位。 接著，如第4B圖所示，以一沖壓具1〇對準該些端 13 201007909 點通孔213，向下沖壓該線路屠 叫層216，使其成為複數個 突出於該下表面212之殼型電 土电極215。具體而言，該些 殼型電極215係可非平面薄装# , T J开卞甸覆蓋該些端點通孔213之一 端，以避免該封膠體230的淄ψ 〜A出。在本實施例中，該些 ❹ 般型電極2丨5係可具有方形條截面’以提供—平坦之^卜 接表面。但不受局限地’該些殼型電極215之截面亦可 為各種形狀4V形條n形條或其他條狀。該些殼 型電極215的形成不需要繁複步驟與附加額外元件便 能形成，可作為一體化外接球端，以取代銲球。 再如第4B圖所示，該基板21〇之該上表面2ιι可預 先設置該圖案化黏晶層240以供後續黏貼晶片之用。該 圖案化黏晶層240係可利用網印或針筒點膠、貼附等方 法形成在該基板210之該上表面211。該圖案化黏晶層 240係可選自於B階膠體、液態膠或聚亞醯胺（ρι)膠帶 之其中之一。如第5圖所示，較佳地，該圖案化黏晶層 Φ 240係不覆蓋該些端點通孔213並在晶片覆蓋區内形成 有模流通孔’以供後續該封膠體230之填入。 之後’如第4C圖所示，設置該晶片22〇於該基板21〇 之上。並藉由該圖案化黏晶層240黏著該晶片220於該基 板210之該上表面211。在本實施例中，該晶片220之該主 動面221係朝下，該些銲墊223係位於該晶片220之中央區 域，該内部電性連接通道217亦形成在該基板210之中央區 域。該些銲墊223可對準顯露在該内部電性連接通道217 内。具體而言，如第3及5圖所示，該内部電性連接通 14 201007909 道217係可為一中央狹長槽孔。而該些跡線2i4可延伸 至該内部電性連接通道217内，可直接接合至該些銲墊 223。因此，該些跡線214之一區段係可延伸並懸浮在該内 部電性連接通道217對應該些銲墊223之位置，利用引腳接 σ技術使一沖壓工具將位於該内部電性連接通道217内之懸 空跡線214熱壓合接觸到該些銲墊223，以達到電性連接該 晶片220與該基板210。 φ 該些端點通孔213係可概呈圓形孔，其位置對應於 該球柵陣列封裝構造之腳位t但該些端點通孔2 1 3亦可 為矩形孔或其他形狀。在本實施例中，該些殼型電極 .215係可為金屬塾並經引腳結合（ieaij b〇n(j)方式變形形 成°該些金屬墊在未受沖壓之前係平面覆蓋整個對應之 端點通孔2 1 3之對應端口。 最後，如第3圖所示，利用模封（或稱轉移成形）方法 形成該封膠體230於該基板210之該上表面211，並填入該 # 内部電性連接通道217以及該些端點通孔213，並可完 全密封該晶片220 ’以使該些内部元件與外界氣密隔離 而免受外界衝擊或污染。 因此，該些殼型電極215可作為與外界裝置電性連 接之輸入/輸出（1/0，input/output)端，並藉由該封膠體 230填入該些殼型電極215之内部空間而形成一體互連 之該些絕緣凸塊231’可防止該些殼型電極215變形或 位移。此外，以該金屬接合層 250包覆該些殼型電極 215之外露表面’可做為補強電極，增加該些殼型電極 15 201007909 215之結構強度。 依據本發明之第二具體實施例，另 一灌免用銲球之 6圖之截面示意圖。該球柵 一基板210、至少一晶片220 球栅陣列封裝構造說明於第 陣列封裝構造300主要包含 以及-封㈣230。纟要元件係肖第一具體實施例相同 並以相同圖號表示之，故可以理解亦具有上述功效，不 再贅述。 e 在本實施例中，該球柵陣列封裝構造3〇〇可另包含 複數個銲線360，該些銲線360係通過該内部電性連接 通道217以電性連接該些銲塾223與該些跡線214。該 些銲線360之材質可為金線、銘線或銅線，其中以金 線較為常用。 在本實施例中係以打線電性連接方式取代以跡線2 i 4 沖壓直接接合至該些銲墊223 ^但不受限地’該晶片22〇除 了可以打線電性連接之外，亦可以覆晶接合（fHp chip • b〇nding)或是其它已知電性連接方式完成該些晶片 220與該 基板210之電性互連。 依據本發明之第三具體實施例，另一種免用銲球之 球栅陣列封裝構造說明於第7圖之截面示意圖。該球栅 陣列封裝構造400主要包含一基板21〇、至少一晶片220 以及一封膠體230。主要元件係與第一具體實施例相同 並以相同圖號表示之，並不再贅述。 較佳地，該線路層216係形成於該基板210之該上 表面211，可避免該些殼型電極215由該基板21〇產生 16 201007909 剝離。在本實施例中’該晶片220之該背面222係可貼 附於該基板210之該上表面211，再以複數個銲線460 電性連接該些銲墊22 3與該些跡線214。該球柵陣列封 裝構造400可應用在多晶片堆疊之封裝，即在該基板21〇 之該上表面211疊設複數個晶片22〇，再電性連接至該基板 210 ° 此外，在本實施例中，該些殼型電極215係具有圓 ❹ 弧形截面並且其内部空間係被該封膠體230填滿成絕緣 凸塊23 1 ’以現有封裝材料的延伸變化以能省略習知的 銲球設置，可作為一體化外接球端，不會增加封裝步驟 也不需要附加銲球，製程中能省略習知封膠之後的銲球 設置步驟，在結構中能消除習知銲球斷裂或掉落之 題。 以上所述，僅是本發明的較佳實施例而已並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 • 所附申請專利範園為準。任何熟悉本專業的技術人員可 利用上述揭*的技術内容作出些冑更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内.。 【圖式簡單說明】 第1圖：為-種習知球柵陣列封裝構造的截面示意圖。 第2A至2D圖：為習知球柵陣列封裝構造在製程 17 201007909 件的截面示意圖。 第3圖·依據本發明第—具體實施例的一種免用銲球之 球栅陣列封敕構造之截面示意圖。 第4A及4D圖.為依據本發明第—具體實施例的該球 撕陣列封裝構造在製程中元件的截面示意圖。 第5 ® .為依據本發明帛—具體實施例的該球栅陣列封 裝構造之基板上表面示意圖。 φ 帛6圖’·為依據本發明帛二具體實施例的-種免用薛球 之球桃陣列封裝構造之截面示意圖。 第7圖：為依據本發明第三具體實施例的一種免用銲球 之球概陣列封裝構造之截面示意圖。 【主要元件符號說明】 10 沖壓具 100球柵陣列封裝構造 110基板 111上表面 117内部電性連接通道 120晶片 121主動 123銲墊 130封膠體 14〇黏晶 170銲球 200球栅陣列封裝構造 210基板 211上表 213端點通孔 2 14跡線 216線路層 面 層 112下表面 122背面 160銲線 面 212下表面 215殼型電極 217内部電性連接通道 201007909 218防焊層 222背面 220晶片 221主動面 223銲墊 230封膠體 231絕緣凸塊 240圖案化黏晶層250金屬接合層 300球柵陣列封裝構造 3 6 0銲線 400球柵陣列封裝構造 ❿ 460銲線 19The layer 240 is adhered to the crystal H piece 220 and the substrate 210. The patterned doped layer 240 is not sealed but the end hole 213 (as shown in FIG. 5) is used to mask the insulation. . The ghost 231 is physically interconnected with the sealant 230. Preferably, the ball grid array package structure 2 further includes a metal smear layer 250 covering the exposed surfaces of the shell electrodes. Preferably, the thickness of the metal bonding layer 25 可 is greater than The thickness of the shell electrode 2 serves as a reinforcing electrode to increase the structural strength of the shell electrode 215.制造 In accordance with a first embodiment of the present invention, the method of fabricating the ball grid array package structure 200 illustrates a cross-sectional view of the components in the process of FIGS. 4A through 4D and a top view of the upper surface of the substrate of FIG. 5. As shown in FIG. 4A, a substrate 21 is first provided, and the substrate 21 is used as a wafer carrier of the ball grid array package structure, and can be pre-cut to a desired size or a plurality of matrix arrays. The tantalum is formed on a stack of substrate strips which are then diced into individual semiconductor package structures after packaging. The lower surface 212 of the substrate 210 is provided with the circuit layer 216, and the circuit layer 216 is covered by the solder resist layer 218, but does not cover the relative positions of the end vias 2 1 3 for subsequent These locations form the shell electrodes 215. In particular, the end vias 213 can be formed by laser, mechanical drilling or reactive ion etching, and the circuit layer 216 is not interrupted. The end vias 213 correspond to the pins of the ball grid array package structure 200. Next, as shown in FIG. 4B, the punching holes 213 are aligned with the end points 13 201007909 by a punching tool 1 ,, and the line calling layer 216 is punched down to form a plurality of shells protruding from the lower surface 212. Type electric earth electrode 215. Specifically, the shell-shaped electrodes 215 are non-planar thin-packed #, and TJ covers the ends of the end-holes 213 to avoid the 封-A of the sealant 230. In the present embodiment, the 型-type electrodes 2丨5 may have a square strip section to provide a flat surface. However, the cross-section of the shell-shaped electrodes 215 may be various shapes of 4V-shaped strips or other strips. The formation of the shell electrodes 215 can be formed without complicated steps and additional additional components, and can be used as an integrated external ball end to replace the solder balls. Further, as shown in FIG. 4B, the upper surface 2102 of the substrate 21 can be preliminarily provided with the patterned doped layer 240 for subsequent adhesion to the wafer. The patterned doped layer 240 can be formed on the upper surface 211 of the substrate 210 by screen printing or syringe dispensing or attachment. The patterned doped layer 240 can be selected from one of a B-stage colloid, a liquid glue, or a poly-nalylene (ρι) tape. As shown in FIG. 5, preferably, the patterned doped layer Φ 240 does not cover the end vias 213 and forms a mold via hole in the wafer cover region for subsequent filling of the encapsulant 230. In. Thereafter, as shown in Fig. 4C, the wafer 22 is placed on the substrate 21A. The wafer 220 is adhered to the upper surface 211 of the substrate 210 by the patterned doped layer 240. In this embodiment, the active surface 221 of the wafer 220 is directed downward, and the pads 223 are located in a central region of the wafer 220. The internal electrical connection channel 217 is also formed in a central region of the substrate 210. The pads 223 are aligned to be exposed within the internal electrical connection channel 217. Specifically, as shown in Figures 3 and 5, the internal electrical connection 14 201007909 217 can be a central elongated slot. The traces 2i4 can extend into the internal electrical connection channel 217 and can be directly bonded to the pads 223. Therefore, one of the traces 214 can be extended and suspended in the position of the internal electrical connection channel 217 corresponding to the pads 223, and a stamping tool will be placed in the internal electrical connection by using the pin-connected σ technique. The floating traces 214 in the channel 217 are thermocompression bonded to the pads 223 to electrically connect the wafer 220 to the substrate 210. φ The end vias 213 are substantially circular holes, the positions of which correspond to the feet t of the ball grid array package structure, but the end vias 2 1 3 may also be rectangular holes or other shapes. In this embodiment, the shell-shaped electrodes .215 can be metal tantalum and deformed by pin bonding (ieaij b〇n(j) method. The metal pads are covered by the plane before being punched. Corresponding ports of the end through holes 2 1 3. Finally, as shown in FIG. 3, the encapsulant 230 is formed on the upper surface 211 of the substrate 210 by a molding (or transfer forming) method, and the # is filled in The internal electrical connection channel 217 and the end vias 213 can completely seal the wafer 220' to hermetically isolate the internal components from the outside from external impact or contamination. Therefore, the shell electrodes 215 The input/output (1/0) input/output end is electrically connected to the external device, and the insulating body 230 is filled into the inner space of the shell-shaped electrode 215 to form the insulation of the integral interconnection. The bumps 231 ′ can prevent the shell-shaped electrodes 215 from being deformed or displaced. In addition, the exposed surfaces of the shell-shaped electrodes 215 can be used as reinforcing electrodes by the metal bonding layer 250 to increase the shell-shaped electrodes 15 201007909 Structural strength of 215. According to the second aspect of the present invention DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT, FIG. 6 is a cross-sectional view of another solder ball. The ball grid-substrate 210 and at least one wafer 220 ball grid array package structure are mainly included in the first array package structure 300 and include a package (four) 230. The first embodiment of the present invention is the same as the first embodiment and is represented by the same reference numerals, so that it can be understood that the above-mentioned functions are not described. e In this embodiment, the ball grid array package structure 3 can additionally include a plurality of The bonding wires 360 are electrically connected to the soldering pads 223 and the traces 214 through the internal electrical connection channels 217. The bonding wires 360 may be made of gold wires, inscribed wires or copper. a wire in which a gold wire is more commonly used. In this embodiment, a wire bonding electrical connection is used instead of a wire 2 i 4 stamping to directly bond to the pads 223 ^but without limitation, the wafer 22 can be removed. In addition to the wire-bonding, the electrical interconnection between the wafers 220 and the substrate 210 can also be accomplished by flip-chip bonding (fHp chip) or other known electrical connections. Specific embodiment, another exemption The spherical ball grid array package structure is illustrated in a cross-sectional view of Fig. 7. The ball grid array package structure 400 mainly includes a substrate 21, at least one wafer 220, and a colloid 230. The main components are the same as the first embodiment. Preferably, the circuit layer 216 is formed on the upper surface 211 of the substrate 210 to prevent the shell electrodes 215 from being generated by the substrate 21 2010 16 201007909 stripping In the present embodiment, the back surface 222 of the wafer 220 can be attached to the upper surface 211 of the substrate 210, and the solder pads 22 3 and the traces 214 are electrically connected by a plurality of bonding wires 460. . The ball grid array package structure 400 can be applied to a package of a multi-wafer stack, that is, a plurality of wafers 22 are stacked on the upper surface 211 of the substrate 21, and then electrically connected to the substrate 210. Further, in this embodiment. The shell-shaped electrodes 215 have a circular arc-shaped cross section and the internal space is filled by the encapsulant 230 to form an insulating bump 23 1 'to extend the variation of the existing packaging material so as to omit the conventional solder ball setting. It can be used as an integrated external ball end, without adding packaging steps or adding additional solder balls. In the process, the solder ball setting step after the conventional sealing can be omitted, and the conventional solder ball can be broken or dropped in the structure. question. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. The technical scope of the present invention is subject to the scope of the appended patent application. Any person skilled in the art can make any equivalent changes or modifications to the equivalent embodiments by using the technical content of the above-mentioned disclosure, but the above embodiments are implemented according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications made by the examples are still within the scope of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional ball grid array package structure. 2A-2D: A schematic cross-sectional view of a conventional ball grid array package constructed in process 17 201007909. Fig. 3 is a cross-sectional view showing a ball grid array sealing structure of a solderless ball in accordance with a first embodiment of the present invention. 4A and 4D are cross-sectional views showing the components of the ball-to-rug array package constructed in the process according to the first embodiment of the present invention. The fifth embodiment is a schematic view of the upper surface of the substrate of the ball grid array package structure according to the present invention. φ 帛6图' is a schematic cross-sectional view of a ball-to-pole array package structure of a Xue-free ball in accordance with a second embodiment of the present invention. Figure 7 is a cross-sectional view showing a ball-like array package structure of a solderless ball according to a third embodiment of the present invention. [Major component symbol description] 10 stamping tool 100 ball grid array package structure 110 substrate 111 upper surface 117 internal electrical connection channel 120 wafer 121 active 123 pad 130 encapsulant 14 〇 晶 170 170 solder ball 200 ball grid array package structure 210 Substrate 211 on the table 213 end point through hole 2 14 trace 216 line layer 112 lower surface 122 back side 160 wire surface 212 lower surface 215 shell electrode 217 internal electrical connection channel 201007909 218 solder mask 222 back 220 wafer 221 active Surface 223 solder pad 230 encapsulant 231 insulating bump 240 patterned adhesive layer 250 metal bonding layer 300 ball grid array package structure 3 60 0 wire 400 ball grid array package structure 460 460 wire 19

Claims (1)

201007909 十、申請專利範圍： 1、 一種免用銲球之球栅陣列封裝構造，包含： 基板，係具有一上表面、一下表面、複數個端點通孔、 複數個跡線以及複數個連接該些跡線之殼型電極，其中 該些殼型電極係對準並連通至該些端點通孔，更突出於 該下表面； 至少一晶片，係設置於該基板之該上表面，該晶片之— ❿ 主動面係具有複數個銲墊，該些銲墊係電性連接至該此 跡線；以及 一封膠體’係形成於該基板之該上表面並通過該些端點 通孔填入至該些殼型電極之内部空間。 2、 如申請專利範圍第丨項所述之免用銲球之球柵陣列封裝 構造’其中該些殼型電極與該些跡線係一體連接於一 路層。 3、 如申請專利範圍第2項所述之免用銲球之球柵陣列封裝 ® 構造’其中該線路層係形成於該基板之該下表面。 4、 如申請專利範圍第2項所述之免用銲球之球柵陣列封裝 構造’其中該線路層係形成於該基板之該上表面。 5、 如申請專利範圍第1項所述之免用銲球之球柵陣列封裳 構造，其中該些殼型電極係非平面覆蓋該些端點通孔之 —端0 6、 如申請專利範圍第1項所述之免用銲球之球柵陣列封裝 構造’其中該封膠體在該些殼型電極之内部空間係形成 為複數個一體互連之絕緣凸塊。 20 201007909 7、如申請專利範圍 構造’另包含有 板，該圖案化黏 絕緣凸塊一體互 第6項所述之免用 一圖案化黏晶層， 晶層係不密閉該些 連。 銲球之球柵陣列封裝 係黏著該晶片與該基 端點通孔’以使該些 8、 如申請專利侧第）項所述之免用銲球之球柵降列 構造，其中該些殼型電極係具有圓弧形截面。201007909 X. Patent application scope: 1. A ball grid array package structure for eliminating solder balls, comprising: a substrate having an upper surface, a lower surface, a plurality of end point through holes, a plurality of traces, and a plurality of connections a shell-shaped electrode of the traces, wherein the shell-type electrodes are aligned and communicated to the end-point vias to protrude further from the lower surface; at least one wafer is disposed on the upper surface of the substrate, the wafer The active surface has a plurality of pads electrically connected to the traces; and a gel is formed on the upper surface of the substrate and filled through the end vias To the internal space of the shell-shaped electrodes. 2. The ball grid array package structure of the spare solder ball of the invention of claim </ RTI> wherein the shell electrodes are integrally connected to the trace layers. 3. The ball grid array package of the solder ball of the exemption solder ball described in claim 2, wherein the circuit layer is formed on the lower surface of the substrate. 4. The ball grid array package structure of the free solder ball according to claim 2, wherein the circuit layer is formed on the upper surface of the substrate. 5. The ball grid array sealing structure of the free solder ball according to claim 1, wherein the shell electrodes are non-planarly covering the end vias - end 0.6, as in the patent application scope The ball grid array package structure of the solder ball of the above-mentioned item 1 wherein the sealant is formed in the inner space of the shell electrodes as a plurality of integrally interconnected insulating bumps. 20 201007909 7. As claimed in the patent application, the structure ′ further includes a plate, and the patterned viscous bumps are integrated with a patterned viscous layer as described in item 6, and the layer does not seal the connections. The ball grid array package of the solder ball adheres the wafer and the base end via hole to make the spherical ball drop-down structure of the solder ball as described in claim 8, wherein the shell The type electrode system has a circular arc cross section. 9、 如申請專利錢第i項料之免料球之球栅陣列封裝 構造，其中該些殼型電極係具有方形條截面。 1〇、如中請專利範圍第丨項所述之免料球之球柵陣列封 裝構造’另包含-金屬接合層，包覆該些殼型電極之外 露表面。 U、如申請專利範圍第！項所述之免用銲球之球栅陣列封 裝構造’其中該封膠體係完全密封該晶片。 12、如申請專利範圍第i項所述之免用銲球之球栅陣列封 裝構造，其中該基板係具有一内部電性連接通道，其係 貫穿該上表面至該下表面，當該晶片之該主動面貼附於 該基板之該上表面，以使該基板不覆蓋該些銲墊。 13、如申請專利範圍第12項所述之免用銲球之球柵陣列封 裝構造’其中該些跡線係延伸至該内部電性連接通道内 並直接接合至該些銲塾。 14、 如申請專利範圍第12項所述之免用銲球之球栅陣列封 裝構造’另包含複數個銲線’係通過該内部電性連接通 道以電性連接該些銲墊與該些跡線。 15、 如申請專利範圍第12項所述之免用銲球之球柵陣列封 21 201007909 裝構造’其中該封_係更填人該内部電性連接通道。 16、 如申請專利漏第12項所述之免用録球之球栅陣列封 裝構造’其中該内部電性連接通道係為一中央狹長槽孔。 17、 如申請專利範圍第i項所述之免用輝球之球拇陣列封 裝構造’其中該晶片係具有一相對於該主動面之一背 面’該#面係貼附於該基板之該上表面，該球柵陣列封 裝構造係另包含複數個銲線，係電性連接該些鲜墊與該 些跡線。 18、 如申請專利範圍第1項所述之免用銲球之球栅陣列封 裝構造’其中該些殼型電極係為金屬塾，並經引腳結合 (lead bond)方式變形形成。 229. The ball grid array package structure of the material-free ball of claim i, wherein the shell-type electrodes have a square strip section. 1 . The ball-free ball grid array package structure of the free-bead ball according to the above-mentioned patent scope is further included as a metal bonding layer covering the exposed surfaces of the shell-shaped electrodes. U, such as the scope of patent application! The ball grid array package construction of the spare solder ball described in the item wherein the encapsulation system completely seals the wafer. 12. The ball grid array package structure of the free solder ball according to claim i, wherein the substrate has an internal electrical connection channel extending through the upper surface to the lower surface when the wafer is The active surface is attached to the upper surface of the substrate such that the substrate does not cover the pads. 13. The ball grid array package construction of the free solder ball of claim 12, wherein the traces extend into the internal electrical connection channel and are directly bonded to the solder pads. 14. The ball grid array package structure of the spare solder ball according to claim 12, further comprising a plurality of bonding wires, wherein the pads are electrically connected to the traces through the internal electrical connection channels line. 15. The ball grid array seal of the spare solder ball according to claim 12 of the patent application scope of claim 12, wherein the seal is further filled with the internal electrical connection passage. 16. The ball grid array package structure of the free-recording ball described in claim 12, wherein the internal electrical connection channel is a central elongated slot. 17. The ball-and-eye array package structure of the exempted glow ball of claim i, wherein the wafer has a back surface of the active surface attached to the substrate The surface of the ball grid array package structure further includes a plurality of bonding wires electrically connected to the fresh pads and the traces. 18. The ball grid array package structure of the free solder ball according to claim 1, wherein the shell electrodes are metal crucibles and are deformed by a lead bond. twenty two
TW97130894A 2008-08-13 2008-08-13 Ball grid array package without solder balls TW201007909A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI549248B (en) * 2011-11-01 2016-09-11 住友電木股份有限公司 Method of manufacturing semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI549248B (en) * 2011-11-01 2016-09-11 住友電木股份有限公司 Method of manufacturing semiconductor package

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