1236718 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種無導線架之晶片封裝方法 指-種免用㈣架即能使裸晶片I有可對外電性 功能，而可組餘電路板等設備應用《晶片縣方法設 計。 【先前技術】 傳統的晶片封裝方法，通常包括有（一）晶圓切割 (Die Saw)，係將晶圓切割分離為複數裸晶片。（二） 鮮晶（Die Attach)，將切割完成的裸晶片放置在導料 上面，並使用黏性膠帶加以黏著固定。（三）打線（Wk Bond)，將裸晶片上的訊號接點以金屬線連接到導線架 的引腳内端。（四）封膠（Mold)，使用半熔化之絕緣性 封膠體密封住晶片周圍及導線架，僅預留導線架外端部 分接點外露。（E)切單成型，即以機器將導線架及封膠 體多餘的材料切除’並成型為獨立的一顆封裝晶片。 上揭封裝製成之晶片結構如第九圖所示，包括具有 一金屬質導線架10,該導線架10係為兩側或四周採二沖 壓出複數片狀引腳1 〇 1所排列構成，各個引腳i 〇 1下端 沖設有一凸塊102，藉以該凸塊102端面i 03作為對外導 電部位，而導線架10之引腳101上方係貼覆有一黏性膠 帶20，於該膠帶20固定有一裸晶片3〇 ,藉此，並於該 裸曰曰片30與各引腳1〇1間設有一構成電性連接之金屬 線40 ’且在金屬線4〇連接完成後，實施有上述之一絕緣 性封膠體50密封住晶片30周圍及導線架1〇底面，僅預 留所述該引腳101之下端面103或外端露出封膠體5〇， 藉此可與電路板組裝形成電性連接應用。 1236718 /上述晶片封裝方法中，該導線架另需預先使用金屬 =衝壓、裁切成型’而衝壓、裁切技術的困難點在於精 密f控制，特別是使用在晶片封裝所需之導線架處，必 :^合現今電子7〇件精小化趨勢，因此相對的製造成本 較高；其次，習知該金屬線4〇焊接（打線）完成後，另 需經過封膠體5GS封製成，其置放在模具内注入半融化 的封膠體5G過程中，經常發生衝擊、壓力損毁金屬線4〇 或其吼唬接點情事，因而生產許多瑕疵品，必須再後續 檢測時使用高貴的儀器探測，由此可見，習知晶片封裝 製程使用導線架及打線方法，不利於簡化封裝製程，^ 其封裝成本及品管成本無法有效降低。 【發明内容】 本發明主要目的，係在提供一種無導線架之晶片封 裝方法，特別指一種免用習知的導線架元件，且不需經 過金屬線焊接（打線）製程，即能使裸晶片具有可對外 電I*生導接功月b之晶片封裝方法，藉以達成封裝程序簡易 ’以及成本降低、封裝晶片精小化等效益。 依上述目的，本發明無導線架之晶片封裝製程，其 實施内容包括： ’、 (A) 金屬導線成型，預先令複數金屬導線之内端設 有一錫凸塊，且亦可於外端設有一錫凸塊； (B) 覆膠，係於裸晶片之訊號接點該面覆設一層接 著膠層，該接著膠層設有對應晶片訊號接點之内接窗口 ’令裸晶片訊號接點經由接著膠層之内接窗口外露； (C) 上片，將内面固設有上述複數金屬導線之一固 疋層覆設於接著膠層外面，該固定層設有對應電路板訊 號接點之外接窗口，藉此使金屬導線外端延伸於外接窗 1236718 =電=屬接導線内端之錫凸塊係與裸晶一接點 導：電 /、I屬導線外端構成電性連接 ，並令導電體露出於外接窗口處； ()切單成型’將多餘的接著膠層及固定層材料切 除，並形成單一顆封裝晶片； :此，即組成：裸晶片之訊號接點面依序設有一接 ^曰、複數金屬導線及—固定層之封裝晶片，令金屬 導線内端錫凸塊延伸於接著膠層之内接窗口與晶片訊 號接點構成電性連接’而金屬導線外端延伸於固定層之 卜接固π與導電體構成電性連接，俾能免用習知導線架 及焊接金屬線（打線）製程，即可組成一封裝晶片，利 用該導電體與電路板等設備作電性連接應用。 【實施方式】 絲依附圖實施例將本發明之製程方法、結構特徵及 其他之作用、目的詳細說明如下·· 、月參考苐圖至苐二圖所示，本發明所為一種『無 導線架之晶片封裝方法』，其結構係為—裸晶片i之訊 號接點11該面依序設有—接著膠層2、複數金屬導線3 及一固定層4等所組成，主要製程方法包括·· ^ (A)金屬導線成型，請參閱第四圖及第五圖所示， 係預先々複數金屬導線3之内端31上面設有一錫凸塊 311且亦可於金屬導線3外端32下面設有一錫凸塊 321 ;其中，該錫凸塊311、錫凸塊321之構成方式，可 於所述金屬導線3之内端31及外端32預先成型一板片 312、322，藉此於該板片312、322選定面點設所述錫 1236718 凸塊311、錫凸塊321 ;另者，該板片312、322所連接 之金屬導線3内端31及外端32部，亦可實施為連續彎折 狀之彈性結構，使板片312、322及其錫凸塊311、錫凸 塊321可調整位移而與下述之内接窗口 21及外接窗口 41精確對準； (B)覆膠，參閱第二圖及第六圖所示，係於裸晶片 1之訊號接點11該面覆設一層接著膠層2，使該接著膠 層2具有對應裸晶片1訊號接點11之内接窗口 $彳（如第 六圖所示），令裸晶片i之訊號接點彳彳經由接著膠層2 之内接窗口 21外露；其中，所述覆設接著膠層2方法， 係可於該裸晶片1切單（成為單一晶粒）後各別實施（ 參閱第六圖所示），或可於該裸晶片i切單後，將複數 裸晶片1連續貼覆於一膠帶材料之接著膠層2上實施 兀成（參閱第七圖所示），或可在該裸晶片丄切單前， 即於晶圓10狀態時預先覆設所述該接著膠層2(參閱第 八圖所示另者，該接著膠層2構成方式係包括可應 用黏著性膠帶材料之貼覆方式，或以樹脂、矽膠等材料 之塗a又方式達成，其塗設方式包括可為網屏印刷法（1236718 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to-a kind of chip packaging method without a lead frame refers to-a kind of free-rack can make the bare chip I have external electrical functions, and can be used for Circuit board and other equipment use the "chip county method design. [Previous Technology] Traditional wafer packaging methods usually include (1) Die Saw, which separates wafers into multiple bare wafers. (2) Fresh Attach: Place the diced bare wafer on the guide and fix it with adhesive tape. (3) Wk Bond. Connect the signal contacts on the bare chip to the inner ends of the leads of the lead frame with metal wires. (4) Mold, use semi-melted insulating sealant to seal around the chip and the lead frame, leaving only the exposed points of the outer ends of the lead frame exposed. (E) Singulation molding, that is, cutting off the excess material of the lead frame and encapsulant with a machine and molding it into an independent package chip. As shown in the ninth figure, the chip structure made by the demolition package includes a metal lead frame 10, which is formed by arranging a plurality of sheet-shaped pins 101 on two sides or four sides. A bump 102 is punched at the lower end of each pin i 〇1, and the end surface i 03 of the bump 102 is used as an external conductive part, and an adhesive tape 20 is pasted on the lead 101 of the lead frame 10 and fixed on the tape 20 There is a bare chip 30, by which a metal wire 40 'constituting an electrical connection is provided between the bare chip 30 and each pin 101, and after the connection of the metal wire 40 is completed, the above-mentioned An insulating sealing compound 50 seals around the chip 30 and the bottom surface of the lead frame 10, leaving only the lower end surface 103 of the pin 101 or the sealing compound 50 exposed on the outer end, thereby assembling with the circuit board to form electrical properties. Connect applications. 1236718 / In the above chip packaging method, the lead frame also needs to use metal = stamping, cutting and forming in advance. The difficulty of stamping and cutting technology lies in precise f control, especially for the lead frame required for chip packaging. , Must: ^ today's trend of 70 electronic miniaturization, so the relative manufacturing cost is relatively high; second, it is known that after the metal wire 40 welding (wire bonding) is completed, it needs to be sealed by a 5GS sealant, which In the process of injecting semi-melted sealing compound 5G in the mold, shocks and pressures often damage the metal wire 40 or its shouting joints. Therefore, many defective products must be produced. Noble equipment must be used for subsequent inspection. It can be seen that the conventional chip packaging process uses lead frames and wire bonding methods, which is not conducive to simplifying the packaging process. Its packaging cost and quality control cost cannot be effectively reduced. [Summary of the Invention] The main purpose of the present invention is to provide a method for packaging a chip without a lead frame, in particular to a conventional lead frame component that is free of the conventional lead frame component, and can be used to make a bare chip without going through a metal wire bonding (bonding) process. It has a chip packaging method that can be used for external electrical connection, so as to achieve the advantages of easy packaging process, cost reduction, and miniaturization of packaged wafers. According to the above purpose, the chip packaging process of the present invention without a lead frame, the implementation contents include: ', (A) metal wire molding, the inner end of a plurality of metal wires is provided with a tin bump in advance, and an outer end may also be provided with a Tin bumps; (B) cladding, which is a layer of adhesive on the surface of the signal contacts of the bare chip. The adhesive layer has an internal window corresponding to the signal contacts of the wafer. Then, the inner window of the adhesive layer is exposed; (C) On the film, the inner layer is fixed with one of the above-mentioned multiple metal wires. A fixed layer is placed on the outside of the adhesive layer, and the fixed layer is provided with a corresponding circuit board signal contact. Window, so that the outer end of the metal wire extends to the outer window 1236718 = electrical = the tin bumps that belong to the inner end of the wire are connected to the bare one contact: electrical /, the outer end of the I wire forms an electrical connection, and makes The conductive body is exposed at the external window; () Cut-to-length molding to cut away the excess adhesive layer and fixed layer material and form a single packaged chip;: This is the composition: the signal contact surface of the bare chip is sequentially provided with a ^^, plural metal wires and-solid The packaging chip of the fixed layer allows the inner bump of the metal wire to extend from the inner window of the adhesive layer and the signal contact of the chip to form an electrical connection. The outer end of the metal wire extends from the fixed layer to the π and the conductor. To form an electrical connection, it is possible to form a packaged chip without using a conventional lead frame and soldering metal wire (bonding) process, and use the conductor and a circuit board for electrical connection applications. [Embodiment] The process method, structural features, and other functions and purposes of the present invention will be described in detail according to the embodiments of the accompanying drawings. The monthly reference is shown in the figure to the second figure. The present invention is a kind of Chip packaging method ", the structure of which is-the signal contact 11 of the bare chip i is arranged in this order in sequence-followed by an adhesive layer 2, a plurality of metal wires 3, and a fixed layer 4, etc., the main process methods include ... (A) Forming of metal wires, please refer to the fourth and fifth figures. A tin bump 311 is provided on the inner end 31 of the plurality of metal wires 3 in advance, and a metal bump 3 may be provided below the outer end 32 of the metal wires 3. Tin bump 321; wherein, the structure of the tin bump 311 and the tin bump 321 can be formed in advance on the inner end 31 and the outer end 32 of the metal wire 3 by a sheet 312, 322, so that The selected surfaces of the sheets 312 and 322 are provided with the tin 1236718 bump 311 and the tin bump 321. In addition, the inner end 31 and the outer end 32 of the metal wire 3 connected to the plates 312 and 322 can also be implemented as continuous The bent elastic structure enables the plates 312, 322 and their tin bumps 311, 3 21 The displacement can be adjusted to precisely align with the inner window 21 and the outer window 41 described below; (B) Glue, see the second and sixth figures, which is on the surface of the signal contact 11 of the bare chip 1 Overlay an adhesive layer 2 so that the adhesive layer 2 has an internal connection window corresponding to the signal contact 11 of the bare chip 1 (as shown in the sixth figure), so that the signal contact 彳 彳 of the bare chip i passes through The inner window 21 of the adhesive layer 2 is exposed; wherein the method of covering and adhering to the adhesive layer 2 can be implemented separately after the bare wafer 1 is singulated (to become a single die) (see the sixth figure), Or after the bare wafer i is cut, a plurality of bare wafers 1 may be successively pasted on a tape material and then adhered to the adhesive layer 2 (see FIG. 7), or the bare wafer may be cut and cut Before, that is, the adhesive layer 2 is pre-laid in the state of the wafer 10 (refer to FIG. 8 for the other, the adhesive layer 2 is formed in a manner of applying an adhesive tape material, or It is achieved by coating a material such as resin and silicone. The coating method includes screen printing (
Screen)、點膠法（Dispe)、薄膜製程（Fj|m)及模型 塑造法（Mold)等，藉此可於覆膠後直接成型所述之内 接窗口 21，並可選擇性經過烘烤程序，使該接著膠層2 凝固； (C)上片，參閱第二圖及第六圖所示，可令上述之 複數金屬導線3預設於一固定層4内面，藉此將内面設 有複數金屬導線3之固定層4覆設於接著膠層2外面 ，該固定層4係預設有對應電路板接點之外接窗口41 ，使金屬導線3内端31之錫凸塊311與裸晶片i之訊號 接點11構成電性連接，而金屬導線3之外端μ乃延伸於 1236718 固定層4外接窗口 41處；其中，所述覆設固定層4步驟 亦可於該裸晶片1切單（成為單一晶粒）狀態各別實 施（參閱第六圖所示），或可於複數切單之裸晶片1連 續貼覆於接著膠層2後實施完成（參閱第七圖所示）， 或可在該裸晶片1切單前，即於晶圓10狀態覆設所述該 接著膠層2之後實施完成（參閱第八圖所示）；另者， 該固定層4構成方式，包括可為一樹脂膜黏著於接著膠 層2外面，其後並可選擇性經過烘烤程序，使該固定層 4凝固； (D) 植入導電體’參閱第二圖及第三圖所示，即於 該固定層4之外接窗口 41植入金屬材質導電體5，令該 導電體5與金屬導線3之外端32部構成電性連接，並令 導電體5露出於外接窗口 41處，可與電路板等設備作電 性連接；其中，所述該導電體5之構成方式，係包括可 為植入錫球或注入錫膏方式達成；請參考第六圖所示， 本發明該固定層4亦可於對應接著層2之内接窗口 21 處預開設有内接窗口42，藉此於上述之（c)上片製程後 ，亦可於該内接窗口42中實施上揭植入導電體製程，俾 使複數導線3之内端31與裸晶片丄訊號接點彳彳構成穩 固電性連接狀態。 (E) 切單成型，即將多餘的接著膠層2及固定層4 $料切除，或將晶圓10之裸晶片連同接著膠層2及固 定層4切單，並形成個別獨立的單一顆封裝晶片； 藉本發明上述(A)金屬導線成型、（B)覆膠、(c)上片 、（D)植入導電體，以及（E)切單成型等製程步驟，即能 組成該裸晶片1之訊號接點彳彳面依序設有一接著膠層 2、複數金屬導線3及一固定層4之封裝晶片（如第二 圖及第三圖所示），令該金屬導線3内端31之錫凸塊311 1236718 延伸於接著膠層2内接窗口21與裸晶片1訊號接點11 構成電性連接，而金屬導線3外端32 (可為其錫凸塊 321)係延伸於外接窗口 41與窗口中之導電體$構成電 料接’俾能免用習知導線架及焊接金屬線（打線）製 紅、、且成封裝晶片，可利用該導電體與電路板等設備作 電性連接應用。 本奄明所揭無導線架之晶片封裝方法，已免除傳統 使用導線架之製程，故可避免傳統導線架衝壓、裁切等 製程中品質難以難精確掌控等缺憾，以降低使用導線架 之材料成本以及品管成本等；並因本發明晶片封裝製程 不f使用導線架，即可使整體晶片封裝結構更臻輕薄， 以符合時下電子產品精巧化設計趨勢，並增進同一晶圓 =切割出的裸晶片i產量。其次，本發明該複數金屬 秦3係可預先黏著於固定層4 (或接著膠層2)，再 令固定層4貼覆於接著層2使複數導線3固定，因此該 :請金屬導線3於製程中不必焊接，將來如需封膠體密 么亦無而承叉傳統封膠體灌注之壓力及衝擊力等，不 僅能改善傳統打線後封膠體封裝程序所造成的損害，進 效提升晶片構裝之良品率，並能因此簡化晶片封 （無需傳統打線步驟），俾有效降低封裝成本及 後續的檢測品管成本等。 、、、示上所述，本發明 P. a 無導線架之晶片封裝方法』， ，且二性與創作性，其手段之運用亦出於新穎無疑 功效以計目的誠然符合，已稱合理 =依法提出發明專射請，《請料惠予詳審 並賜准專利為禱，至感德便。 1236718 【圖式簡單說明】 第一圖為本發明晶片封裝製程之實施步驟示意圖。 第二圖為本發明晶片封裝狀態之縱向斷面示意圖。 第三圖為本發明晶片封裝狀態之橫向斷面示意圖。 第四圖為本發明金屬導線預先成型狀態之示意圖。 第五圖為本發明金屬導線預先成型狀態之示意圖。 第六圖為本發明裸晶片切單後之封裝結構分解示 第七圖為本發明複數裸晶片切單後之封裝結構分 解示意圖。 解示意圖。 第八圖為本發明裸晶片於晶圓狀態之封裝結構分 弟九圖為習知晶片封裝妹構 【主要元件符號說明】金屬導線成型（A); 上片（C);切單成型（E); 晶圓10 ; 之斷面示意圖。 接著膠層2 ; 金屬導線3 ; 錫凸塊311 ; 外端32 ; 板片322 ; 外接窗口 41 ; 導電體5 ; 覆膠（B); 植入導電體（D); 裸晶片1 ; 訊號接點11 ; 内接窗口 21 ; 内端31 ; 板片312 ; 錫凸塊321 ; 固定層4 ; 内接窗口 42 ;Screen), Dispe, Fj | m, and Mold, etc., so that the inscribed window 21 can be directly formed after laminating, and can be optionally baked Procedure to make the adhesive layer 2 solidify; (C) on the film, referring to the second and sixth figures, the plurality of metal wires 3 can be preset on the inner surface of a fixed layer 4, so that the inner surface is provided with The fixing layer 4 of the plurality of metal wires 3 is covered on the outside of the adhesive layer 2. The fixing layer 4 is preset with an external window 41 corresponding to the circuit board contacts, so that the tin bumps 311 and the bare chip 31 on the inner end 31 of the metal wires 3 are preset. The signal contact 11 of i constitutes an electrical connection, and the outer end μ of the metal wire 3 extends from the 1236718 fixed window 4 to the outer window 41; wherein the step of covering the fixed layer 4 can also be singulated on the bare chip 1. (Become a single die), each state can be implemented separately (see Figure 6), or the bare wafers 1 that have been cut into multiple pieces can be consecutively pasted on the adhesive layer 2 (see Figure 7), or It can be implemented before the bare wafer 1 is cut, that is, after the adhesive layer 2 is covered in the state of the wafer 10 ( (See FIG. 8); In addition, the fixing layer 4 is formed in a manner that a resin film can be adhered to the outside of the adhesive layer 2 and thereafter, the fixing layer 4 can be optionally subjected to a baking process to solidify the fixing layer 4; (D) Implanting a conductive body 'Refer to the second and third figures, that is, a metal conductive body 5 is implanted in the window 41 outside the fixed layer 4 so that the conductive body 5 and the outer end 32 of the metal wire 3 The electrical connection of the conductive body 5 is made, and the conductive body 5 is exposed at the external window 41, and can be electrically connected with the circuit board and other equipment. The conductive body 5 is formed in a manner that can be implanted with a solder ball or The method of injecting solder paste is achieved; please refer to the sixth figure, the fixed layer 4 of the present invention may also be provided with an inscribed window 42 at a position corresponding to the inscribed window 21 of the bonding layer 2, so that the above (c) After the chip manufacturing process, a conductive lift-up process can also be performed in the internal window 42 so that the inner end 31 of the plurality of wires 3 and the bare chip 丄 signal contacts 接 form a stable electrical connection state. (E) Cut-to-order molding, that is, the excess adhesive layer 2 and the fixed layer 4 are cut off, or the bare wafer of the wafer 10 together with the adhesive layer 2 and the fixed layer 4 is singulated, and an individual single package is formed. Wafer; The bare chip can be formed by the process steps of (A) metal wire molding, (B) over-molding, (c) upper film, (D) implanted conductor, and (E) singulation molding of the present invention. A package chip (shown in the second and third figures) with an adhesive layer 2, a plurality of metal wires 3, and a fixed layer 4 is sequentially arranged on the signal contact surface of 1 so that the inner end 31 of the metal wire 3 The tin bump 311 1236718 extends from the inner window 21 of the adhesive layer 2 and the signal contact 11 of the bare chip 1 to form an electrical connection, and the outer end 32 of the metal wire 3 (which can be its tin bump 321) extends to the external window 41 and electrical conductors in the window are used to form electrical connections. It is possible to use conventional lead frames and soldering metal wires (wired) to make red and package chips. The conductors and circuit boards can be used for electrical properties. Connect applications. The method of chip packaging without lead frame disclosed in the present invention has eliminated the traditional process of using lead frame, so it can avoid the disadvantages of difficult to accurately control the quality of traditional lead frame stamping, cutting and other processes, so as to reduce the use of lead frame materials. Cost and quality control cost; and because the chip packaging process of the present invention does not use a lead frame, the overall chip packaging structure can be made thinner and thinner, in line with the current trend of sophisticated design of electronic products, and to promote the same wafer = cut out Yield of bare wafers. Secondly, according to the present invention, the plurality of metal Qin 3 series can be adhered to the fixing layer 4 (or adhesive layer 2) in advance, and then the fixing layer 4 is adhered to the adhesion layer 2 to fix the plurality of wires 3, so: No soldering is required in the manufacturing process. In the future, if it is necessary to seal the colloid, the pressure and impact force of the traditional sealing colloid infusion can not only improve the damage caused by the traditional colloid sealing process after wire bonding, but also improve the efficiency of chip assembly. Yield rate, which can simplify wafer packaging (no traditional wire bonding steps), effectively reducing packaging costs and subsequent inspection quality control costs. As shown in the above, the P.a. leadless chip packaging method of the present invention ", and the dual nature and creativeness, the use of its means is also true for the sake of novelty and undoubted efficacy, and it has been said to be reasonable = In accordance with the law, a patent for invention was filed. "Please look forward to scrutinizing the patent and granting a patent as a prayer. 1236718 [Brief description of the drawings] The first figure is a schematic diagram of the implementation steps of the chip packaging process of the present invention. The second figure is a schematic longitudinal sectional view of a chip package state of the present invention. The third figure is a schematic cross-sectional view of the chip packaging state of the present invention. The fourth figure is a schematic view of a pre-molded state of the metal wire of the present invention. The fifth figure is a schematic view of a pre-molded state of the metal wire of the present invention. The sixth figure is an exploded view of the package structure after singulation of the bare chip according to the present invention. The seventh figure is a exploded view of the package structure after singulation of a plurality of bare chips according to the present invention. Solution schematic. The eighth figure is the package structure of the bare chip in the wafer state of the present invention. The ninth figure is the conventional chip package sister structure. [Description of the main component symbols] Metal wire forming (A); Upper chip (C); Cut-to-shape (E ); Sectional view of wafer 10; Adhesive layer 2; metal wire 3; tin bump 311; outer end 32; plate 322; external window 41; electrical conductor 5; rubber (B); implanted electrical conductor (D); bare chip 1; signal connection Point 11; Inner window 21; Inner end 31; Plate 312; Tin bump 321; Fixed layer 4; Inner window 42;