TW200908327A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
TW200908327A
TW200908327A TW097123822A TW97123822A TW200908327A TW 200908327 A TW200908327 A TW 200908327A TW 097123822 A TW097123822 A TW 097123822A TW 97123822 A TW97123822 A TW 97123822A TW 200908327 A TW200908327 A TW 200908327A
Authority
TW
Taiwan
Prior art keywords
region
conductive
semiconductor device
impurity
semiconductor substrate
Prior art date
Application number
TW097123822A
Other languages
English (en)
Inventor
Ji-Hong Kim
Duck-Ki Jang
Byung-Tak Jang
Song-Hee Park
Original Assignee
Dongbu Hitek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Hitek Co Ltd filed Critical Dongbu Hitek Co Ltd
Publication of TW200908327A publication Critical patent/TW200908327A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

200908327 九、發明說明： 【發明所屬之技術領域】 ‘ 本發明係關於一種半導體裝置及其製造方法。 ' 【先前技術】 隨著半導體裝置已經被製造為小尺寸，高壓装置之尺寸也已 經逐漸減少。 尤其地，無論尺寸如何，高廢裝置必須完成相同的性能。此 外，需要提供與低壓裝置之製造製程相容之製造方法。 由於驟回（snapback)現象，高壓裝置可能出現崩潰 (Breakdown)現象。 詳細地’如果高壓電晶體之汲極之供應電壓被增加，則電子 從源極向祕移動。因此，位於汲極方向之間隔物之低位部周圍 發生衝擊游離（impactionization)。 當衝擊游離發生時，電洞從位於沒極方向之間隔物之低位部 向基板移動，這樣電流流經基板。因此，從汲極流向源極的電流 量突然增加，導致驟回現象。因而，崩潰電壓（breakd_v麵e ; BV)特性退化。 【發明内容】 貫施例係關於一種半導體裝置及其製造方法。 以例係騎—種具有改良崎電顯性之半導體裝置及其 製造方法。 5 200908327 實施例係關於一種能夠防止出現衝擊游離之半導體裝置及其 製造方法。 一 實施例之半導體裝置包含：第二導電半導縣板、位於、半 導體基板之上的閘電極、形成於閘電極相對侧面之第一導電漂移 區域、形成於第-導電漂移區域之源極區域歧極區域，以= 成於閘電極和汲極區域之_漂移區域中的淺溝隔離區域。位於 淺溝隔離區域之低位部之漂移區域包含摻雜分佈（加細^ ’其中在向下方向雜質濃度減少然後增加並再次減少。 實施例之轉财置之製造綠包含町挪：用第一能量 植入第-導電雜質至第二導電半導體基板内，從而形成第一雜質 區域於第二導電半導縣板巾，料二能量植人第—導電雜質至 第二導電半導縣板内’從㈣成第二雜質區域於第二導電半導 體基板中，透過分別擴散第—㈣二雜域熱處理半導體基板 以形成第-導電漂㈣域’形成閘電極於第二導電轉體基板之 上’透過植人高濃度之第_導電_至漂㈣勒職源極區域 歧極區域於第-導電漂龍財，以及透·擇性職刻開電 極和汲㈣域之間的第—導電漂碰域娜錢溝隔離區域，此 淺溝隔離區域用絕緣材料被填充。 【實施方式】 以下’將結合圖式部份描述半導體褒置及其製造方法。 「第1圖」所示係為實施例之半_裝置之剖視圖 6 200908327 請參考「第1圖」’容納N型雜質之漂移區域2〇形成於 半導體基板10中’容納高濃度Ν型雜質之源極區域3〇或及極^ 域40形成於漂移（drift)區域2〇中。 然後，閘電極50形成於漂移區域20之間。閘電極％包含閘 極絕緣層5卜複晶閘極（gatepoly) 52以及間隔物（叩_) %。 漂移區域20係水平地形成於閘電極5〇下方。漂移區域包 含摻雜分佈，其巾肺的濃度逐漸增加，織從铸縣板1〇的 表面的向下方向降低，再次逐漸增加，然後降低。 淺溝隔離（shallow trenchis〇lati〇n ; STI)區域6〇透過填充絕 緣材料於溝射而形成，淺溝隔離區域6Q係形成於閘電極％: _區域30之間的漂移區域2〇中。此外，相同的淺溝隔離區域 6〇形成於閘電極50和汲極區域4〇之間的漂移區域如中。 漂移區域20減少閘f極50和汲極區域4〇之間的電場密产。 漂移區域20必須具有足夠的寬度，使得漂移區域μ可^加 Μ電極50和錄區域40之間的間隔。然而，因為半導體裳^ 須被製造為小財，Μ極和源歡_電錄辦轉域:被= 少’閘極電壓被增加，漂移區域2〇之寬度必_減少。/ 依照實施例1移區域2G之寬度被減少，淺溝隔離區域 分別形成於漂移區域20中。 淺溝隔離區域60形成於每一漂移區域2 _ T k樣漂移區蛣 之見度可被減少，閘電極5〇和沒極區域4〇之間的電場密度也 200908327 可被降低。 同％ ’安全作業區（safeoperating_ ; s〇A)係為電源裝置 之特性，在閘電極50、源純域3〇卩及半導縣板1()接地的狀 悲下’纽極區域4〇之供應電壓增加時歸電壓制量，在源極 區域30和半‘體基板1〇接地並且作業電壓被供應至間電極％的 狀態下，當汲極區域4〇之供應電壓增力口時，〇n_breakd_v麵e 電1 BVon被測里’安全作業區由測量的崩潰電壓及測量的 on-breakdown電壓被判定。 依移區域2〇之摻齡佈，紐電壓和電壓 導致取舍（trade-off)現象。 依…、貝w列_ 電壓和on_breakd〇wn電壓特性係獨立地被 控制。詳細地，漂移區域2Q之摻雜濃度保持不變，從而令崩潰電 壓特性不變，漂㈣域2G之_分佈概_域⑽如 電壓特性。 「第2圖」所示係為實施例之料體裝置中從淺溝隔離區域 之底部表面向下方向找移區域之摻雜分佈之曲線圖。 如「第2圖」所示，移區域2〇包含推雜分佈，其中從接觸 =溝槽隔離輯6Q之底職面之漂㈣域2q之深度方向，推雜 辰度逐漸降低，然後增加並且再次降低。 依照實_，當形成漂频域2Q時，在___量下， 兩個步驟之师植讀完成。詳域，p料_職電子伏 200908327 特植入能量和18GK電子伏雜人能量被植人，然倾提交至熱處 理製程。 ’ 因此~票移區域20包含如「第2圖」所示之捧雜分佈。 其間，淺溝隔離區域60形成於漂移區域2〇中之半導體裝置 中，最強的電場形成於鄰接汲極區域4〇之淺溝隔離區域之低 位部61中。 在這樣的狀態下，當電壓被供應至没極區域4〇時，電子透過 淺溝隔離區域60之低位部61從源極區域％流向汲極區域4〇。因 此，衝擊游離可能發生在鄰接汲極區域4〇之淺溝隔離區域⑻之 低位部61中。 然而，實施例之半導體裝置中，漂移區域2〇包含如「第2圖」 所示之摻齡佈。因此，從赫隔離區域6()之低位部Μ之深度 方向中’ ％子可透過偏移電子之運動路徑被分配，這樣可 現衝擊游離和驟回現象。 出 「々弟3圖」'「第4圖」、厂第5圖」、「第6圖」、厂第7圖」以 及「第主8 ®」所示係為實_之半導體裝置之製造方法之剖視圖。 /请參考「第3圖」’遮罩層11形成於半導體基板10之上。然 後、=離子透過400K電子伏特至·電子伏特之植入能量被植 入半V體基板1G内，從而形成第—雜質區域21。依照實施例，p 離子^過5GGK電子伏特之植人能倾植人半導體基板1〇内。 請參考「第4圖」’p離子藉由遮罩層11透過1舰電子伏特 200908327 =歷電子伏特之植人能倾植人轉體基板iq内，從而形成 第二雜質區域22。依照實施例，p離子透過勘κ電子伏特之植入 能量被植入半導體基板1〇内。 請參考「第5圖」，漂移驅動製程被完成以清除遮罩層π並 且熱處理半導體基板1()，然後第_和第二雜質區域Μ和22中容 納的雜質被擴散，從而形成漂移區域20。 此時，漂移驅動製程被完成4〇分鐘至5〇分鐘。依照實施例， 漂移驅動製程被完成45分鐘。 請參考「第6圖」’每-漂移區域2〇之部分選擇性地被清除， 然後絕緣機被填統漂祕域W巾，從而形錢溝隔離區域6〇 於漂移區域20中。 °月參考「第7圖」，閘電極50被形成於漂移區域2〇之間，其 中閘電極5G包含閘極絕緣層5卜複晶閘極％以及間隔物53。 "月參考「第8圖」’尚濃度之ρ離子被植入漂移區域2〇内， 從而形成源極區域30或没極區域40於漂移區域2〇中。 「第9圖」所示係為實施例之半導體裝置之〇n_breakd〇wn電 壓特性之曲線圖。 在「第9圖」中，水平軸表示汲極電壓^，垂直軸表示汲極 電流ID。 「第9圖」所示為第一實例和第二實例之對比，第一實例中， 田形成漂移區域20時完成兩個步驟之雜質植入，第二實例中，當 200908327 形成漂^域2G料成―個步驟之雜質植入。 #X 4口步驟之雜質植入之實例中，當閘極電壓VG為32 規如果沒極電愿奶大於38伏特，没極電流突然增加，此 現象被稱為〃驟回現象„。 「第10圖」和「糾 _ 艰 弟11圖」所示係為實施例之半導體裝置之 4驅動製程作為日鋼函數之雜曲線圖。 f 11圖H圖」所不為漂移驅動製程被完成3G分鐘之實例，「第 」不為漂移驅動製程被完成45分鐘之實例。 請參考「第1〇圖 分鐘之實例f η ®」’在隸驅動製程被完成30 樣可能出現通道拥合（“dmg)。現接面船貝，过 输邮物，巾，雖然汲極電 透㈣=伽絲蝴㈣麵在增加接面之後， ::Γ製程而增加崩潰邊限，崩 方法^ 有改良崩潰特性之半_裝置及其製造 方法 貫施例係敎能触止&觸擊游離之半 導體褒置及其製造 具有代表性的 說明書涉及的” 一個實施例，、〃實施例々 貫施例〃等絲結合實關描述之 ' 於本發明之至少—鱗_中。說、結構雜性被包含 胃^同位置出現這樣的詞 200908327 語並非全部指相同的實施例。此外，特別的特點、結構或特㈣ 員之技術範 結合任何實施例被描述時’被認為處於本領域技術人 圍之内，以影響這些實施例特點、結構或特性。 雖然實施例已經結合-系歹4圖示之實施例被描述，但是應該 理解的是，本躺之技術人貞所設相各難他修正及實施例^ 屬於此揭露之原理之精神和範圍之内。尤其地，在本揭露、圖式 以及所附巾請專利之範_，各種更改和修正可能屬於主題組^ 排列之元件部和/或排列中。除了元件部和/或排列之更改和^ 正之外，本領域之技術人員還顯然可看出其他用法。 ^ 【圖式簡單說明】 第1圖所示為實施例之半導體裝置之剖視圖； 第2圖所示為實施例之半導體裝置之漂移區域之摻雜分 曲線圖； 刀布之
視圖； 圖至第8圖所示為實施例之半導體裝置之製造方法立 第9圖所示為實施例之半導體裝置之on_breakdown電壓 之曲線圖；以及 第W圖至第11圖所示為實施例之半_裝置之漂移龌 程作為時間函數之特性曲線圖。 衣 【主要元件符號說明】 10 半導體基板 12 200908327 11 遮罩層 20 漂移區域 21 第一雜質區域 22 第二雜質區域 30 源極區域 40 >及極區域 50 閘電極 51 閘極絕緣層 52 複晶閘極 53 間隔物 60 淺溝隔離區域 61 低位部 13

Claims (1)

  1. 200908327 十、申請專利範圍'* 1. 一種半導體裝置，包含有： 一第二導電半導體基板； 一閘電極，位於該半導體基板之上； 第一導電漂移區域，形成於該閑電極之相對侧面； 一源極區域或—汲極區域，形成於該第-導電漂移區域； 以及 -淺溝隔離區域’形成於_電極和紐極區域之間的該 漂移區域中 其中位於戰栽離區域之_她部之該漂移區域包含 一推雜分佈，其中在一向下方向雜質漢度降低，然後增加，並 且再次降低。 2.如申請專利範圍第1項所述之半導體裝置，其中該雜質包含p 離子。
    3.如申請專祕ffi第1摘述之铸體裝置，其㈣肺水平地 被植入該閘電極下方。 4. -種半導體裝置之S造方法，財法包含以下步驟： 用第一能1植入第一導電雜暂5 —楚-、兹 年书才准貝至一第二導電半導體基板 内’從而形成-第-雜質區域於該第二導電半導體基板中； 用第二能量植人該第—導電雜質至該第二導電半導體基 板内，從而形成-第二雜質區域於該第二導電半導體基板中； 透過分職散該第-和第二雜f區域，熱處職半導體基 14 200908327 板以形成第一導電漂移區域； 形成一閘電掩於該第二導電半導體基板之上； 透過植入尚濃度的該第一導電雜質至該漂移區域内，形成 一源極區域或一汲極區域於該第一導電漂移區域中；以及 透過選擇性地姓亥，】該閘電極和該没極區域之間的兮第 導電漂移區域，形成一淺溝隔離區域，該淺溝隔離區域被絕 材料填充。 5. 如申請專利範圍第4項所述之半導體裝置之製造方法，其中該 第一能1係為400K電子伏特至6〇〇κ電子伏特。 6. 如申請專利範圍第4項所述之半導體裝置之製造方法，其中該 第一能置係為130Κ電子伏特至23〇κ電子伏特。 7. 如申清專利祀圍第4項所述之半導體裝置之製造方法，其中該 熱處理係被完成40分鐘至50分鐘。 八" 8. 如申料利細第4項所述之半導體裝置之製造方法，其中位 於該淺溝隔離區域之一低位部之該漂移區域包含一推雜八 佈，其中雜質濃度在-向下方向降低，然後增加，並轉= 低。 9. 如申請專纖®第4項所叙铸體裝置之製紗法， 雜質包含Ρ離子。 八邊 !0·如申請專利範圍第4項所述之半導體裝置之製造方法，其中該 雜質水平地被植入該閘電極下方。 /
TW097123822A 2007-06-26 2008-06-25 Semiconductor device and manufacturing method thereof TW200908327A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070062630A KR100899764B1 (ko) 2007-06-26 2007-06-26 반도체 소자 및 그 제조방법

Publications (1)

Publication Number Publication Date
TW200908327A true TW200908327A (en) 2009-02-16

Family

ID=40121676

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097123822A TW200908327A (en) 2007-06-26 2008-06-25 Semiconductor device and manufacturing method thereof

Country Status (6)

Country Link
US (1) US20090001485A1 (zh)
JP (1) JP2009010379A (zh)
KR (1) KR100899764B1 (zh)
CN (1) CN101335298B (zh)
DE (1) DE102008029868B4 (zh)
TW (1) TW200908327A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100861213B1 (ko) * 2007-04-17 2008-09-30 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
CN102013427B (zh) * 2009-09-07 2013-03-06 上海宏力半导体制造有限公司 雪崩击穿二极管结构及制造方法
CN102610521B (zh) * 2011-01-19 2014-10-08 上海华虹宏力半导体制造有限公司 非对称高压mos器件的制造方法及结构
US9478456B2 (en) * 2012-03-06 2016-10-25 Freescale Semiconductor, Inc. Semiconductor device with composite drift region
KR102286014B1 (ko) 2015-11-23 2021-08-06 에스케이하이닉스 시스템아이씨 주식회사 개선된 온저항 및 브레이크다운전압을 갖는 고전압 집적소자

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181011B1 (en) * 1998-12-29 2001-01-30 Kawasaki Steel Corporation Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same
US6548874B1 (en) * 1999-10-27 2003-04-15 Texas Instruments Incorporated Higher voltage transistors for sub micron CMOS processes
TW512533B (en) * 2000-04-26 2002-12-01 Sanyo Electric Co Semiconductor device and its manufacturing process
US6768171B2 (en) * 2000-11-27 2004-07-27 Power Integrations, Inc. High-voltage transistor with JFET conduction channels
US6875699B1 (en) * 2001-06-21 2005-04-05 Lam Research Corporation Method for patterning multilevel interconnects
JP5172069B2 (ja) * 2004-04-27 2013-03-27 富士通セミコンダクター株式会社 半導体装置
KR101068139B1 (ko) * 2004-04-30 2011-09-27 매그나칩 반도체 유한회사 Ｌｄｍｏｓｆｅｔ 제조방법
JP5021301B2 (ja) * 2004-08-17 2012-09-05 ローム株式会社 半導体装置およびその製造方法
JP4874736B2 (ja) * 2005-08-11 2012-02-15 株式会社東芝 半導体装置
KR100859486B1 (ko) * 2006-09-18 2008-09-24 동부일렉트로닉스 주식회사 고전압용 정전기 방전 보호 소자 및 그 제조 방법

Also Published As

Publication number Publication date
KR20080113765A (ko) 2008-12-31
US20090001485A1 (en) 2009-01-01
KR100899764B1 (ko) 2009-05-27
JP2009010379A (ja) 2009-01-15
DE102008029868B4 (de) 2010-08-05
CN101335298A (zh) 2008-12-31
CN101335298B (zh) 2012-05-09
DE102008029868A1 (de) 2009-01-15

Similar Documents

Publication Publication Date Title
CN104011871B (zh) 用于超级结型mosfet器件的边缘端接
KR100300069B1 (ko) 반도체 소자 및 그 제조방법
JP5746699B2 (ja) スーパージャンクショントレンチパワーｍｏｓｆｅｔデバイスの製造
US6946705B2 (en) Lateral short-channel DMOS, method of manufacturing the same, and semiconductor device
CN101299438B (zh) 一种半导体结构
CN106571394B (zh) 功率器件及其制造方法
JP2008140817A (ja) 半導体装置
CN105321824B (zh) 半导体装置的制造方法
CN101645459A (zh) 半导体器件及其制造方法
US7888767B2 (en) Structures of high-voltage MOS devices with improved electrical performance
CN101783295B (zh) 一种高压ldmos器件及其制造方法
JP2006165145A (ja) 横型半導体デバイスおよびその製造方法
DE102020004718A1 (de) Siliziumcarbid-grabenleistungsvorrichtung
TW200908327A (en) Semiconductor device and manufacturing method thereof
JP2008199029A (ja) 半導体装置及びその製造方法
JP2006066438A (ja) 半導体装置およびその製造方法
JP2007073942A (ja) 半導体装置
JP5087816B2 (ja) 半導体装置およびその製造方法
JP4725040B2 (ja) Ｓｏｉトレンチ横型ｉｇｂｔ
CN111509044B (zh) 半导体结构及其形成方法
JP2005116651A (ja) 半導体装置及びその製造方法
US7863144B2 (en) Semiconductor device and method for manufacturing the device
KR20130014026A (ko) 핫 캐리어 인젝션의 신뢰성 향상 방법들 및 장치
JP2006140250A (ja) 半導体装置及びその製造方法
CN103295910B (zh) 半导体装置及其制造方法