CN111509044B - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- CN111509044B CN111509044B CN201910097564.4A CN201910097564A CN111509044B CN 111509044 B CN111509044 B CN 111509044B CN 201910097564 A CN201910097564 A CN 201910097564A CN 111509044 B CN111509044 B CN 111509044B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 39
- 150000002500 ions Chemical class 0.000 claims abstract description 106
- 238000002955 isolation Methods 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 18
- 229910044991 metal oxide Inorganic materials 0.000 description 12
- 150000004706 metal oxides Chemical class 0.000 description 12
- 210000000746 body region Anatomy 0.000 description 4
- -1 boron ions Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
一种半导体结构及其形成方法,半导体结构的形成方法包括:提供基底,基底内具有邻接的第一掺杂区和第二掺杂区,第一掺杂区内具有第一掺杂离子,第二掺杂区内具有第二掺杂离子,第二掺杂离子与第一掺杂离子导电类型相反;在第二掺杂区内形成若干个相互分立的第一隔离结构;在相邻第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区,第三掺杂区内具有第三掺杂离子,第三掺杂离子与第二掺杂离子导电类型相反;在部分第一掺杂区、第二掺杂区和第一隔离结构表面形成栅极结构;在栅极结构一侧的第一掺杂区内形成源区;在栅极结构另一侧的第二掺杂区内形成漏区,部分所第一隔离结构位于栅极结构与漏区之间。所形成的器件性能较好。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体结构及其形成方法。
背景技术
横向双扩散金属氧化物半导体晶体管(lateral double diffusion MOS,LDMOS),由于具备高压击穿电压,与互补金属氧化物半导体(CMOS)工艺兼容的特性,被广泛应用于功率器件中。与传统MOS晶体管相比,传统MOS器件中的源极区域和漏极区域相对于栅极对称;而横向双扩散金属氧化物半导体晶体管中的漏极区域比源极更远离栅极,在漏极区域与栅极之间有一个较长的轻掺杂区域,被称为漂移区。横向双扩散金属氧化物半导体晶体管在源漏接高压时,通过漂移区来承受较高的电压降,获得高击穿电压的目的。横向双扩散金属氧化物半导体晶体管除了需要耐高压外,还需要低的开态电阻和高安全工作范围。
然而,现有技术形成的横向双扩散金属氧化物半导体晶体难以同时满足上述性能要求。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法,以提高半导体器件的性能。
为解决上述技术问题,本发明提供一种半导体结构的形成方法,包括:提供基底,所述基底内具有邻接的第一掺杂区和第二掺杂区,所述第一掺杂区内具有第一掺杂离子,所述第二掺杂区内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反;在所述第二掺杂区内形成若干个相互分立的第一隔离结构;在相邻所述第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区,所述第三掺杂区内具有第三掺杂离子,所述第三掺杂离子的导电类型与第二掺杂离子的导电类型相反;在部分所述第一掺杂区、第二掺杂区和第一隔离结构表面形成栅极结构;在栅极结构一侧的第一掺杂区内形成源区;在栅极结构另一侧的第二掺杂区内形成漏区,部分所述第一隔离结构位于栅极结构与漏区之间。
可选的,所述第一隔离结构的形成方法包括:在所述基底、第一掺杂区和第二掺杂区顶部形成第一掩膜层,所述第一掩膜层内具有若干个暴露出第二掺杂区顶部表面的第一掩膜开口;以所述第一掩膜开口为掩膜,刻蚀所述第二掺杂区,在所述第二掺杂区内形成第一隔离开口;在所述第一隔离开口内形成第一隔离结构,所述第一隔离结构充满第一隔离开口。
可选的,所述第一隔离结构的材料包括氧化硅或者氮氧化硅。
可选的,所述漏区上的电压为:500伏特~700伏特。
可选的,沿源区和漏区连线方向上,若干个相互分离的第一隔离结构的尺寸之和为:40微米~50微米;沿源区和漏区连线方向上,所述第一隔离结构的个数为:3个~4个。
可选的,所述第一隔离结构的厚度为:360纳米~400纳米。
可选的,所述第二掺杂离子的掺杂浓度为:2e15原子数/每平方厘米~3e15原子数/每平方厘米。
相应的,本发明还提供一种半导体结构,包括:基底,所述基底内具有邻接的第一掺杂区和第二掺杂区,所述第一掺杂区内具有第一掺杂离子,所述第二掺杂区内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反;位于所述第二掺杂区内的若干个相互分立的第一隔离结构;位于相邻所述第一隔离结构之间以及第一隔离结构底部第二掺杂区内的第三掺杂区,所述第三掺杂区内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反;位于部分所述第一掺杂区、第二掺杂区和第一隔离结构表面的栅极结构;位于所述栅极结构一侧第一掺杂区内的源区;位于所述栅极结构另一侧第二掺杂区内的漏区,部分所述第一隔离结构位于栅极结构与漏区之间。
可选的,所述第一隔离结构的材料包括氧化硅。
可选的,所述漏区上的电压为:500伏特~700伏特。
可选的,沿源区和漏区连线方向上,若干个相互分离的第一隔离结构的尺寸之和为:40微米~50微米;沿源区和漏区连线方向上,所述第一隔离结构的个数为:3个~4个。
可选的,所述第一隔离结构的厚度为:360纳米~400纳米。
可选的,所述第二掺杂离子的掺杂浓度为:2e15原子数/每平方厘米~3e15原子数/每平方厘米。
与现有技术相比,本发明实施例的技术方案具有以下有益效果:
本发明技术方案提供的半导体结构的形成方法中,由于所述第二掺杂区内的第二掺杂离子与第三掺杂区内的第三掺杂离子的导电类型相反,因此,所述第二掺杂区与第三掺杂区构成PN结。尽管所述第二掺杂区内第二掺杂离子的掺杂浓度较高,但是,由于所述第三掺杂区不仅位于第一隔离结构底部,还位于若干相邻第一隔离结构之间,使得所述PN结的耗尽区能够完全耗尽,在所述耗尽区产生电场增强效应,因此,有利于提高器件的击穿电压。同时,由于第二掺杂离子的掺杂浓度较高,使得器件的开启电阻较低。综上,所述方法能够同时提高器件的击穿电压、降低开态电阻。
附图说明
图1是一种横向双扩散金属氧化物半导体晶体管的结构示意图;
图2是另一种横向双扩散金属氧化物半导体晶体管的结构示意图;
图3至图6是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
具体实施方式
正如背景技术所述,横向双扩散金属氧化物半导体晶体管的性能较差。
图1是一种横向双扩散金属氧化物半导体晶体管的结构示意图。
请参考图1,基底100,所述基底100内具有相邻的第一掺杂区101和第二掺杂区102,所述第一掺杂区101内具有第一掺杂离子,所述第二掺杂区102内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反;位于所述第二掺杂区102内的第一隔离结构103;位于所述基底100顶部的栅极结构104,所述栅极结构104覆盖部分第一掺杂区101、第二掺杂区102和第一隔离结构103;位于所述栅极结构104一侧第一掺杂区101内的源区105;位于所述栅极结构104和第一隔离结构103一侧第二掺杂区102内的漏区106。
上述横向双扩散金属氧化物半导体晶体管具有两个重要性能参数,包括击穿电压和开态电阻。当击穿电压较高时,有利于提高器件的可靠性;当所述开态电阻较小时,有利于提高器件的电学性能。因此,性能良好的横向双扩散金属氧化物半导体晶体管具有较高的击穿电压和较低的开态电阻。
目前,提高器件击穿电压的方法有两种,一种方法是:增加第一隔离结构103沿源区105和漏区106连线方向上的尺寸;另一种方法是:降低第二掺杂区102内第二掺杂离子的掺杂浓度。然而,增加第一隔离结构103沿源区105和漏区106连线方向上的尺寸,容易增大器件的开态电阻;降低所述第二掺杂离子的掺杂浓度时,由于所述第二掺杂离子用于提高第二掺杂区102的导电能力,使得第二掺杂区102的电阻较大。相反的,减小第一隔离结构103沿源区105和漏区106连线方向上的尺寸,或者增加第二掺杂区102内第二掺杂离子的掺杂浓度,能够降低态电阻,但是,器件的击穿电压较小。综上,所述方法难以同时提高器件击穿电压和降低开态电阻。
图2是另一种横向双扩散金属氧化物半导体晶体管的结构示意图。图2所示横向双扩散金属氧化物半导体晶体管与图1所示横向双扩散金属氧化物半导体晶体管的不同点仅在于:在所述第一隔离结构103底部的第二掺杂区102内形成第三掺杂区200,所述第三掺杂区200内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反。
上述横向双扩散金属氧化物半导体晶体管中,由于第三掺杂离子与第二掺杂离子的导电类型相反,使得第三掺杂区200与第二掺杂区102之间形成PN结。为了降低开态电阻,增加所述第二掺杂区102内第二掺杂离子的掺杂浓度较高。尽管所述第二掺杂区102内第二掺杂离子的掺杂浓度较高,但是,所述PN结耗尽区能够被完全耗尽,因此,有利于提高击穿电压。
为了进一步降低开态电阻,需进一步增大第二掺杂离子的掺杂浓度。然而,所述第二掺杂离子的掺杂浓度过大,使得第二掺杂区与第三掺杂区形成的PN结耗尽区难以完全耗尽,因此,不利于提高器件的击穿电压。
由此可见,所述第三掺杂区200提高击穿电压、降低开态电阻的能力有限。
为解决所述技术问题,本发明提供了一种半导体结构的形成方法,在所述第二掺杂区内形成若干个相互分立的第一隔离结构;在相邻所述第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区,所述第三掺杂区内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反。所述方法能够同时提高击穿电压、降低开态电阻。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图3至图6是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
请参考图3,提供基底300,所述基底300内具有邻接的第一掺杂区301和第二掺杂区302,所述第一掺杂区301内具有第一掺杂离子,所述第二掺杂区302内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反。
所述基底300的材料包括硅或者硅锗。
所述第一掺杂区301的形成工艺包括第一离子注入工艺;所述第二掺杂区302的形成工艺包括第二离子注入工艺。
在本实施例中,所述第一掺杂离子为P型离子,所述第二掺杂离子为N型离子。所述P型离子包括硼离子,所述N型离子包括磷离子或者砷离子。
所述第二掺杂离子用于降低第二掺杂区302的电阻,所述第二掺杂离子的掺杂浓度为:2e15原子数/每平方厘米~3e15原子数/每平方厘米,所述第二掺杂离子的掺杂浓度较高,因此,有利于降低器件的开态电阻,提高器件的电学性能。
请参考图4,在所述第二掺杂区302内形成若干个相互分立的第一隔离结构304;在相邻所述第一隔离结构304之间以及第一隔离结构304底部的第二掺杂区302内形成第三掺杂区303,所述第三掺杂区303内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反。
所述第一隔离结构304的形成方法包括:在所述基底300、第一掺杂区301和第二掺杂区302顶部形成第一掩膜层(图中未示出),所述第一掩膜层内具有若干个暴露出第二掺杂区302顶部表面的第一掩膜开口(图中未示出);以所述第一掩膜开口为掩膜,刻蚀所述第二掺杂区302,在所述第二掺杂区302内形成第一隔离开口;在所述第一隔离开口内形成第一隔离结构304,所述第一隔离结构304充满第一隔离开口。
所述第一掩膜层的材料包括氮化硅或者氮化钛,所述第一掩膜层用于形成第一隔离开口的掩膜。
以所述第一掩膜开口为掩膜,刻蚀所述第二掺杂区302的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
所述第一隔离结构304的材料包括氧化硅。
所述第三掺杂区303的形成工艺包括:第三离子注入工艺。所述第三掺杂区303内第三掺杂离子的导电类型与第二掺杂离子的导电类型相反。
在本实施例中,所述第三掺杂离子的导电类型为P型,如:硼离子。
由于所述第三掺杂离子与第二掺杂离子的导电类型相反,因此,第三掺杂区303和第二掺杂区302之间形成PN结。所述第三掺杂区303提高击穿电压的同时降低开态电阻的原理包括:由于第三掺杂区303和第二掺杂区302之间形成PN结,尽管所述第二掺杂区302内第二掺杂离子的掺杂浓度较高,但是,由于第三掺杂区303不仅位于第一隔离结构304底部,还位于相邻第一隔离结构304之间,使得第三掺杂区303与第二掺杂区302形成的PN结的耗尽区能够完全耗尽,因此,有利于提高器件的击穿电压。同时,由于第二掺杂离子的掺杂浓度较高,使得器件的开启电阻较低。
后续在第二掺杂区302内形成漏区,在第一掺杂区301内形成源区,后续在漏区上接电压。可以根据所述电压的范围,调节第一隔离结构304沿源区和漏区连线上的尺寸之和以及第一隔离结构304沿源漏连续上的个数。
在本实施例中,所述漏区电压为:500伏特~700伏特,所述第一隔离结构304沿源区和漏区连线方向上的尺寸之和为:40微米~50微米,所述第一隔离结构沿源区和漏区连续上的个数为3个~4个,所述第一隔离结构304用于提高半导体器件的击穿电压。
所述形成方法还包括:在第一掺杂区301和第二掺杂区302内形成第二隔离结构305。
所述第二隔离结构305的材料包括氧化硅。
所述第二隔离结构305用于实现与周围器件之间的电隔离。
请参考图5,在部分所述第一掺杂区301、第二掺杂区302和部分第一隔离结构304表面形成栅极结构306,;在所述栅极结构306一侧的第一掺杂区301内形成源区307;在所述栅极结构306另一侧的第二掺杂区302内形成漏区308。部分所述第一隔离结构304位于栅极结构306与漏区308之间。
所述栅极结构306包括栅介质层(图中未标出)和位于栅介质层顶部的栅极层(图中未标出)。
所述栅介质层的材料包括氧化硅,所述栅极层的材料包括硅。
所述源区307内具有源离子,所述源离子的导电类型与第二掺杂离子的导电类型相同。在本实施例中,所述源离子为N型离子。
所述漏区308内具有漏离子,所述漏离子的导电类型与第二掺杂离子的导电类型相同。在本实施例中,所述漏离子为N型离子。
所述形成方法还包括:在所述栅极结构306一侧的第一掺杂区301内形成体区(图中未标出),所述体区内具有体离子,所述体离子的导电类型与源离子的导电类型相同。
通常在漏区308上接电压。可根据所述电压的大小调节第一隔离结构304沿源区和漏区连线上的尺寸之和以及第一隔离结构304沿源区和漏区连线上的个数,使得器件的击穿电压较大,有利于提高器件的可靠性。
请参考图6,在所述基底300、第一掺杂区301、第二掺杂区302和栅极结构306的侧壁和顶部表面形成介质层309;去除部分介质层309,在所述介质层309内形成若干个互连开口(图中未标出),部分所述互连开口底部暴露出体区,部分所述互连开口底部暴露出源区307顶部,部分所述互连开口底部暴露出漏区308顶部;在所述互连开口内形成互连结构310。
所述介质层309的材料包括氧化硅或者氮氧化硅。
所述介质层309的形成工艺包括化学气相沉积工艺或者物理气相沉积工艺。
所述互连结构310的材料为金属,所述互连结构310用于实现体区、源区307和漏区308与外部电路之间的电连接。
相应的,本发明还提供一种半导体结构,请参考图6,包括:
基底300,所述基底300内具有邻接的第一掺杂区301和第二掺杂区302,所述第一掺杂区301内具有第一掺杂离子,所述第二掺杂区302内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反;
位于所述第二掺杂区302内的若干个相互分立的第一隔离结构304;
位于相邻所述第一隔离结构304之间以及第一隔离结构304底部的第三掺杂区303,所述第三掺杂区303内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反;
位于部分所述第一掺杂区301、第二掺杂区302和第一隔离结构304表面的栅极结构306;
位于所述栅极结构306一侧第一掺杂区301内的源区307;
位于所述栅极结构306另一侧第二掺杂区302内的漏区308,部分所述第一隔离结构304位于漏区308与栅极结构306之间。
所述第一隔离结构304的材料包括氧化硅。
所述漏区308上的电压为:500伏特~700伏特。
沿源区307和漏区308连线方向上,若干个相互分离的第一隔离结构304的尺寸之和为:40微米~50微米;沿源区307和漏区308连线方向上,所述第一隔离结构304的个数为:3个~4个。
所述第一隔离结构304的厚度为:360纳米~400纳米。
所述第二掺杂离子的掺杂浓度为:2e15原子数每平方厘米~3e15原子数/每平方厘米。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (13)
1.一种半导体结构的形成方法,其特征在于,包括:
提供基底,所述基底内具有邻接的第一掺杂区和第二掺杂区,所述第一掺杂区内具有第一掺杂离子,所述第二掺杂区内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反;
在所述第二掺杂区内形成若干个相互分立的第一隔离结构;
在相邻所述第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区,所述第三掺杂区内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反;
在部分所述第一掺杂区、部分第二掺杂区和部分第一隔离结构表面形成栅极结构;
在栅极结构一侧的第一掺杂区内形成源区;
在栅极结构另一侧的第二掺杂区内形成漏区,部分所述第一隔离结构位于栅极结构与漏区之间。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一隔离结构的形成方法包括:在所述基底、第一掺杂区和第二掺杂区顶部形成第一掩膜层,所述第一掩膜层内具有若干个暴露出第二掺杂区顶部表面的第一掩膜开口;以所述第一掩膜开口为掩膜,刻蚀所述第二掺杂区,在所述第二掺杂区内形成第一隔离开口;在所述第一隔离开口内形成第一隔离结构,所述第一隔离结构充满第一隔离开口。
3.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一隔离结构的材料包括氧化硅或者氮氧化硅。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,所述漏区上的电压为:500伏特~700伏特。
5.如权利要求4所述的半导体结构的形成方法,其特征在于,沿源区和漏区连线方向上,若干个相互分离的第一隔离结构的尺寸之和为:40微米~50微米;沿源区和漏区连线方向上,所述第一隔离结构的个数为:3个~4个。
6.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一隔离结构的厚度为:360纳米~400纳米。
7.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第二掺杂离子的掺杂浓度为:2e15原子数/每平方厘米~3e15原子数/每平方厘米。
8.一种半导体结构,其特征在于,包括:
基底,所述基底内具有邻接的第一掺杂区和第二掺杂区,所述第一掺杂区内具有第一掺杂离子,所述第二掺杂区内具有第二掺杂离子,所述第二掺杂离子与第一掺杂离子的导电类型相反;
位于所述第二掺杂区内的若干个相互分立的第一隔离结构;
位于相邻所述第一隔离结构之间以及第一隔离结构底部第二掺杂区内的第三掺杂区,所述第三掺杂区内具有第三掺杂离子,所述第三掺杂离子与第二掺杂离子的导电类型相反;
位于部分所述第一掺杂区、第二掺杂区和部分第一隔离结构表面的栅极结构;
位于所述栅极结构一侧第一掺杂区内的源区;
位于所述栅极结构另一侧第二掺杂区内的漏区,部分所述第一隔离结构位于所述栅极结构与漏区之间。
9.如权利要求8所述的半导体结构,其特征在于,所述第一隔离结构的材料包括氧化硅。
10.如权利要求8所述的半导体结构,其特征在于,所述漏区上的电压为:500伏特~700伏特。
11.如权利要求10所述的半导体结构,其特征在于,沿源区和漏区连线方向上,若干个相互分离的第一隔离结构的尺寸之和为:40微米~50微米;沿源区和漏区连线方向上,所述第一隔离结构的个数为:3个~4个。
12.如权利要求8所述的半导体结构,其特征在于,所述第一隔离结构的厚度为:360纳米~400纳米。
13.如权利要求8所述的半导体结构,其特征在于,所述第二掺杂离子的掺杂浓度为:2e15原子数/每平方厘米~3e15原子数/每平方厘米。
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