200820282 九、發明說明： 【發明所屬之技術領域】 本發明係一種多元晶片型積層電容器及其製造 方法，尤指一種製程簡單、成本低、產品良率高^積 層電容器製造方法者。 门、 【先前技術】 σ按，由於半導體技術的演進，使得半導體構裝的 ，•產品在市場需求提高下，不斷發展出更精密、更先進 =電子元件。以目前的半導體技術而言，比如覆晶構 1的技術、積層基板的設計及被動元件的設計等，均 在半導體產業中，佔有不可或缺的地位。以覆晶"求 格陣列封裝結構為例，晶片係配置於封裝基板的表面 上，並且晶片與封裝基板電性連接，而封 多層圖案化電路層，以及多層絕緣層積集而其^ •圖案化電路層可經由微影蝕刻的方式加以定義而成 、’而，層配置於相鄰二圖案化電路層之間。此外， ^得到更佳的電氣純，封裝基板之表面上還配置 有電容、電感以及電阻等被動元件，其可藉由封裝基 反之内部線路，而電性連接於晶片以及其他電子元件 备產ί!:元件之設計上’由於晶片在高速運算下， 【 同尤、，且晶片所產生之熱能會傳至封裝基板 再傳至被動元件上。為了使被動元件即使在高溫 5 200820282 的環境下’也不會影響其電氣特性，因此必須設計具 有耐高溫以及高穩定性的被動元件，而微小型積層電 容器即是其中一例。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip type multilayer capacitor and a method of manufacturing the same, and more particularly to a method for manufacturing a multilayer capacitor, which is simple in process, low in cost, and high in product yield. Door, [previous technology] σ press, due to the evolution of semiconductor technology, the semiconductor components, and products in the market demand, continue to develop more sophisticated, more advanced = electronic components. In the current semiconductor technology, technologies such as flip-chip 1, laminated substrate design, and passive component design all play an indispensable role in the semiconductor industry. For example, in the case of a flip chip array structure, the wafer is disposed on the surface of the package substrate, and the wafer is electrically connected to the package substrate, and the patterned circuit layer is sealed, and the plurality of insulating layers are accumulated. The patterned circuit layer can be defined by lithographic etching, and the layers are disposed between adjacent two patterned circuit layers. In addition, ^ is better electrical purity, the surface of the package substrate is also equipped with passive components such as capacitors, inductors and resistors, which can be electrically connected to the chip and other electronic components by the package and vice versa. !: The design of the component 'Because the wafer is under high-speed operation, the thermal energy generated by the wafer is transferred to the package substrate and then transmitted to the passive component. In order to make the passive components do not affect their electrical characteristics even in the high temperature environment of 200820282, it is necessary to design passive components with high temperature resistance and high stability, and a micro-layered laminated capacitor is one of them.
一般習知之微小型積層電容器，主要係由多層介 電層與多層金屬層堆疊而成，其中，介電層係由高介 電常數之材質，如：鋇鈦酸鹽所組成，而金屬層係由 如：銀、銀鈀合金之導電材質所組成，且多層金屬層 形成多個陽、陰極交替之内電極（Intern^ electrode)，而内電極與介電層係構成一電容结構， 其兩側還配置有一對終端電才亟’㈣電性連接陽、陰 極之内電極，形成陽極及陰極，且該等陽極及陰極表 面可形成一表面金屬層，如：鎳，以防止氧化。" 習見之微小型積層t纟器雖可因自多層介電芦 與多層金屬層堆疊構成，而體積可微小型二 隹用範圍。但是，其製程複雜，成本高，短路“多運 =造過程及組裝困難。再者，美國第⑽⑽似號 干，^ 日日月電谷為7,請芩閱第1圖所 =顯示該專利之圖示，該電容器係由陽斤 間隔離-隔離層3所構成，其中陽 j 4， 乂》極2與陽極1之間則*導電高 而隔離層3隔絕陰極2與陽極i構成 ：： Η。然而’電容器欲增加其電容值係以並聯連接； 6 200820282 二=電容器堆疊並令該等電容器之電容值相 二=數:電容值相加後之較大的電容值（如第2 圖所不）’並料4後之銘晶片電容器7進行封裝 從陽極1與陰極端分則出導腳2卜形成完 晶片電容器7匕： 以治具17壓著及上銀膠 =雜（增加 ::多’且容易於封裝時產生熱:力二 國！ _227號專利亦揭示電容不同之堆 二：：：閱第4a、4b、4c圖所示，其顯示該專 方Γ:Γ 同堆疊方式’然而，不論何種堆疊 方式’亦如上述美國第US6249424號專利，益法 服電谷裔容易損壞、製程複雜、成本高、短路 之缺^因此’如何能開發設計出—種多元晶片 層電容器，將是相關業界亟待努力之課題。 貝 【發明内容】 發明人有鑑於前述先前技街之缺點，乃 各種電容器之製造經驗和技術累積，針對上述缺= 心研究各種解決的方法’在經過不斷的研究㈣ 改良後，終於開發輯出本發明之—種全 =/、 型積層電容器及其製造方法的發明，= 技術所產生之缺失。 于、％則 因此本發明即旨在提供一種多元晶片型積層電 7 200820282 容器及其製造方法，依本發明之此種電容器，其製造 過程中，能簡化製程，大幅降低成本，組裝容易，提 高產品良率，以改善習見之電容器的缺失，此為本發 明之主要目的。 Λ 為便貴審查委員能對本發明之目的、形狀、構 造裝置特徵及其功效，做更進一步之認識與瞭解，茲 舉實施例配合圖式，詳細說明如下： 【實施方式】 本發明之此種「多元晶片型積層電容器及其製造 方法」，乃如第5至11圖所示，必需先予陳明者，為了 說明上的清楚起見，第5至〇圖均係實物放大了數十 倍之多。本發明之電容器1係依以下步驟製成： (A )首先，將不同的金屬薄片基板jj 2沖壓 出複數個分離並以延伸部13止於基板而形成相連之 陽極片 Π1、112、113…及陰極片 121、122、123,..， 如此，陽極片111、112、113與金屬薄片基板^間乃 以一延伸部13連接，陰極片121、122、123···與金屬 薄片基板12間亦以一陰極片之延伸片13連接，並於一 多細孔性之隔離薄板14上沖壓出陰、陽極片m、U2 、113…、121、122、123…對應而較陰、陽極片小之 開孔14卜作為陰、陽極片in、n2、i13 、m、 122、123…之間的隔離層142 (如第5圖所示）； (B )接著，若有必要，依檢驗的結果，對陽極 8 200820282 片in、112、113,,,與陰極片12i、122、123…進行整 修（修除毛邊）（如第6圖所示）；再將陽極片Π1、Π2 、113…、陰極片121、122、123…及隔離層142依照 順序相互堆疊及壓合，而形成陽、陰極片n丨、i 12 、113…、121、122、123…之間夾置著隔離層142的 積層結構15 (如第7圖所示）； 一 （C)之後，若有必要，可視隔離層ι42材料之 ，響性質’施以碳化之製程（如第8圖所示）；再將該積層 結構15浸潰於電解質溶液槽16中，以吸收電解質（如 第9圖所示）； (D)如果所浸潰的為高分子電解質溶液，則在 高溫下，予以熱聚合，使陽極片111、112、113··,與 陰極片121、122、123…之間之隔離層142所吸附的電 解貝/谷液，成為導電性高分子聚合物固態電解質層（ 如第10圖所示）； 鲁 （Ε)最後，將此積層結構15進行裁切，使形成 陽極片 111 ' 112、113···、陰極片 121、122、123 與 隔離層142所組成之積層電容器結構17， 保留-與陽極片⑴、„2、113相連接之陽極=；； ，以及一與陰極片121、122、123…相連接之陰極導 片13,作為外部電氣連接使用之外部電極，嗣再於該 積層電谷益結構17上封裝一作為保護外層之覆蓋声 m ’即獲得單元晶片型積層電容器j(如第Ua圖與 9 200820282 弟11b圖所示）。 復请參閱第lib與11c圖所示，上述積層電容哭1 引出之陽極導片13、陰極導片13可視實際使用之需求 ，將該等陽極導片13、陰極導片13彎折至與覆蓋層171 表面貼合，以便於表面黏著（SMT )方式之連結。 上述隔離層142亦可用塗佈可溶性之導電性高分 子溶液等方式，使其吸附導電性高分子單量體等固態 電解質。而本發明之積層電容器，其陽極片1U、 、⑴…與陰極片121、122、123...之間的隔離層142 ’較佳的係為具有碳素纖維（簡稱碳纖） 紙所構成者。 請參閱第12圖所示，本發明積層電容 f:可將複數片陽極片⑴、Π2、113...、複數二 咖及複數片隔離層142依照覆3 (cover )162、碳 - ^ ^rbon fiber 152 . ^ 片、隔離芦卜層、陽極片、隔離層、陰極 二公離層陰極片、隔離層、纖維帶、覆蓋居之 順序相互堆疊及懕人、， 復盈續之 1U相、二 並引出與陽極片⑴、⑴、 ，…相連==片導：以及-與陰極片12ί， 成多元晶片型㈣作為外部電極，即形 此處，需陳明的是 之單元者，為陽極片、個晶片型積層電容器 Θ隔離層、以及陰極片，其中， 200820282 :極片較佳的為鋁箔；隔離層較佳的可以 布纖維、碳化紙、碳纖* 為、、，氏不織 維尊.险托μ 0成緘維布、碳纖與紙質纖 、：，丢木片之材料則可為金屬箔、；^ , M A s A/_ 亦即，金眉其H爲陆 破覆的金屬箔（ 材質可與被覆層相同或不同，被霜…：屬基片之 、主 4々个Ν被覆層可利用喷濺、浸 續、電鍍或其他被覆方法形成於基片之、至Generally, a micro-sized multilayer capacitor is mainly composed of a multilayer dielectric layer and a plurality of metal layers, wherein the dielectric layer is composed of a material having a high dielectric constant, such as barium titanate, and the metal layer is It is composed of a conductive material such as silver or silver-palladium alloy, and the multi-layer metal layer forms a plurality of inner and outer electrodes (alternating electrodes), and the inner electrode and the dielectric layer form a capacitor structure, and both sides thereof A pair of terminals is also configured to electrically connect the inner electrodes of the anode and the cathode to form an anode and a cathode, and the anode and cathode surfaces may form a surface metal layer such as nickel to prevent oxidation. " The micro-small layered t-sigma of Xi's can be composed of a multi-layer dielectric reed and a multi-layer metal layer, and the volume can be used in a small size. However, the process is complicated, the cost is high, and the short circuit "multiple transport = manufacturing process and assembly difficulty. Moreover, the United States (10) (10) seems to be dry, ^ the sun and the moon valley is 7, please refer to Figure 1 = show the patent In the figure, the capacitor is composed of the isolation and isolation layer 3, wherein the anode 4 and the anode 1 are electrically conductive and the isolation layer 3 is insulated from the cathode 2 and the anode i: Η. However, 'capacitors want to increase their capacitance values in parallel connection; 6 200820282 two = capacitor stacking and make the capacitance value of these capacitors two = number: the larger the capacitance value after the capacitance values are added (as shown in Figure 2) No) After the 4th chip, the chip capacitor 7 is packaged from the anode 1 and the cathode end, and the lead pin 2 is formed. The wafer capacitor 7 is formed: the jig 17 is pressed and the silver paste is mixed (added: : Many 'and easy to generate heat when encapsulating: force two countries! _227 patent also reveals a different stack of capacitors two::: see pictures 4a, 4b, 4c, which shows the special Γ: Γ same stacking 'However, regardless of the stacking method' is also the above-mentioned US Patent No. 6,294,424, It is easy to damage, complicated in process, high in cost, and short of short circuit. Therefore, 'how to develop and design a multi-layer wafer capacitor will be an urgent task for the industry.” [Inventor] In view of the aforementioned prior art street Disadvantages are the manufacturing experience and technical accumulation of various capacitors, and the methods for solving various solutions to the above-mentioned problems are improved. After continuous research (4) improvement, the full-size / / type multilayer capacitors of the present invention are finally developed. Invention of the manufacturing method, = the absence of technology. The present invention is therefore intended to provide a multi-wafer type laminated electric power 7 200820282 container and a method of manufacturing the same, in the manufacturing process of the capacitor according to the present invention, The main purpose of the present invention is to simplify the process, greatly reduce the cost, ease the assembly, improve the product yield, and improve the lack of capacitors of the present invention. Λ For the purpose of the present invention, the purpose, shape, and structure of the device can be Its efficacy, to make a further understanding and understanding, the implementation of the example with the diagram, detailed description [Embodiment] The "multi-chip type multilayer capacitor and the method of manufacturing the same" of the present invention are as shown in Figures 5 to 11, and must be clearly stated. For the sake of clarity, the fifth to The stencils are magnified dozens of times. The capacitor 1 of the present invention is made in the following steps: (A) First, different metal foil substrates jj 2 are punched out by a plurality of separations and terminated by extensions 13 The substrate is formed to form connected anode sheets 1121, 112, 113... and cathode sheets 121, 122, 123, . . . , so that the anode sheets 111, 112, 113 and the foil substrate are connected by an extension portion 13, the cathode sheet 121, 122, 123··· is also connected with the extension piece 13 of the cathode piece with the metal foil substrate 12, and punches the anode and cathode sheets m, U2, 113, ... on a multi-porous isolating thin plate 14. 121, 122, 123... corresponding to the opening of the cathode and anode sheets 14 as the isolation layer 142 between the anode and cathode sheets in, n2, i13, m, 122, 123... (as shown in Fig. 5) (B) Next, if necessary, according to the results of the test, for the anode 8 200820282 pieces in, 112, 113,,, and The cathode sheets 12i, 122, 123... are subjected to refurbishment (removing the burrs) (as shown in Fig. 6); and the anode sheets Π1, Π2, 113..., the cathode sheets 121, 122, 123, ... and the spacer layer 142 are mutually ordered in order Stacking and pressing to form a laminated structure 15 in which the isolation layer 142 is interposed between the anode and cathode sheets n丨, i 12 , 113..., 121, 122, 123, ... (as shown in Fig. 7); After that, if necessary, the material of the spacer layer ι42 can be visualized, and the process of carbonization is applied (as shown in Fig. 8); the layered structure 15 is then immersed in the electrolyte solution tank 16 to absorb the electrolyte ( (Fig. 9); (D) If the polymer electrolyte solution is impregnated, it is thermally polymerized at a high temperature to cause the anode sheets 111, 112, 113··, and the cathode sheets 121, 122, 123. The electrolytic shell/valley solution adsorbed by the separation layer 142 between the ... becomes a conductive polymer polymer solid electrolyte layer (as shown in Fig. 10); Lu (Ε) Finally, the laminated structure 15 is cut, The product of the anode sheets 111' 112, 113···, the cathode sheets 121, 122, 123 and the separator 142 is formed. The layer capacitor structure 17, retaining - an anode connected to the anode sheets (1), „2, 113=;; and a cathode lead 13 connected to the cathode sheets 121, 122, 123... as an external electrical connection The electrode, and then encapsulating a cover film m' as a protective outer layer on the laminated electric grid structure 17, obtains a cell wafer type multilayer capacitor j (as shown in FIG. Ua and FIG. 9 200820282). Referring to the figures lib and 11c, the anode guide 13 and the cathode guide 13 of the above-mentioned laminated capacitor crying 1 can be bent and covered by the anode guide 13 and the cathode guide 13 according to the actual use requirements. Layer 171 is surface-fitted to facilitate surface mount (SMT) bonding. The separator 142 may be coated with a soluble conductive polymer solution or the like to adsorb a solid electrolyte such as a conductive polymer. In the multilayer capacitor of the present invention, the spacer layer 142' between the anode sheets 1U, (1), ... and the cathode sheets 121, 122, 123, ... is preferably composed of carbon fiber (carbon fiber for short). . Referring to FIG. 12, the laminated capacitor f of the present invention can: a plurality of anode sheets (1), Π2, 113..., a plurality of dicans, and a plurality of isolation layers 142 according to a cover 3 (cover) 162, carbon-^ ^rbon fiber 152 . ^ Sheet, isolation layer, anode sheet, separator, cathode two-ion cathode sheet, separator layer, fiber belt, covering the order of stacking each other and smashing, 1U phase And the second lead is connected to the anode sheets (1), (1), ..., == sheet guide: and - and the cathode sheet 12ί, into a multi-wafer type (4) as an external electrode, that is, the shape here, the unit to be clearly stated is An anode sheet, a wafer type multilayer capacitor, an isolating layer, and a cathode sheet, wherein, 200820282: the pole piece is preferably an aluminum foil; the separator layer is preferably made of fiber, carbonized paper, carbon fiber*, and Respect. Risky μ 0 into 缄 缄 、, carbon fiber and paper fiber,:, the material of the wood chip can be metal foil, ^, MA s A / _ that is, the gold eyebrow H is the land broken metal foil (The material can be the same or different from the coating layer, and it is frosted...: It is a substrate, and the main 4 Ν coating can be sprayed. Splashing, immersion, plating or other coating methods are formed on the substrate to
c通過隔離層者，其可為液態電解質，、； V电性4合物固態電解質之單體。 一在本發明中，請參閱第13&、13卜13(:、13(1圖所 不，本發明之積層電容器〗可視使用之需求於其三侧 =引出三個電極導片（二個陽極導片13a、—個陰極 =片13b或一個陽極導片13a、二個陰極導片如 第13a圖所示）；或於其四側面分別引出四個電極導片 (二個陽極導片13a、二個陰極導片Ub)(如第 圖所示）；或於其二相鄰冬側面分別引出陽極導片13a 、陰極導片13b (如第13c圖所示）；或於任一側面引 出陽極導片13a、陰極導片Ub (如第Uci圖所示）。 請參閱第14圖所示，本發明之另一實施例中，陽 極片 111、112、113···、陰極片 m、122、123···及隔 離層142之相互堆疊及壓合方式，可以前後堆疊、壓 合方式進行，使作為陰極之導片1%及作為陽極之導 片13a分別位於積層結構15之前、後端，再將該積層 結構15浸潰於電解質溶液槽16中，以吸收電解質；然 11 200820282 後，在高溫下，予以熱聚合，使陽極片U1、112、113… 與陰極片121、122、123...之間之隔離層142所吸附的 電解質溶液，成為導電性高分子聚合物固態電解質層 ，最後，將此積層結構15進行裁切，使形成陽極片丄j i 、112、113…、陰極片 121、122、123.·.與隔離層 142 所組成之積層電容器結構17，並於裁切時保留一與陽 極片111、112、113…相連接之陽極導片13，以及一 鲁與陰極片121、I22、m…相連接之陰極導片13，作 為外部電氣連接使用（外部電極），嗣再於該積層電 ，器結構17上封裝一作為保護外層之絕緣塑膠層（覆 蓋層）162，並將作為電極之陰極導片13、陽極導片 13彎曲貼合於絕緣塑膠層（覆蓋層）162表面上，即 形成多元晶片型積層電容器1。 綜合上所述，本發明之多元晶片型積層電容器及 其製造方法，確實具有前所未有之功能與結構，盆既 鲁未見於任何刊物，且市面上亦未見有任何類似的產品 ’是以，其具有新穎性應無疑慮。另外，本發明所具 有之獨特特徵以及功能遠非習用所可比擬，所以其確 實比習用更具有其進步性，而符合我國專利法有關發 明專利之申請要件之規定，乃依法提起專利申請。 以上所述，僅為本發明最佳具體實施例，惟本發 明之構造特徵並不揭限於此，任何熟悉該項技蓺者丄 本發明領域内’可輕易思及之變化或修飾，皆；涵蓋 12 200820282 在以下本案之專利範圍。c through the separator, which may be a liquid electrolyte, a monomer of a V-electrolyte solid electrolyte. In the present invention, please refer to the 13th & 13b 13 (:, 13 (1, the multilayer capacitor of the present invention) can be used on the three sides of the visible use of the present invention = three electrode guides (two anodes) a guide piece 13a, a cathode=sheet 13b or an anode guide 13a, two cathode guides as shown in FIG. 13a; or four electrode guides (two anode guides 13a, respectively) on four sides thereof Two cathode guides Ub) (as shown in the figure); or an anode guide 13a and a cathode guide 13b (as shown in Fig. 13c) on the two adjacent winter sides; or an anode on either side The guide piece 13a and the cathode guide piece Ub (as shown in Fig. Uci). Referring to Fig. 14, in another embodiment of the present invention, the anode sheets 111, 112, 113, ..., the cathode sheets m, 122 The stacking and pressing manner of the 123··· and the isolation layer 142 can be performed by stacking and pressing in a front-rear manner, so that the guide piece 1% as the cathode and the guide piece 13a as the anode are respectively located before and behind the laminated structure 15 . Then, the laminated structure 15 is immersed in the electrolyte solution tank 16 to absorb the electrolyte; after 11 200820282, At a temperature, thermal polymerization is carried out to make the electrolyte solution adsorbed by the separator 142 between the anode sheets U1, 112, 113... and the cathode sheets 121, 122, 123... into a conductive polymer polymer solid electrolyte layer. Finally, the laminated structure 15 is cut so as to form the laminated capacitor structure 17 composed of the anode sheets 丄ji, 112, 113, ..., the cathode sheets 121, 122, 123, and the isolation layer 142, and is cut at the time of cutting. An anode guide 13 connected to the anode sheets 111, 112, 113... and a cathode guide 13 connected to the cathode sheets 121, I22, m are retained as external electrical connections (external electrodes), Further, an insulating plastic layer (cover layer) 162 as a protective outer layer is encapsulated on the laminated structure, and the cathode guiding piece 13 and the anode guiding piece 13 as electrodes are bent and attached to the insulating plastic layer (cover layer). On the surface of 162, a multi-wafer type multilayer capacitor 1 is formed. As described above, the multi-chip type multilayer capacitor of the present invention and the method of manufacturing the same have an unprecedented function and structure, and the pot is not found in any publication, and There is no similar product on the market. Yes, its novelty should be undoubted. In addition, the unique features and functions of the present invention are far from comparable, so it is indeed more progressive than its use. In accordance with the requirements of the application requirements of the invention patents of the Chinese Patent Law, the patent application is filed according to law. The above description is only the best embodiment of the present invention, but the structural features of the present invention are not limited thereto, and any one is familiar with the The skilled artisan is susceptible to variations or modifications in the field of the invention; covers 12 200820282 in the scope of the patents herein below.
13 200820282 【圖式簡單說明】 第1至4圖為習用電容器之剖面示意圖。 第5至11圖為本發明電容器之製造過程示意 圖。 第12至14圖為本發明電容器其他實施例之示 意圖。 【主要元件符號說明】 II、 12 :金屬薄片 III、 112、113···:陽極片 121、122、123···:陰極片 13 :陽極片延伸部 13 :陰極片延伸部 14 ·隔離薄板 141 ··開孔 142 :隔離層 15 :積層結構 16 :電解質溶液槽 17 :積層電容器結構 152 :纖維帶 162 :覆蓋層 1413 200820282 [Simple description of the diagram] Figures 1 to 4 are schematic cross-sectional views of conventional capacitors. Figures 5 through 11 are schematic views of the manufacturing process of the capacitor of the present invention. Figures 12 through 14 are schematic views of other embodiments of the capacitor of the present invention. [Description of main component symbols] II, 12: Metal foils III, 112, 113·:: anode sheets 121, 122, 123:: cathode sheet 13: anode sheet extension 13: cathode sheet extension 14 • separator sheet 141 ·· Opening 142 : Isolation layer 15 : Laminated structure 16 : Electrolyte solution tank 17 : Multilayer capacitor structure 152 : Fiber ribbon 162 : Cover layer 14