TW200707699A - Sip type package containing analog semiconductor chip and digital semiconductor chip stacked in order, and method for manufacturing the same - Google Patents
Sip type package containing analog semiconductor chip and digital semiconductor chip stacked in order, and method for manufacturing the sameInfo
- Publication number
- TW200707699A TW200707699A TW095116427A TW95116427A TW200707699A TW 200707699 A TW200707699 A TW 200707699A TW 095116427 A TW095116427 A TW 095116427A TW 95116427 A TW95116427 A TW 95116427A TW 200707699 A TW200707699 A TW 200707699A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor chip
- manufacturing
- order
- same
- package containing
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2225/06503—Stacked arrangements of devices
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
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- H01L2924/30107—Inductance
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Semiconductor Integrated Circuits (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005147831A JP4408832B2 (ja) | 2005-05-20 | 2005-05-20 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
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TW200707699A true TW200707699A (en) | 2007-02-16 |
Family
ID=36968879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW095116427A TW200707699A (en) | 2005-05-20 | 2006-05-09 | Sip type package containing analog semiconductor chip and digital semiconductor chip stacked in order, and method for manufacturing the same |
Country Status (6)
Country | Link |
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US (1) | US20060261471A1 (zh) |
EP (1) | EP1724833A2 (zh) |
JP (1) | JP4408832B2 (zh) |
KR (1) | KR100744979B1 (zh) |
CN (1) | CN1866515A (zh) |
TW (1) | TW200707699A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9269674B2 (en) | 2014-06-17 | 2016-02-23 | Realtek Semiconductor Corporation | Integrated circuit having electromagnetic shielding capability and manufacturing method thereof |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4408832B2 (ja) * | 2005-05-20 | 2010-02-03 | Necエレクトロニクス株式会社 | 半導体装置 |
KR100764682B1 (ko) * | 2006-02-14 | 2007-10-08 | 인티그런트 테크놀로지즈(주) | 집적회로 칩 및 패키지. |
DE102006033175A1 (de) * | 2006-07-18 | 2008-01-24 | Robert Bosch Gmbh | Elektronikanordnung |
CN101150123B (zh) * | 2007-10-31 | 2010-06-02 | 日月光半导体制造股份有限公司 | 具有电磁屏蔽罩盖的半导体封装结构 |
US20110193243A1 (en) * | 2010-02-10 | 2011-08-11 | Qualcomm Incorporated | Unique Package Structure |
CN101908082B (zh) * | 2010-04-30 | 2012-10-24 | 梅州市志浩电子科技有限公司 | 印刷电路板的阻抗设计方法及阻抗设计装置 |
JP5924110B2 (ja) * | 2012-05-11 | 2016-05-25 | 株式会社ソシオネクスト | 半導体装置、半導体装置モジュールおよび半導体装置の製造方法 |
CN103969572B (zh) * | 2013-02-05 | 2017-05-17 | 泰斗微电子科技有限公司 | 一种sip芯片测试平台和方法 |
CN103441124B (zh) * | 2013-08-27 | 2016-01-06 | 矽力杰半导体技术(杭州)有限公司 | 电压调节器的叠层封装方法及相应的叠层封装装置 |
WO2015037390A1 (ja) * | 2013-09-10 | 2015-03-19 | 株式会社村田製作所 | センサモジュール |
KR20160036945A (ko) * | 2014-09-26 | 2016-04-05 | 삼성전기주식회사 | 인쇄회로기판 및 이를 포함하는 전자부품 패키지 |
WO2016154438A1 (en) * | 2015-03-26 | 2016-09-29 | Life Technologies Corporation | Method for treating a semiconductor sensor array device |
JP2018032680A (ja) * | 2016-08-23 | 2018-03-01 | 日本電信電話株式会社 | 積層集積回路 |
CN106324484B (zh) * | 2016-08-30 | 2019-04-02 | 福州瑞芯微电子股份有限公司 | 芯片的无线调试电路和方法 |
CN106324485B (zh) * | 2016-08-30 | 2019-04-02 | 福州瑞芯微电子股份有限公司 | 芯片的无线测试电路及无线测试方法 |
CN106374962B (zh) * | 2016-08-30 | 2019-03-12 | 福州瑞芯微电子股份有限公司 | 一体化wifi芯片及其封装方法 |
CN106361303A (zh) * | 2016-08-30 | 2017-02-01 | 福州瑞芯微电子股份有限公司 | 血管检测一体化芯片及其实现方法 |
US10332820B2 (en) * | 2017-03-20 | 2019-06-25 | Akash Systems, Inc. | Satellite communication transmitter with improved thermal management |
US10374553B2 (en) * | 2017-06-15 | 2019-08-06 | Akash Systems, Inc. | Microwave transmitter with improved information throughput |
US10680633B1 (en) * | 2018-12-21 | 2020-06-09 | Analog Devices International Unlimited Compnay | Data acquisition system-in-package |
US20210055255A1 (en) * | 2019-08-21 | 2021-02-25 | Life Technologies Corporation | Devices incorporating multilane flow cell |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399898A (en) * | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
US5198693A (en) * | 1992-02-05 | 1993-03-30 | International Business Machines Corporation | Aperture formation in aluminum circuit card for enhanced thermal dissipation |
US5285352A (en) * | 1992-07-15 | 1994-02-08 | Motorola, Inc. | Pad array semiconductor device with thermal conductor and process for making the same |
US5642261A (en) * | 1993-12-20 | 1997-06-24 | Sgs-Thomson Microelectronics, Inc. | Ball-grid-array integrated circuit package with solder-connected thermal conductor |
US5858814A (en) * | 1996-07-17 | 1999-01-12 | Lucent Technologies Inc. | Hybrid chip and method therefor |
US6381283B1 (en) * | 1998-10-07 | 2002-04-30 | Controlnet, Inc. | Integrated socket with chip carrier |
JP2000323617A (ja) * | 1999-05-12 | 2000-11-24 | Mitsubishi Electric Corp | 高周波用半導体パッケージ |
JP2001035994A (ja) * | 1999-07-15 | 2001-02-09 | Toshiba Corp | 半導体集積回路装置およびシステム基板 |
US6261869B1 (en) * | 1999-07-30 | 2001-07-17 | Hewlett-Packard Company | Hybrid BGA and QFP chip package assembly and process for same |
US6531784B1 (en) * | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
JP3417388B2 (ja) * | 2000-07-19 | 2003-06-16 | 松下電器産業株式会社 | 半導体装置 |
KR100391093B1 (ko) * | 2001-01-04 | 2003-07-12 | 삼성전자주식회사 | 히트 싱크가 부착된 볼 그리드 어레이 패키지 |
US6586825B1 (en) * | 2001-04-26 | 2003-07-01 | Lsi Logic Corporation | Dual chip in package with a wire bonded die mounted to a substrate |
US6867500B2 (en) * | 2002-04-08 | 2005-03-15 | Micron Technology, Inc. | Multi-chip module and methods |
JP2004111656A (ja) * | 2002-09-18 | 2004-04-08 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US7479407B2 (en) * | 2002-11-22 | 2009-01-20 | Freescale Semiconductor, Inc. | Digital and RF system and method therefor |
JP2004214249A (ja) * | 2002-12-27 | 2004-07-29 | Renesas Technology Corp | 半導体モジュール |
TWI317549B (en) * | 2003-03-21 | 2009-11-21 | Advanced Semiconductor Eng | Multi-chips stacked package |
JP2004296719A (ja) * | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | 半導体装置 |
TWI278947B (en) * | 2004-01-13 | 2007-04-11 | Samsung Electronics Co Ltd | A multi-chip package, a semiconductor device used therein and manufacturing method thereof |
US7235889B2 (en) * | 2004-09-10 | 2007-06-26 | Lsi Corporation | Integrated heatspreader for use in wire bonded ball grid array semiconductor packages |
JP4748648B2 (ja) * | 2005-03-31 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4408832B2 (ja) * | 2005-05-20 | 2010-02-03 | Necエレクトロニクス株式会社 | 半導体装置 |
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2005
- 2005-05-20 JP JP2005147831A patent/JP4408832B2/ja not_active Expired - Fee Related
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2006
- 2006-05-09 TW TW095116427A patent/TW200707699A/zh unknown
- 2006-05-12 US US11/432,528 patent/US20060261471A1/en not_active Abandoned
- 2006-05-18 EP EP06010256A patent/EP1724833A2/en not_active Withdrawn
- 2006-05-18 KR KR1020060044762A patent/KR100744979B1/ko active IP Right Grant
- 2006-05-22 CN CNA2006100848891A patent/CN1866515A/zh active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9269674B2 (en) | 2014-06-17 | 2016-02-23 | Realtek Semiconductor Corporation | Integrated circuit having electromagnetic shielding capability and manufacturing method thereof |
TWI553817B (zh) * | 2014-06-17 | 2016-10-11 | 瑞昱半導體股份有限公司 | 具有電磁防護功能之積體電路及其製造方法 |
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EP1724833A2 (en) | 2006-11-22 |
JP4408832B2 (ja) | 2010-02-03 |
KR20060120462A (ko) | 2006-11-27 |
CN1866515A (zh) | 2006-11-22 |
US20060261471A1 (en) | 2006-11-23 |
JP2006324563A (ja) | 2006-11-30 |
KR100744979B1 (ko) | 2007-08-02 |
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