TW200418100A - Metal layer planarization method for preventing pattern density effect - Google Patents

Abstract

A metal layer planarization method for preventing pattern density effect comprises the following steps: firstly, providing a semiconductor substrate having a trench area with relatively high pattern density and a trench area with relatively low pattern density; forming a metal layer on the semiconductor substrate to fill up the aforementioned trench areas; using a first planarization method to remove a portion of the metal layer; then, using a second planarization method to remove the residual metal layer on the semiconductor substrate until the surface of the semiconductor substrate is exposed, in which the second planarization method has essentially the same removal rate for the metal layer at the top of the trench area with relatively high pattern density and for the metal layer at the top of the trench area with relatively low pattern density.

Description

200418100 五、發明說明（l) 發明所屬之技術領域 本發明係有關於一種金屬層平坦化方法，特別是有關於— 一種可避免圖案密度效應（pattern density effect)的電解 拋光金屬層方法。 〜 先前技術 在積體電路的技術上’為了提南元件的積集度以及資料 傳輸速度’製程技術已由次微米（s u b - m i c r 0 n )進入了四分 之一微米（quarter-micron)甚或更細微尺寸的範圍。然 而 ^線見愈末愈小’铭導線已無法滿足對速度的要求， 此’以具有高導電性之金屬銅做為導線，以降低延遲（rc delay)，係為目前的趨勢。 但是，銅金屬無法以乾蝕刻的方式來定義圖案，因為銅 金屬與氣氣電漿氣體反應生成的氣化銅（CuC 12 )的沸點極 高（約1 5 0 0 °C )，因此銅導線的製作需以鑲嵌製程 (damascene process )來進行。另外，銅金屬的沈積通常 是以電鍍的方式，而在進行電鍍之前，需先於已形成溝槽的 介電層上形成一層順應性（conformal )阻障層後，於溝槽 中的阻障層表面沈積一層活化晶種層（seed layer)。 此外，當銅金屬電鍍完成後，需進行化學機械研磨製4 將多餘的銅磨除，然而，當化學機械研磨製程進行至一程度 時，會因為銅金屬與阻障層之間的研磨速率不同，造成所形 成的銅導線有碟化（dishing)和磨^(erosion)現象、介電 層會有剝離（peel ing)等耗損的問題發生，這些問題均會影200418100 V. Description of the invention (l) Field of the invention The present invention relates to a method for planarizing a metal layer, and more particularly to a method for electrolytic polishing a metal layer that can avoid a pattern density effect. ~ In the previous technology, in terms of integrated circuit technology, 'in order to improve the integration degree and data transmission speed of the south component', the process technology has entered the quarter-micron or even the sub-micron (sub-micr 0 n). Finer size range. However, the wire is no longer able to meet the speed requirements. The use of copper with high conductivity as the wire to reduce rc delay is a current trend. However, copper metal cannot define the pattern by dry etching, because the vaporized copper (CuC 12) produced by the reaction of copper metal and gas plasma gas has a very high boiling point (about 15 0 ° C), so the copper wire The fabrication process is performed by a damascene process. In addition, copper metal is usually deposited by electroplating. Before plating, a conformal barrier layer must be formed on the trenched dielectric layer, and then a barrier in the trench must be formed. A seed layer is deposited on the surface of the layer. In addition, after the copper metal plating is completed, chemical mechanical polishing is required to remove excess copper. However, when the chemical mechanical polishing process is performed to a certain extent, the polishing rate between the copper metal and the barrier layer will be different. , Resulting in the formation of copper wires have dishing and erosion phenomena, dielectric layer will have peeling problems such as peeling, these problems will affect

200418100 五、發明說明（2) 響内連線的品質。 因上述化學機 有人發展出電解拋 研磨製程，而成為 的優點在於使用電 屬轉為銅離子而脫 機械研磨法中機械 免介電層剝離現象 研磨速率的差異， 生。 i 然而在使用電 列問題：首先介電 因為電解金屬時， 金屬層其表面型態 於發揮電解拋光法 解離至露出介電層 於金屬離子在不同 同，導致電鍍後的 平坦化步驟方得與 另一面臨到的 内金屬的流失。以 具有溝槽2、3之半 層4 0，且在施行電 行電解拋光後的剖 械研磨製程所產生的缺點，在習知技術中 光銅金屬導電層的方法，欲取代化學機械 未來平坦化製程採用的技術。電解拋光法 解的化學方式將電鍍於介電層表面的銅金 離介電層表面，此化學方式避免了如化學 研磨部分對介電層所施加的應力，故可避 的發生’且可避免因銅金屬與介電層間的 造成溝槽内銅金屬的碟化、磨蝕等問題發 解拋光法來去除金屬導電層時，亦面臨下 層表面的金屬層必須已達相當的平整度， 亦如電鍍金屬時，一般而言金屬會會順應 而逐步脫離，故金屬層表面的平坦性有助 的最大效益，可逐步將介電層表面金屬層 表面為止。然而一般再電鑛金屬層時，由 線寬（line width)的溝槽中沈積速率的不 金屬層表面通常會凹凸不平，故一般須經 電解拋光法合併施行。 問題為圖案密度效應導致低圖案密度溝$ 下參照第1 a及第1 b圖說明。第1 a圖顯示一 導體基板1的剖面♦圖，其上已電鍍有金屬 解拋光前已達表面平整。第lb圖顯示在施 面圖。由第lb圖可看出在電解拋光後圖案200418100 V. Description of the invention (2) The quality of the internal connection. Because the above chemical machine has developed an electrolytic polishing process, it has the advantage of using electrical conversion to copper ions to remove the mechanical layer in the mechanical polishing method to avoid the phenomenon of dielectric layer peeling. The difference in polishing rate is caused. i However, in the case of using electric columns: firstly, when the dielectric is electrolyzed, the surface type of the metal layer is dissociated by the electrolytic polishing method to expose the dielectric layer to be different from the metal ions, which leads to the planarization step after electroplating. Another faced the loss of internal metal. With the shortcomings of the half-layer 40 with the grooves 2 and 3 and the electromechanical polishing process after electropolishing, the method of the optical copper metal conductive layer in the conventional technology is intended to replace the chemical mechanical future flat. Technology used in the manufacturing process. The chemical solution of electrolytic polishing method will remove the copper and gold plated on the surface of the dielectric layer from the surface of the dielectric layer. This chemical method avoids the stress imposed on the dielectric layer by the chemical polishing part, so it can be avoided and can be avoided. Due to the problem of dishing and abrasion of copper metal in the trench caused by the copper metal and the dielectric layer, when the polishing method is used to remove the metal conductive layer, the metal layer on the surface of the underlying layer must also have a fairly flat surface, such as electroplating. In the case of metal, in general, the metal will be gradually detached in response to the metal layer. Therefore, the flatness of the surface of the metal layer can help the maximum benefit, and the surface of the dielectric layer can be gradually changed to the surface of the metal layer. However, in general, when the metal layer is re-powered, the surface of the non-metallic layer formed by the deposition rate in the line width grooves is usually uneven, so it is generally combined with electrolytic polishing. The problem is that the pattern density effect causes a low pattern density groove. The description is made with reference to FIGS. 1 a and 1 b. Figure 1a shows a cross-sectional view of a conductor substrate 1, which has been plated with metal and has a flat surface before being polished. Figure lb is shown in the top view. Figure lb shows the pattern after electrolytic polishing

〇503-8174TWF(Nl) ： TSMC2001-1764 ； Renee.ptd 第5頁 200418100 五、發明說明（3) ---- 密度較低區域之溝槽2〇產生流失金屬的現象，此為由於使用 電解拋光至露出半導體10表面及溝槽2〇、30後，金屬電解的 速率對圖案密度較低區域中之溝槽2〇及密集溝槽3〇區會產生 差異，在圖案密度較低區域的溝槽20上方金屬的電解^ 岔集溝槽3 0區快，導致整體溝槽内金屬的深度無法一致的^ 到所預定的值，圖案密度較低區域之溝槽2〇會產生流失金屬 里此即稱為圖案密度效應。而本發明則為特:;針對此 發明内容〇503-8174TWF (Nl): TSMC2001-1764; Renee.ptd Page 5 200418100 V. Description of the invention (3) ---- The phenomenon of metal loss in the groove 20 in the lower density area is due to the use of electrolysis After polishing until the surface of the semiconductor 10 and the trenches 20 and 30 are exposed, the rate of metal electrolysis will cause a difference in the trenches 20 and dense trenches 30 in the lower pattern density area, and the trenches in the lower pattern density area will be different. The electrolysis of the metal above the groove 20 is fast. The area of the groove 30 is fast, which causes the depth of the metal in the overall groove to be inconsistent ^ to the predetermined value. The groove 20 in the region with a lower pattern density will lose the metal. This is called the pattern density effect. The present invention is special: in view of this invention

生的問題， ’其可避免 方金屬深度 有鑑於此，為了解決上述圖案密度效應所產 本發明主要目的在於提供一種金屬層平坦化方法 圖案密度效應而使在孤立的溝槽及密集溝槽區1 為達成上述目的，本發明提出一種 金屬層平坦化方法，其包括下列步驟·、，=，案岔度效應的 底，其具有一相對圖案密度高的溝槽區提供一半導體基 的溝槽區，接著於此半導體基底上^ 一相對圖案密度低 溝槽區，之後以一第一平坦化方式移:金屬層以填滿上述 著再以一第二平坦化方式移除上述半分上述金屬層，接 層，至露出上述半導體表面為止，且表面剩餘之金屬♦ 述相對圖案密度高的溝槽區及相對 $ —平坦化方式對上 金屬層之移除速率實質上相同。 一岔度低的溝槽區上方 如上所述，本發明利用之第—In order to solve the above problem of the pattern density effect, the main purpose of the present invention is to provide a method for planarizing a metal layer, and the pattern density effect can be used in isolated trenches and dense trench regions. 1 In order to achieve the above object, the present invention proposes a method for planarizing a metal layer, which includes the following steps: ... ,, =, the bottom of the bifurcation effect, which has a trench region with a relatively high pattern density to provide a semiconductor-based trench Area, and then on the semiconductor substrate a relatively low-density trench region, and then moved by a first planarization method: the metal layer is filled to fill the above and then the second half of the metal layer is removed by a second planarization method The bonding layer is until the above semiconductor surface is exposed, and the remaining metal on the surface ♦ The trench region with high relative pattern density and the relative $ —planarization method for removing the upper metal layer are substantially the same. Above the trench region with a low bifurcation As described above, the present invention uses

0503-81741^RN1) : TSMC2001 -1764 ； Renee.ptd 第6頁 200418100 五、發明說明（4) 式，較佳為電解抛光法 硫酸、和碟酸所組成的 如上所述，本發明 方式，較佳為化學餘刻 二其：：之電解液係選自由硫酸銅、 族群中 利用之第二 法，其係利 刻 本發 法，包括 銅晶種層 鍍溶液中 面；利用 刻方式移 體表面為 如上 以及一第 案密度高 移除速率 金屬層之 上述 解拋光方 屬層的去 的優點， 金屬的碟 段改以化 圖案密度 平坦化方 用璘酸溶 出一避免圖案密度 驟：提 半導體 電壓以 式移除 半導體 效應的金 供一具有溝槽之半導 基底上；將該半導體 沈積一銅金屬層在上 屬層；以 鋼金屬層 部分該銅金 表面剩餘之 本發明 化方式 區及相對圖案密度 相同 之特徵在於 ，其中藉由 可結合一 第二平坦 低的溝槽 來進一步克服圖案密 平坦化 第一平 式及化 除及平 避免了 化、介 學蝕刻 影響， 坦化方 學钱刻 坦化。 傳統化 電層的 法取代 故此亦 式以及一第 方式，其用 利用本發明 學機械研磨 磨#等問題 電解拋光法 解決了電解 二平坦化 以進行介 方法，可 法所造成 、並在製 ’由於化 抛光法所 式，其可為蝕刻 液進行化學餘 屬層平坦化方 體基底；形成_ 基底置入一銅電 述半導體基底表 及利用非電解蝕· ，至露出該半導 第一平坦化方式 化方式對相對圖 區上方金屬層之 度效應，並達成 方式可分別為電 電層上方電鍍金 結合電解拋光法「 介電層剝離、鋼 程中接近完成階 學蝕刻速率不受 面臨圖案密度效0503-81741 ^ RN1): TSMC2001 -1764; Renee.ptd Page 6 200418100 V. Description of the invention (4) Formula, preferably electrolytic polishing method sulfuric acid, and dishic acid is as described above. It is better to use chemical engraving II. The electrolyte solution is selected from the second method used by copper sulfate and the group. It is a method of engraving the hair, including the middle surface of the copper seed layer plating solution. As described above and in the first case, the above-mentioned advantages of the high-density removal rate metal layer for removing the polishing layer are as follows. The metal disc segment is changed to a flat pattern density and the flattened side is dissolved with osmium acid to avoid the pattern density. The semiconductor effect gold is removed on a semiconductive substrate with a trench; the semiconductor is deposited with a copper metal layer on the upper subordinate layer; a steel metal layer part of the copper-gold surface remaining on the copper-gold surface area and the relative pattern The feature of the same density is that it can be combined with a second flat low groove to further overcome the pattern dense planarization. Etching effects of Tan Tan engraved money side of science. The traditional electric layer method replaces this and the first and first methods. The electrolytic polishing method using the present invention to mechanically grind the mill # solves the electrolytic two planarization to perform the dielectric method, which can be caused by the method and is in process. Due to the chemical polishing method, it can be used to flatten a cuboid substrate with a chemical residual layer by an etching solution; forming the substrate into a copper semiconductor substrate surface and using non-electrolytic etching to expose the semiconducting first flat surface The effect of the method on the degree of the metal layer above the relative area, and the methods can be achieved by electroplating gold above the electrical layer combined with the electrolytic polishing method "the dielectric layer is peeled off, and the near-complete etch rate in the steel process is not subject to the pattern density effect

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0503-8174TWF(N1) ； TSMC200M764 ； Renee.ptd 第7頁 200418100 五、發明說明（5) 應的問題=本發明亦顧及化學㈣速率的緩慢，故單純以 A 餅it! 電鍍金屬層的去除及平坦化也不 拋光法及化學姓刻法此兩丄=明：說是結合了電解 化學機械研磨法的另一選擇.。 了取代傅統 為上述目的、特徵和優點能更明顯易懂，下 文特舉一較佳貫施例，並配合 、 W附圖式，作詳細說明如下： 實施方式 清參弟2 a圖至第2 e圖，繁9s 發明之電解拋光製程一較佳奋> ^弟e圖係用以說明本 首先請參閱第2a圖；=剖！圖。 矽曰圓，直上可以开…二代表一半導體基底，例如-矽日日&] /、上刁以形成任何所需的半導妒开杜r 土舶—、如 半導體基底20上有一介電層22 疋件（未顯不）。在 (CVD)而形成的氧化石夕層/或是可^如。疋以化學氣相沈積法 氮化石夕、…璃 '則：玻V、由二層上數層由氧切、 =:=序簡r示之。接著，以 度低的溝槽24及圖案密度高的溝槽25;代: 此處則以單鑲欲溝槽舉例，供後績製作銅導線之用’丨 接著，如第2b圖所示，可在介 槽24及圖案密度高的溝槽25表 ^ ：案密度低的溝 種層54可以瞧，或離子化金屬電=銅晶種層5“銅晶 κ U MF, ionized metal0503-8174TWF (N1); TSMC200M764; Renee.ptd Page 7 200418100 V. Explanation of the invention (5) Application problem = The present invention also takes into account the slow rate of chemical ㈣, so it simply uses A cake it! The removal of the electroplated metal layer and The flattening method and the polishing method and the chemical surname method are clear: it is another option that combines electrolytic chemical mechanical polishing. In order to replace Fu Tong for the above purpose, features and advantages, it is more obvious and easy to understand. The following is a detailed implementation example, which is described in detail with the following drawings: Implementation Mode Qingshendi 2a to 1st Figure 2e, traditional 9s invention of the electrolytic polishing process is a better idea> ^ brother e chart is used to explain this first, please refer to Figure 2a; = section! Illustration. The silicon is round and can be opened on the straight ... Two represents a semiconductor substrate, for example-Silicon Day &] /, to form any required semiconducting Kaidu r Tubo-such as a semiconductor substrate 20 with a dielectric Layer 22 file (not shown). The oxide layer formed by (CVD) may be exemplified.疋 The chemical vapor deposition method of nitride nitride, ... glass' then: glass V, cut by oxygen on the two layers, =: = sequence r shown. Next, the grooves 24 with a low degree and the grooves 25 with a high pattern density are replaced: Here, a single inlay groove is used as an example for the subsequent production of copper wires. Then, as shown in Figure 2b, Can be seen in the mesas 24 and the trenches 25 with high pattern density: the seed layer 54 with a low density can be seen, or the ionized metal = copper seed layer 5 "copper crystal κ U MF, ionized metal

0503-8174TO(Nl) ; TSMC200M764 ： Renee.ptd 第8頁 200418100 五、發明說明（6) plasma)濺鍍法沈積，厚度可為500 A至5〇〇〇 A之門。 @= 2第2c圖所示，進行金屬電鑛，例如為^金屬電 鍍，以在圖案密度低的溝槽24及圖案密度高的溝槽25内填入 銅，並在介電層22上方形成一銅金屬層4，其厚度a可為上、 計3 之間。以下為了方便說明起見，銅晶種層不·再二 不0 *只 接著進行介電層22表面銅金屬4的移除。首先，如第2d 圖所示，利用電解拋光法，將介電層22表面大部分的銅金屬 層4去除。電解拋光係採用例如濃度7〇%的磷酸溶液作為電解 液，溫度的較佳範圍係介於室溫〜5〇 t間， 度於約〇.〇1〜2安培/cm2，使銅的電解移除速率在2/〇〇電〜㈣聲 A/mU的數倍以上。其中電解液的選用亦可為硫酸銅、 硫酸或其組合。經由電解拋光法進行介電層22表面大部分銅 金屬層4的移除後，銅金屬層4較佳遺留的厚度為5〇〇至2〇〇〇 A間。 最後，如第2e圖所示，採用化學蝕刻法，將半導體基板 20置於蝕刻槽中，使用如含〇〜1〇〇 OOppm檸檬酸的85%磷酸溶 =’以如20〜6〇nm/min、依温度而定的蝕刻速率，均勻地將 介電層22表面剩餘的金屬層4以及圖案密度低的溝槽24上方 的，層40 2、圖案密度高的溝槽25上方的銅層403蝕刻移除，< 至路出介電層22的表面為止，且由於化學蝕刻法對圖案密度 低的溝槽24上方的銅層4〇2、圖案密噥高的溝槽25上方的銅 $403的餘刻速率相同，故蝕刻結束時銅層會停止在相同的 /木度’不致由於圖案密度效應而產生在圖案密度低的溝槽24 0503-8174TWF(Nl) ； TSMC2001- 1764 ； Renee.ptd 第9頁0503-8174TO (Nl); TSMC200M764: Renee.ptd Page 8 200418100 V. Description of the invention (6) Plasma sputtering deposition, thickness can be 500 A to 5000 A gate. @ = 2 As shown in FIG. 2c, a metal electromine is performed, for example, metal plating, to fill the trenches 24 with a low pattern density and the trenches 25 with a high pattern density, and form them over the dielectric layer 22. A copper metal layer 4 may have a thickness a between 3 and 3 inclusive. In the following, for convenience of explanation, the copper seed layer is not repeated, and is not 0. Only the copper metal 4 on the surface of the dielectric layer 22 is removed. First, as shown in Fig. 2d, most of the copper metal layer 4 on the surface of the dielectric layer 22 is removed by electrolytic polishing. The electrolytic polishing system uses, for example, a 70% concentration phosphoric acid solution as the electrolyte. The preferred range of temperature is between room temperature and 50 t, and the degree is about 0.01 to 2 amps / cm2. The removal rate is more than several times of 2/00 electricity ~ snoring A / mU. The choice of the electrolytic solution may be copper sulfate, sulfuric acid, or a combination thereof. After the majority of the copper metal layer 4 on the surface of the dielectric layer 22 is removed by an electrolytic polishing method, the copper metal layer 4 preferably has a thickness between 500 and 2000 A. Finally, as shown in FIG. 2e, the semiconductor substrate 20 is placed in an etching bath using a chemical etching method, and an 85% phosphoric acid solution containing citric acid such as 0 to 10,000 ppm = is used such as 20 to 60 nm / min, depending on the temperature, the etching rate, the remaining metal layer 4 on the surface of the dielectric layer 22 and the pattern pattern of the trenches 24 over the low density layer 24, layer 40 2, the pattern density of the copper layer 403 over the trench 25 Etching is removed until the surface of the dielectric layer 22 is exposed, and the copper layer 402 above the trench 24 with a low pattern density is formed by the chemical etching method. The copper above the trench 25 with a high pattern density is $ 403. The remaining etch rate is the same, so the copper layer will stop at the same / woodiness at the end of the etch. It will not cause grooves with low pattern density due to the pattern density effect. 24 0503-8174TWF (Nl); TSMC2001-1764; Renee.ptd Page 9

200418100 五、發明說明（7) 内銅金屬流失的情形。 上述以電解拋光及化學蝕刻兩方法搭配性的移除金屬層 的方式，各方法中移除銅層的相對比例並不在本發明限定的 範圍，可在考量施行經濟效益下自行選擇。 如上所述，依本發明施行的實施例，相較化學機械研磨 法或是傳統姓刻法，具有電解拋光的優點：可以有效避免銅 導線碟化、剝離和磨蝕的問題發生。且由於在製程最後步驟 加入化學蝕刻法，可均句的移除介電層表面剩餘的金屬層： 圖案密度低的溝槽上方的金屬層，以及 :的金屬而避免電解抛光法因圖案密度效應 本發明雖以較佳實施例 發明的範圍，任何熟習此項技藏 上 然其並非用以限定本 和範圍内，當可做些許的更藝者’在不脫離本發明之精神 圍當視後附之申請專利範R 與潤飾’因此本發明之保護範 ㈤所界定者為準。200418100 V. Description of the invention (7) The situation of copper metal loss. In the foregoing method of removing the metal layer by using the two methods of electrolytic polishing and chemical etching, the relative proportion of the copper layer removed in each method is not within the scope of the present invention, and can be selected by taking into consideration the implementation of economic benefits. As described above, according to the embodiment of the present invention, compared with the chemical mechanical polishing method or the traditional surname engraving method, it has the advantage of electrolytic polishing: it can effectively avoid the problems of dishing, peeling and abrading of copper wires. And because the chemical etching method is added at the last step of the process, the remaining metal layer on the surface of the dielectric layer can be removed uniformly: the metal layer above the trench with low pattern density, and the metal to avoid the effect of pattern density due to the electrolytic polishing method Although the present invention is based on the scope of the preferred embodiments of the invention, anyone familiar with this technology is not intended to limit the scope and scope, and can be a more performer without departing from the spirit of the present invention. The attached patent application R and retouching are therefore defined by the protection scope of the present invention.

200418100 圖式簡單說明 第la圖顯示一具有溝槽之半導體基板的剖面圖，其上覆 蓋有一平坦金屬層； 第1 b圖顯示第1 a圖中所示金屬層在施行電解拋光後的剖 面圖； 第2 a圖至第2 e圖係用以說明本發明之電解拋光製程一較 佳實施例的剖面圖。 符號說明 1、 20〜半導體基底； 5、2 2〜介電層； 2、 24〜圖案密度低的溝槽； 3、 25〜圖案密度高的溝槽； 4、 402、403〜金屬層； 5 4〜銅晶種層。200418100 Brief Description of Drawings Figure 1a shows a cross-sectional view of a semiconductor substrate with a trench covered with a flat metal layer; Figure 1b shows a cross-sectional view of the metal layer shown in Figure 1a after electrolytic polishing is performed Figures 2a to 2e are cross-sectional views for explaining a preferred embodiment of the electrolytic polishing process of the present invention. Explanation of symbols 1. 20 to semiconductor substrate; 5. 2 to 2 dielectric layer; 2. 24 to groove with low pattern density; 3. 25 to groove with high pattern density; 4. 402 and 403 to metal layer; 5 4 ~ Cu seed layer.

()503-8174TW(Nl) ； TSMC2001-1764 ； Renee.ptd 第11頁() 503-8174TW (Nl); TSMC2001-1764; Renee.ptd Page 11

Claims (1)

六、申請專利範圍 1 · 一種避 下列步驟： 提 區及一 於 以 以 出該半 向的溝 速率實 2. 金屬層 3· 金屬層 槽。 4. 金屬層 5· 金屬層 用之電 群中。 6. 金屬層 利用磷 供一半 相對圖 該半導 電解方 餘刻方 導體表 槽區及 質上相 如申請 平坦化 如申請 平坦化 如申請 平坦化 如申請 平坦化 解液係 如申請 平坦化 酸溶液 導體基 案密度 體基底 式移除 式移除 面為止 相對圖 同。 專利範 方法， 專利範 方法， 專利範 方法， 專利範 方法， 選自由 專利範 方法， 進行化 免圖案密度效應的金屬層平坦化方法，包括 底’其具有一相對圖案密度高的溝槽 低的溝槽區； 上形成一金屬層以填滿上述溝槽區； 部分該金屬層；以及 上述半導體表面剩餘之金屬層，至露 ’ t該1虫刻方式對該等相對圖案密度 案密度低的溝槽區上方金屬層之移除 ，第1項所述之避免圖案密度效應的 二中該半導體基底為一矽基底。 复第1項所述之避免圖案密度效應的 〃中上述溝槽為單鑲嵌或雙鑲嵌溝 =第1項所述之避免圖案密度效應的 其，該金屬層為—銅層。 ，第L項所述之避免圖案密度效應的 二中6亥電解方式為電解拋光法，其所 爪酉文銅、硫酸、和磷酸所組成的一族 ^項所述之*避免圖案密度效應的 二忒蝕刻方式為化學蝕刻法，其係 學蝕刻。6. Scope of patent application 1 · One method avoids the following steps: extracting the area and realizing it at the rate of the semi-directional groove 2. Metal layer 3 · Metal layer groove. 4. Metal layer 5 · The metal layer is used in the electric group. 6. The metal layer uses phosphorus for half of the relative map. The semi-conductive solution square cuts the surface area of the conductor and the phase. For example, apply for planarization. For example, for flattening. For example, for flattening solution. For example, for flattening acid solution. The relative diagrams of the conductor-based case-density-body-based removal-type removal surface are the same. The patented method, the patented method, the patented method, and the patented method are selected from the patented method and a method for flattening a metal layer without a pattern density effect, including a bottom having a relatively low pattern density and a low trench. A groove region; a metal layer is formed on the groove region to fill the groove region; a portion of the metal layer; and the remaining metal layer on the semiconductor surface are exposed to the relative pattern density with a low density. In the removal of the metal layer above the trench region, the second semiconductor substrate described in item 1 to avoid the effect of pattern density is a silicon substrate. The pattern groove avoiding pattern density effect described in item 1 above is a single damascene or double mosaic groove = the pattern density effect avoidance item described in item 1, wherein the metal layer is a copper layer. The electrolytic method for avoiding the effect of pattern density described in item L is electrolytic polishing method, which is a group consisting of copper, sulfuric acid, and phosphoric acid. The second item described in item ** to avoid the effect of pattern density The rhenium etching method is a chemical etching method, which is an etching method. 0503-8174TW(Ni) ： TSMC2001-1764 ； Renee.ptd 第12頁 200418100 六、申請專利範圍 7 · 一種避免圖案密度效應的金屬層平坦化方法，包括 下列步驟： 提供二具有溝槽之半導體基底； 層 於々半導體基底上形成一金屬層以填滿該溝槽； 利用電解方式移除部分該金屬層；以及 利用非電解#刻方式移除上述半導體表面剩餘之金屬 至露出=半導體表面為止。 8·如中4專利範圍第7項所述之避免圖案密度效應的 金屬9層平如坦化主方法中該半導體基底為一矽基底。 人s a如申清專利範圍第7項所述之避免圖案密度效應的 =s平坦化方法’其中上述溝槽為單鑲嵌或雙鑲嵌溝 槽。 a厘工如+ '凊專利範園第7項所述之避免圖案密度效應的 金屬，平坦由化/法，其中該金屬層為-銅層。 金屬層.平如坦化凊方專\園第7項所述，免圖案密度效應的 用之電解液係選自由電解：式為電解拋光法’其所 群中。 ；1L ‘銅、硫I、和磷酸所組成的一族 金屬声平\曰申(卜°\專么利轭圍第7項所述之避免圖案密度效應的 利用鱗酸溶液進行化學：：触刻方式為化學㈣法，其係 姓3牛種避免圖案密度效應的金♦屬層平坦化方法，包 括下列步驟： 提供一具有溝槽之半導體基底；0503-8174TW (Ni): TSMC2001-1764; Renee.ptd Page 12 200418100 6. Patent application scope 7 · A method for planarizing a metal layer to avoid the effect of pattern density, including the following steps: providing two semiconductor substrates with trenches; Forming a metal layer on the semiconductor substrate to fill the trench; removing a portion of the metal layer by electrolysis; and using a non-electrolytic method to remove the remaining metal on the semiconductor surface until the semiconductor surface is exposed. 8. The metal 9-layer flattening method as described in item 7 of the patent scope of Chinese 4 to avoid pattern density effects. The semiconductor substrate is a silicon substrate. As described in item 7 of the scope of the patent application, the method for avoiding the effect of pattern density = s flattening method ', wherein the groove is a single damascene or a double damascene groove. a. The metal as described in the item 7 of the '+ Patent Patent Park' to avoid the effect of pattern density is flattened, wherein the metal layer is a copper layer. Metal layer. As described in item 7 of Tanhuafangfangzhuanyuan, the electrolyte used to avoid the effect of pattern density is selected from the group consisting of electrolysis: the formula is electrolytic polishing method. ; 1L 'copper, sulfur I, and phosphoric acid group of metal sound level \ Yueshen (Bu ° \ Special Mody yoke Wai Item 7 to avoid the effect of pattern density using chemical solution: scale etching The method is a chemical method, which is a method for planarizing a metal layer of three cattle species to avoid the effect of pattern density, including the following steps: providing a semiconductor substrate having a trench; 0503-8174TWF(Nl) ; TSMC2001·1764 ; Renee ptd ---- 第13頁 200418100 六、申請專利範圍 形成一銅晶種層於上述半導體基底上； 將該半導體基底置入一銅電鍍溶液中，施加電壓以沈 積一銅金屬層在上述半導體基底表面； 利用電解拋光法移除部分該銅金屬層；以及 利用化學#刻法移除上述半導體表面剩餘之銅金屬 層，至露出該半導體表面為止。 1 4.如申請專利範圍第1 3項所述之避免圖案密度效應 ， 的金屬層平坦化方法，其中該半導體基底為一矽基底。 1 5.如申請專利範圍第1 3項所述之避免圖案密度效應 的金屬層平坦化方法，其中上述溝槽為單鑲嵌或雙鑲嵌溝 φ 槽。 1 6.如申請專利範圍第1 3項所述之避免圖案密度效應 的金屬層平坦化方法，其中該電解拋光法所用之電解液係 選自由硫酸銅、硫酸、和磷酸所組成的一族群中。 1 7.如申請專利範圍第1 3項所述之避免圖案密度效應 的金屬層平坦化方法，其中該化學蝕刻法係利用磷酸溶液 進行化學餘刻。 1 8. —種避免圖案密度效應的金屬層平坦化方法，包 括下列步驟： 提供一半導體基底，其具有一相對圖案密度高的溝槽 〇 區及一相對圖案密度低的溝槽區； 於該半導體基底上形成一金屬層以填滿上述溝槽區.； 以一第一平坦化方式移除部分該金屬層；以及 以一第二平坦化方式移除上述半導體表面剩餘之金屬0503-8174TWF (Nl); TSMC2001 · 1764; Renee ptd ---- page 13 200418100 6. Apply for a patent to form a copper seed layer on the semiconductor substrate; place the semiconductor substrate in a copper plating solution, A voltage is applied to deposit a copper metal layer on the surface of the semiconductor substrate; a portion of the copper metal layer is removed by an electrolytic polishing method; and a copper metal layer remaining on the semiconductor surface is removed by a chemical etching method until the semiconductor surface is exposed. 14. The method for planarizing a metal layer as described in item 13 of the scope of patent application, wherein the semiconductor substrate is a silicon substrate. 1 5. The method for planarizing a metal layer to avoid the effect of pattern density as described in item 13 of the scope of the patent application, wherein the groove is a single damascene or double damascene groove φ groove. 16. The metal layer planarization method for avoiding pattern density effect according to item 13 of the scope of the patent application, wherein the electrolytic solution used in the electrolytic polishing method is selected from the group consisting of copper sulfate, sulfuric acid, and phosphoric acid . 1 7. The method for planarizing a metal layer to avoid the effect of pattern density as described in item 13 of the scope of the patent application, wherein the chemical etching method uses a phosphoric acid solution to perform chemical etching. 1 8. A method for planarizing a metal layer to avoid pattern density effects, including the following steps: providing a semiconductor substrate having a trench region with a high relative pattern density and a trench region with a low relative pattern density; Forming a metal layer on the semiconductor substrate to fill the trench region; removing a portion of the metal layer by a first planarization method; and removing the remaining metal on the semiconductor surface by a second planarization method 0503-8174TWF(Nl) : TSMC2⑻1-1764 : Renee.ptd 第14頁 200418100 六、申請專利範圍 層，至露出該半導體表面為止，且該第二平坦化方式對該 等相對圖案密度高的溝槽區及相對圖案密度低的溝槽區上 方金屬層之移除速率實質上相同。 1 9.如申請專利範圍第1 8項所述之避免圖案密度效應 的金屬層平坦化方法，其中該第一平坦化方式為電解拋光 法，其所用之電解液係選自由硫酸銅、硫酸、和磷酸所組 成的一族群中。 2 0.如申請專利範圍第1 8項所述之避免圖案密度效應 的金屬層平坦化方法，其中該第二平坦化方式為化學蝕刻 法，其係利用磷酸溶液進行化學蝕刻。0503-8174TWF (Nl): TSMC2⑻1-1764: Renee.ptd Page 14 200418100 VI. Patent application layer, until the semiconductor surface is exposed, and the second planarization method has a high relative density of the trench regions The removal rate of the metal layer above the trench region with a relatively low pattern density is substantially the same. 19. The method for planarizing a metal layer to avoid the effect of pattern density as described in item 18 of the scope of the patent application, wherein the first planarization method is an electrolytic polishing method, and the electrolyte used is selected from the group consisting of copper sulfate, sulfuric acid, And phosphoric acid. 20. The method for planarizing a metal layer to avoid a pattern density effect according to item 18 of the scope of the patent application, wherein the second planarization method is a chemical etching method, which uses a phosphoric acid solution for chemical etching. 0503-8174TWF(Nl) ； TSMC2001-1764 ； Renee.ptd 第15頁0503-8174TWF (Nl); TSMC2001-1764; Renee.ptd page 15