TW588416B

TW588416B - Metal layer planarization method for preventing pattern density effect

Info

Publication number: TW588416B
Application number: TW92104385A
Authority: TW
Inventors: Shih-Wei Chou; Ming-Hsing Tsai; Shau-Lin Shue
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2003-03-03
Filing date: 2003-03-03
Publication date: 2004-05-21
Also published as: TW200418100A

Abstract

A metal layer planarization method for preventing pattern density effect comprises the following steps: firstly, providing a semiconductor substrate having a trench area with relatively high pattern density and a trench area with relatively low pattern density; forming a metal layer on the semiconductor substrate to fill up the aforementioned trench areas; using a first planarization method to remove a portion of the metal layer; then, using a second planarization method to remove the residual metal layer on the semiconductor substrate until the surface of the semiconductor substrate is exposed, in which the second planarization method has essentially the same removal rate for the metal layer at the top of the trench area with relatively high pattern density and for the metal layer at the top of the trench area with relatively low pattern density.

Description

588416 五、發明說明（1) 發明所屬之技術領域本發明係有關於一種金屬層平坦化方法，特別是有關於一種可避免圖案密度效應（Pattern density effect)的電解拋光金屬層方法。先前技術在積體電路的技術上’為了提南元件的積集度以及資料傳輸速度’製程技術已由次试米（sub-micron)進入了四分之一微米（quarter-micron)甚或更細微尺寸的範圍。然而’當線見愈來愈小’铭導線已無法滿足對速度的要求，气. 此，以具有高導電性之金屬銅做為導線，以降低“延遲（RC delay)，係為目前的趨勢。但是，銅金屬無法以乾蝕刻的方式來定義圖案，因為銅金屬與氣氣電漿氣體反應生成的氯化銅（C u c 12 )的沸點極尚（約1 5 0 0 C )’因此銅導線的製作需以鑲嵌製程 (damascene process )來進行。另外，銅金屬的沈積通常是以電鑛的方式’而在進行電鍍之前，需先於已形成溝槽的介電層上形成一層順應性（c 〇 n f 〇 r m a 1 )阻障層後，於溝槽中的阻障層表面沈積一層活化晶種層（seed layer)。此外，當銅金屬電鍍完成後，需進行化學機械研磨製4 將多餘的銅磨除，然而，當化學機械研磨製程進行至一程度時，會因為銅金屬與阻障層之間的研磨速率不同，造成所ς 成的銅導線有碟化（dishing)和磨蝕（erosion)現象、介電層會有剝離（peel ing)等耗損的問題發生，這些問題均會影588416 V. Description of the invention (1) Field of the invention The present invention relates to a method for planarizing a metal layer, and more particularly to a method for electrolytically polishing a metal layer that can avoid a pattern density effect. In the prior art, in the technology of integrated circuits, the process technology of 'in order to improve the integration degree and data transmission speed of South components' has been changed from sub-micron to quarter-micron or even finer. The range of sizes. However, when the wire is getting smaller and smaller, the Ming wire cannot meet the speed requirements. Therefore, the use of metal copper with high conductivity as the wire to reduce "RC delay" is the current trend. However, copper metal cannot define the pattern by dry etching, because the copper chloride (C uc 12) produced by the reaction between copper metal and gas plasma gas has a very high boiling point (about 15 0 0 C) '. Therefore copper The fabrication of the wires needs to be carried out in a damascene process. In addition, the copper metal is usually deposited by means of electrical ore. 'Before plating, a compliance layer must be formed on the dielectric layer where the trench has been formed. (C 〇nf 〇rma 1) After the barrier layer, an activated seed layer is deposited on the surface of the barrier layer in the trench. In addition, after the copper metal plating is completed, chemical mechanical polishing is required. Excess copper is removed. However, when the chemical mechanical polishing process is carried out to a certain extent, the copper wire and the barrier layer have different grinding rates, which causes the copper wires to be dished and abraded ( erosion) phenomenon, Problems layer will peel (peel ing) like depletion occurs, these problems will Movies

588416588416

五、發明說明（2) 響内連線的品質。因上述化學機械研磨製程所產生的缺點，在習知技術中有人發展出電解拋光銅金屬導電層的方法，欲取代化研磨製程’而成為未來平坦化製程採用的技術。電解拋光： =優點在於使用電解的化學方式將電鍍於介電層表面的銅金屬轉為銅離子而脫離介電層表面，此化學方式避免了如化學機械研磨法中機械研磨部分對介電層所施加的應力，故免介電層剝離現象的發生，且可避免因銅金屬與介電層間的研磨速率的差異，造成溝槽内銅金屬的碟化U等問題發生。然而在使用電解拋光法來去除金屬導電層時，亦面臨下《列問題：首先介電層表面的金屬層必須已達相當的平整度，因f電解金屬時，亦如電鍍金屬時，一般而言金屬會會：應金屬層其表面型態而逐步脫離，故金屬層表面的平坦性有助於發揮電解拋光法的最大效益，可逐步將介電層表面金屬層解離至露出介電層表面為止。然而一般再電鍍金屬層時，由於金屬離子在不同線寬（line width)的溝槽中沈積速率的不同，導致電鍍後的金屬層表面通常會凹凸不平，故一般須經平坦化步驟方得與電解拋光法合併施行。另一面臨到的問題為圖案密度效應導致低圖案密度溝4 内金屬的流失。以下參照第la及第lb圖說明。第1&圖顯示一具有溝槽2、3之半導體基板i的剖面，，其上已電鍵有金屬層40，且在施行電解拋光前已達表面平整。第丨匕圖顯示在施行電解拋光後的剖面圖。由第lb圖可看出在電解拋光後圖案V. Description of the invention (2) The quality of the internal connection. Due to the shortcomings of the above-mentioned chemical mechanical polishing process, some people have developed a method of electrolytically polishing the conductive layer of copper metal in the conventional technology, which is intended to replace the chemical polishing process' and become the technology used in the future planarization process. Electrolytic polishing: = The advantage is that the electroplated chemical method is used to convert the copper metal plated on the surface of the dielectric layer to copper ions and detach from the surface of the dielectric layer. This chemical method avoids the mechanical polishing part of the dielectric layer from chemically polishing The applied stress avoids the occurrence of the dielectric layer peeling phenomenon, and can avoid problems such as dishing U of the copper metal in the trench due to the difference in the polishing rate between the copper metal and the dielectric layer. However, when using the electrolytic polishing method to remove the metal conductive layer, it also faces the following problems: First, the metal layer on the surface of the dielectric layer must have a fairly flat degree. Because f electrolytic metal is also like electroplated metal, it is generally Speaking of metal society: The surface of the metal layer will gradually detach, so the flatness of the surface of the metal layer will help maximize the benefits of the electrolytic polishing method. The metal layer on the surface of the dielectric layer can be gradually dissociated to expose the surface of the dielectric layer. until. However, when the metal layer is re-plated, due to the different deposition rates of metal ions in the grooves with different line widths, the surface of the metal layer after plating is usually uneven, so it generally needs to go through a planarization step Combined electrolytic polishing method. Another problem is that the pattern density effect leads to the loss of metal in the low pattern density trench 4. The following description is made with reference to the la and lb diagrams. Fig. 1 & shows a cross section of a semiconductor substrate i having grooves 2, 3, on which a metal layer 40 has been electrically bonded, and the surface is flat before performing electrolytic polishing. Figure 丨 shows the cross-section view after electrolytic polishing. Figure lb shows the pattern after electrolytic polishing

588416 五、發明說明（3) ^ if ί區域之溝槽20產生流失金屬的現象’此為由於使用，拋光至露出半導體10表面及溝槽20、30後，金屬逮率對圖案密度較低區域中之溝槽20及密集溝槽3〇區會產生 =異、，在圖案密度較低區域的溝槽2〇上方金屬的電解^ 畨集溝槽30區快，導致整體溝槽内金屬的深度無法一致的到所預定的值，圖案密度較低區域之溝槽2〇會產生流失金屬的現象，此即稱為圖案密度效應。而本發明則為特別問題處理。 τ 丁此發明内容有本發明圖案密相同。為金屬層底，其的溝槽溝槽區著再以層，至述相對金屬層如鑑於此，為了解決上述圖案密主要目的在於提供一種金屬層度效應而使在孤立的溝槽及密提出一列步驟的溝槽底上形方式移上述半止，且相對圖達成上述目的，本發明平坦化方法，其包括下具有一相對圖案密度高區，接著於此半導體基，之後以一第一平坦化一第二平坦化方式移除露出上述半導體表面為圖案密度高的溝槽區及之移除速率實質上相同上所述，本發明利用之度效應所產生的問題，平坦化方法，其可避免集溝槽區上方金屬深度種避免圖案密度效應的 :首先提供一半導體基區及一相對圖案密度低成一金屬層以填滿上述除部分上述金屬層，接導體表面剩餘之金屬讀此第二平坦化方式對上案密度低的溝槽區上方第一平坦化方式可為電解方588416 V. Description of the invention (3) ^ if ί the phenomenon of metal loss occurs in the trench 20 in the region 'This is due to the use, after polishing to expose the surface of the semiconductor 10 and the trenches 20 and 30, the metal capture rate has a lower pattern density region The groove 20 in the middle and the dense groove 30 area will be different, and the electrolysis of the metal above the groove 20 in the area with a lower pattern density ^ The gathering groove 30 area is faster, resulting in the depth of the metal in the overall groove. If the predetermined value cannot be reached uniformly, the groove 20 in a region with a lower pattern density will lose metal, which is called a pattern density effect. The present invention deals with special problems. τ This invention has the same pattern as the present invention. It is the bottom of the metal layer, and its layer is located in the trench area. As far as the relative metal layer is concerned, in order to solve the above-mentioned pattern density, the main purpose is to provide a metal layer effect to isolate the trench and the density. A series of steps of the bottom shape of the trench shift the half stop, and the relative figure achieves the above purpose. The planarization method of the present invention includes a region having a high relative pattern density, followed by a semiconductor substrate, and then a first planarization. A second planarization method is used to remove the trench region that exposes the semiconductor surface with a high pattern density and the removal rate is substantially the same as described above. The problem caused by the degree effect of the present invention is a planarization method, which can Avoid collecting the metal depth above the trench area to avoid pattern density effects: first provide a semiconductor base region and a metal layer with a relatively low pattern density to fill the above-mentioned except the above-mentioned metal layer, and connect the remaining metal on the conductor surface to read this second The first planarization method above the trench region with a low density in the case may be an electrolytic method.

588416 五、發明說明（4) 式’較佳為電解拋光法，其所用之電解液係選自由硫酸銅、硫酸、和磷酸所組成的一族群中。如上所述，本發明利用之第二平坦化方式，其可為蝕刻方式’較佳為化學蝕刻法，其係利用磷酸溶液進行化學蝕刻。本發明尚提出一避免圖案密度效應的金屬層平坦化方法’包括下列步驟：提供一具有溝槽之半導體基底；形成一銅^種層於上述半導體基底上；將該半導體基底置入一銅電鍍溶液中，施加電壓以沈積一銅金屬層在上述半導體基底表面；利用電解方式移除部分該銅金屬層；以及利用非電解& 刻方式移除上述半導體表面剩餘之銅金屬層，至露出該半導體表面為止。如上所述，本發明之特徵在於可結合一第一平坦化方式以^ 一 =二平坦化方式，其中藉由第二平坦化方式對相對圖案密度高的溝槽區及相對圖案密度低的溝槽區上方金屬層之移除速率實質上相同’來進一步克服圖案密度效應，並‘成述第一平坦化方式以及十坦化方式可分別為電解拋光方式及化學蝕刻方式，其用以進行介電層上方電鍍金屬層的去除及平坦化。利用本發明方法，可結合電解拋^法^議 ::點’避免了傳統化學機械研磨法所造成金屬的碟化、介電層的磨姓等問題；‘並在製程段改以化學餘刻法取代電解拋光法，由於化 = 圖案密度影響，故此亦解決了電解拋光法所 =588416 5. Description of the invention (4) Formula ′ is preferably an electrolytic polishing method, and the electrolytic solution used is selected from the group consisting of copper sulfate, sulfuric acid, and phosphoric acid. As described above, the second planarization method used in the present invention may be an etching method ', preferably a chemical etching method, which is a chemical etching using a phosphoric acid solution. The present invention also proposes a method for planarizing a metal layer to avoid the effect of pattern density, including the following steps: providing a semiconductor substrate having a trench; forming a copper seed layer on the semiconductor substrate; and placing the semiconductor substrate in a copper plating In the solution, a voltage is applied to deposit a copper metal layer on the surface of the semiconductor substrate; a portion of the copper metal layer is removed by electrolysis; and the remaining copper metal layer on the semiconductor surface is removed by non-electrolytic & Up to the semiconductor surface. As described above, the present invention is characterized in that a first planarization method can be combined with ^ one = two planarization methods, wherein the trench region with high relative pattern density and the trench with low relative pattern density can be adjusted by the second planarization method. The removal rate of the metal layer above the trench area is substantially the same 'to further overcome the effect of pattern density, and' the first planarization method and the ten-tanning method can be an electrolytic polishing method and a chemical etching method, respectively, which are used for conducting Removal and planarization of the electroplated metal layer above the electrical layer. By using the method of the present invention, the electrolytic polishing method can be combined with :: point 'to avoid the problems of metal dishing and dielectric layer grinding caused by the traditional chemical mechanical grinding method;' and change the chemical process in the process section Method instead of electrolytic polishing method. Because of the influence of pattern density, it also solves the problem of electrolytic polishing method.

588416 五、發明說明（5) 應的問題。而本發明亦顧及化學蝕刻速率的緩慢，故單純以化學餘刻法進行介電層上方電鍍金屬層的去除及平坦化也不適於工業上所要求的快速量產。故本發明可說是結合了電解拋光法及化學餘刻法此兩種方法的優點，提供一可取代傳統化學機械研磨法的另一選擇。 ' 為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：實施方式請參照第2a圖至第2e圖，第2a圖至第2e^係用以說明^ 發明之電解拋光製程一較佳實施例的剖面圖。 — 首先請參閱第2a圖，標號20代表一半導體基底，例如_ 矽晶圓，其上可以形成任何所需的半導體元件（未顯示）。半導體基底20上有~介電層22，例如是以化學氣相沈積法 (CVD)而形成的氧化石夕層，或是可由單層或數層由氧化矽、氮化石夕“时玻璃L夕玻璃、或是其它低介電係數材料所構成的結構，但在此處僅以標號22簡單表示之。接著，以微影和蝕刻程序，在介電層22内形成複數個溝槽，以圖度低的溝及圖案密度高的溝槽25為代表說明。上述亦可為具有雙鑲嵌結構之溝槽，以供後續製作銅導線之此處則以單鑲嵌溝槽舉例說明。接著’如第2b圖所示，可在介電層22和圖案密度低的溝槽24及圖案密度商的溝槽25表面上形成一銅晶種㈣。銅^ 種層54可以濺鍍法或離子化金屬電聚（IMp;丨〇111_ 曰曰588416 V. Description of the invention (5) The corresponding problem. The present invention also takes into account the slow chemical etching rate, so simply removing and planarizing the electroplated metal layer over the dielectric layer by chemical post-etching is not suitable for rapid mass production required by industry. Therefore, the present invention can be said to combine the advantages of the two methods of electrolytic polishing method and chemical etching method, and provide an alternative to the traditional chemical mechanical polishing method. '' In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: For implementation, please refer to FIGS. 2a to 2e. 2a to 2e ^ are cross-sectional views for explaining a preferred embodiment of the electrolytic polishing process of the invention. — First refer to Figure 2a, reference numeral 20 represents a semiconductor substrate, such as a silicon wafer, on which any desired semiconductor element (not shown) can be formed. There is a dielectric layer 22 on the semiconductor substrate 20, such as a stone oxide layer formed by chemical vapor deposition (CVD), or a single layer or several layers made of silicon oxide and nitride The structure made of glass or other low-dielectric-constant material is simply indicated here by the reference numeral 22. Next, a plurality of trenches are formed in the dielectric layer 22 by lithography and etching procedures, as shown in the figure. Low degree grooves and high pattern density grooves 25 are representative descriptions. The above may also be grooves with a dual damascene structure for subsequent production of copper wires. Here, a single damascene groove is used as an example. As shown in Fig. 2b, a copper seed can be formed on the surface of the dielectric layer 22, the trench 24 having a low pattern density, and the trench 25 having a pattern density quotient. The copper seed layer 54 can be sputtered or ionized.聚（IMp; 丨〇111_

588416588416

五、發明說明（6) plasma)—濺鍍法沈積，厚度可為5〇〇人至5〇〇〇 A之間。供接第2c圖所示，進行金屬電鍍，例如為：金屬電鍍’以在圖案密度低的溝槽24及圖案密度 ^ , Λ/Λι! 广之間。以下為了方便說明起見，晶種層54不再顯接著進行介電層22表面銅金屬4的移除。首先，如第Μ 圖所示，制電解拋光法，將介電層22表面大部分的鋼金屬層4去除。電解拋光係採用例如濃度7〇%的磷酸溶液作為電解液，溫度的較佳範圍係介於室溫〜50 t間，調整陰極電流度於約0.01〜2安培/cm2，使銅的電解移除速率在2〇〇〇〜 3000A/min的數倍以上。其中電解液的選用亦可為硫酸銅、硫酸或其組合。經由電解拋光法進行介電層22表面大部分銅金屬層4的移除後，銅金屬層4較佳遺留的厚度為5〇〇至2〇〇〇 A間。最後，如第2 e圖所示，採用化學蝕刻法，將半導體基板 20置於触刻槽中，使用如含〇〜l〇〇〇〇ppm檸檬酸的85%磷酸溶液’以如2 0〜6 0 n m / m i η、依溫度而定的触刻速率，均勻地將介電層22表面剩餘的金屬層4以及圖案密度低的溝槽24上方的銅層402、圖案密度高的溝槽25上方的銅層403餘刻移除，峰至露出介電層22的表面為止，且由於化學蝕刻法對圖案密度低的溝槽24上方的銅層402、圖案密、度高的溝槽25上方的銅層4 0 3的蝕刻速率相同，故蝕刻結束時銅層會停止在相同的深度，不致由於圖案密度效應而產生在圖案密度低的溝槽24V. Description of the invention (6) plasma) —Sputter deposition, the thickness can be between 500 people and 5000 A. As shown in FIG. 2c, metal plating is performed, for example, metal plating is performed between the trench 24 having a low pattern density and the pattern density ^, Λ / Λι! In the following, for convenience of explanation, the seed layer 54 is no longer visible, and then the copper metal 4 on the surface of the dielectric layer 22 is removed. First, as shown in Fig. M, an electrolytic polishing method is used to remove most of the steel metal layer 4 on the surface of the dielectric layer 22. The electrolytic polishing system uses, for example, a 70% concentration phosphoric acid solution as the electrolyte. The preferred range of temperature is between room temperature and 50 t. The cathode current is adjusted to about 0.01 to 2 amps / cm2 to remove the copper electrolytically. The rate is several times higher than 2000 ~ 3000A / min. The choice of the electrolytic solution may be copper sulfate, sulfuric acid, or a combination thereof. After the majority of the copper metal layer 4 on the surface of the dielectric layer 22 is removed by an electrolytic polishing method, the copper metal layer 4 preferably has a thickness between 500 and 2000 A. Finally, as shown in FIG. 2e, the semiconductor substrate 20 is placed in a contact groove using a chemical etching method, and an 85% phosphoric acid solution containing citric acid such as 0 to 100 ppm is used, such as 20 to 60 nm / mi η, temperature-dependent etch rate, uniformly divides the remaining metal layer 4 on the surface of the dielectric layer 22 and the copper layer 402 above the trench 24 with low pattern density and the trench 25 with high pattern density The upper copper layer 403 is removed in a short time, and the peak reaches the surface of the dielectric layer 22, and due to the chemical etching method, the copper layer 402 above the trench 24 having a low pattern density and the trench 25 having a high density and a high pattern are formed by chemical etching. The etching rate of the copper layer 4 0 3 is the same, so the copper layer will stop at the same depth at the end of the etching, and the grooves with low pattern density will not be generated due to the pattern density effect 24

〇503-8174TWF(Nl) ； TSMC200M764 ； Renee.ptd〇503-8174TWF (Nl); TSMC200M764; Renee.ptd

588416 發明說明（7) 内鋼金屬流失的情形。上述以電解拋光及化學蝕刻兩方法搭配性的移除金屬 ^ 1? ~ ’ 百八’各方法中移除銅層的相對比例並不在本發明限定的 a圍’可在考量施行經濟效益下自行選擇。、、如上所述’依本發明施行的實施例，相較化學機械研磨暮或是傳統餘刻法，具有電解拋光的優點··可以有效避免銅線碟化、剝離和磨蝕的問題發生。且由於在製程最後步驟 =2，學姓刻法，可均勻的移吟介電層表面剩餘的金屬層、二密度低的溝槽上方的金屬層，以及圖案密度高的溝槽上 =的金屬層，而避免電解抛光法因圖案密度效應而f見的_ 本發明雖以較佳實施例揭露如上，發明的範圍，任何熟習此項技蔽I，h /非用％和範圍内，當可做些許的更動;2在：脫離本發明之精:; 圍當視後附之申請專利範圍所界定者為準此本發明之保護犯588416 Invention description (7) The situation of steel metal loss. The above-mentioned removal of metals in combination with electrolytic polishing and chemical etching ^ 1? ~ 'One hundred and eight' The relative proportion of the copper layer removed is not within the limits of the present invention, which can be determined by considering the implementation of economic benefits. select. As mentioned above, according to the embodiment of the present invention, compared with chemical mechanical polishing or traditional post-etching, it has the advantages of electrolytic polishing. It can effectively avoid the problems of copper wire dishing, peeling and abrasion. And since the last step of the process = 2, the method of engraving the surname can uniformly transfer the remaining metal layer on the surface of the dielectric layer, the metal layer above the trench with low density, and the metal on the trench with high pattern density = Layer to avoid electrolytic polishing method due to the effect of pattern density _ Although the present invention is disclosed in the preferred embodiment as above, the scope of the invention, any familiarity with this technology I, h / non-use% and range, when possible Make a few changes; 2 In: Depart from the essence of the present invention:

588416588416

一具有溝槽之半導體基板的剖面圖層；其上覆圖式簡單說明第1 a圖顯示蓋有一平坦金屬第lb圖顯示第圖中所示金屬層在施行電解拋光後的巧面圖；第2 a圖至第2 e圖係用以說明本發明之電解拋光製程一較佳實施例的剖面圖。符號說明 1、 20〜半導體基底； 5、22〜介電層； ‘ 2、 24〜圖案密度低的溝槽； 3、 25〜圖案密度高的溝槽； 4、 402、403〜金屬層； 5 4〜銅晶種層。A cross-sectional layer of a semiconductor substrate with a trench; a brief description of the superimposed drawings; FIG. 1 a shows a flat metal cover; FIG. 1 b shows a clever view of the metal layer shown in the figure after electrolytic polishing is performed; Figures a through 2e are cross-sectional views illustrating a preferred embodiment of the electrolytic polishing process of the present invention. Explanation of symbols 1, 20 to semiconductor substrate; 5, 22 to dielectric layer; '2, 24 to grooves with low pattern density; 3, 25 to grooves with high pattern density; 4, 402, 403 to metal layer; 5 4 ~ Cu seed layer.

0503-8174TWF(Nl) ； TSMC200M764 ： Renee.ptd 第11頁0503-8174TWF (Nl); TSMC200M764: Renee.ptd Page 11

Claims

六、申請專利範圍 1 一種避免圖案密下列步驟：提供一半導體基底區及一相對圖案密度低於該半導體基底上以電解方式移除部以姓刻方式移除上出該半導體表面為止，高的溝槽區及相對圖案速率實質上相同。 2 ·如申請專利範圍金屬層平坦化方法，其 3 ·如申請專利範圍金屬層平坦化方法，复槽。 ' 4·如申請專利範圍金屬層平坦化方法，其 5 ·如申請專利範圍金屬層平坦化方法，其用之電解液係選自由硫群中。 6·如申請專利範圍金屬層平坦化方法，其利用磷酸溶液進行化學度效應的金屬層平坦化方法，包括 ’其具有一相對圖案密度高的溝槽的溝槽區；形成一金屬層以填滿上述溝槽區；分該金屬層；以及述，導體表面剩餘之金屬層，至露士該蝕刻方式對該等相對圖案密度达度低的溝槽區上方金屬層之移除第1項所述之避免圖案密度效應的中该半導體基底為一矽基底。第1項所述之避免圖案密度效應的中上述溝槽為單鑲嵌或雙鑲嵌溝第1項所述之避免圖案密度效應的中該金屬層為一銅層。第1項所述之避免圖案密度效應的中違電解方式為電解拋光法，其所酸銅、硫酸、和磷酸所組成的一族第1/員所述之嚼免圖案密度效應的中遠餘刻方式為化學蝕刻法，其係餘刻。6. Scope of Patent Application 1 A method for avoiding pattern denseness: providing a semiconductor substrate region and a relative pattern density lower than that of the semiconductor substrate by electrolytically removing the semiconductor surface and removing the semiconductor surface by engraving. The trench region and the relative pattern rate are substantially the same. 2 · As the scope of patent application for metal layer planarization method, 3 · As the scope of patent application for metal layer planarization method, compound groove. '4 · As claimed in the scope of patent application for metal layer planarization method, 5 · As stated in the scope of patent application for metal layer planarization method, the electrolyte used is selected from the group consisting of sulfur. 6. A method for flattening a metal layer as claimed in the patent application, which uses a phosphoric acid solution to perform a chemical effect of the metal layer, including: 'a trench region having a trench having a relatively high pattern density; forming a metal layer to fill The above-mentioned trench region is divided; the metal layer is divided; and the remaining metal layer on the conductor surface is removed by Ruth's etching method to the metal layer above the trench region where the relative pattern density is low. It is mentioned that the semiconductor substrate is a silicon substrate to avoid the effect of pattern density. The groove for avoiding the pattern density effect described in item 1 is a single damascene or a double damascene groove. The metal layer for avoiding the pattern density effect described in item 1 is a copper layer. The medium electrolysis method for avoiding the effect of pattern density as described in item 1 is electrolytic polishing. The method described in the first and second member of the family consisting of acid copper, sulfuric acid, and phosphoric acid is used to avoid the pattern density effect. It is a chemical etching method, and it is a remainder.

588416 六、申請專利範圍 7·種避免圖案密度效應的金屬層平坦化方法，包括下列步驟·· 成匕符提供一具有溝槽之半導體基底；於遠半導體基底上形成一金屬層以填滿該溝槽；利用電解方式移除部分該金屬層；以及利用非電解蝕刻方式移除上述半導體表面剩餘之金屬層，至露出該半導體表面為止。 8·如申請專利範圍第7項所述之避免圖案密度效應的孟屬層平坦化方法，其中該半導體基底為一矽基底。 a 如申請專利範圍第7項所述之避免圖案密度效應的 ^屬層平坦化方法，#中上述溝槽為單鑲嵌或雙鑲後溝 1 0 ·如申請專利範圍第7 金屬層平坦化方法，其中該 1 1 ·如申請專利範圍第7 金屬層平坦化方法，其中該用之電解液係選自由硫酸銅群中。項所述之避免圖案密度效應的金屬層為一銅層。項所述之避免圖案密度效應的電解方式為電解拋光法，其所、硫酸、和磷酸所組成的一族 1 2·如申請專利範圍第7項所述之避免圖案密度效應的平坦化方☆，其中該蝕刻方式為化學蝕刻法，其係+ 利用磷酸溶液進行化學蝕刻。 13· —種避免圖案密度效應的金屬層平坦化方法，包括下列步驟：提供一具有溝槽之半導體基底；588416 6. Application patent scope 7. A method for planarizing a metal layer to avoid the effect of pattern density, including the following steps: forming a semiconductor substrate with a trench into a dagger; forming a metal layer on a far semiconductor substrate to fill the Trench; removing part of the metal layer by electrolytic method; and removing the remaining metal layer on the semiconductor surface by non-electrolytic etching method until the semiconductor surface is exposed. 8. The method of flattening a mongolian layer to avoid the effect of pattern density as described in item 7 of the scope of patent application, wherein the semiconductor substrate is a silicon substrate. a As described in item 7 of the scope of patent application, a method for flattening the metal layer to avoid the effect of pattern density, the grooves in # are single or double inlay grooves. Wherein, the 1 1 · method for flattening a metal layer as described in the seventh patent application range, wherein the electrolytic solution used is selected from the group consisting of copper sulfate. The metal layer described in the item to avoid the effect of pattern density is a copper layer. The electrolytic method for avoiding the effect of pattern density as described in the item is an electrolytic polishing method. The family consisting of sulfuric acid and phosphoric acid is a flattening method to avoid the effect of pattern density as described in item 7 of the scope of patent application ☆, The etching method is a chemical etching method, which uses + phosphoric acid solution for chemical etching. 13. · A method for planarizing a metal layer to avoid pattern density effects, including the following steps: providing a semiconductor substrate having a trench;

588416 六、申請專利範圍形成一銅晶種層於上述半導體基底上；將该半導體基底置入一銅電鐘溶液中，施加電壓以沈積一銅金屬層在上述半導體基底表面；利用電解拋光法移除部分該銅金屬層；以及利用化學蝕刻法移除上述半導體表面剩餘之銅金屬層至硌出該半導體表面為止。 14·如申請專利範圍第1 3項所述之避免圖案密度效應的金屬層平坦化方法，其中該半導體基底為一矽基底。 1 5 ·如申請專利範圍第丨3項所述之避免圖案密度效應的金屬層平坦化方法，其中上述溝槽為單鑲嵌或雙鑲嵌溝槽。 1 6 ·如申請專利範圍第1 3項所述之避免圖案密度效應的金屬層平坦化方法，其中該電解拋光法所用之電解液係選自由硫酸銅、硫酸、和礙酸所組成的一族群中。 1 7 ·如申請專利範圍第1 3項所述之避免圖案密度效應的金屬層平坦化方法，λ中該化學蝕刻法係利用心溶；進行化學蝕刻。 1 8· —種避免圖案密度效應的金屬層平垣化方法，包括下列步驟： /匕588416 6. Apply for a patent to form a copper seed layer on the semiconductor substrate; place the semiconductor substrate in a copper clock solution and apply a voltage to deposit a copper metal layer on the surface of the semiconductor substrate; Removing a portion of the copper metal layer; and removing the remaining copper metal layer on the semiconductor surface by chemical etching until the semiconductor surface is scooped out. 14. The method for planarizing a metal layer to avoid a pattern density effect according to item 13 of the scope of the patent application, wherein the semiconductor substrate is a silicon substrate. 1 5 · The method of planarizing a metal layer to avoid the effect of pattern density as described in item 3 of the scope of the patent application, wherein the groove is a single damascene or a double damascene groove. 16 · The method for planarizing a metal layer to avoid the effect of pattern density as described in item 13 of the scope of patent application, wherein the electrolytic solution used in the electrolytic polishing method is selected from the group consisting of copper sulfate, sulfuric acid, and acid blocking in. 17 · The method of planarizing a metal layer to avoid the effect of pattern density as described in item 13 of the scope of the patent application, the chemical etching method in λ uses heart melting; chemical etching is performed. 1 8 · —A method for flattening a metal layer to avoid the effect of pattern density, including the following steps: /

提供-半導體基底，其具有：相對圖案密度高的溝槽區及一相對圖案密度低的溝槽區，於該半導體基底上形成一金屬層以填滿上述溝槽區· 以一第一平坦化方式移除部分該金屬層；以及θ , 以一第二平坦化方式移除上述半導體表面剩餘之金屬Provide a semiconductor substrate having a trench region with a high relative pattern density and a trench region with a low relative pattern density. A metal layer is formed on the semiconductor substrate to fill the trench region with a first planarization Removing a part of the metal layer in a manner; and θ, removing the remaining metal on the semiconductor surface in a second planarization manner

0503-8174TW(Nl) ： TSMC200M764 ： Renee.ptd 第14頁 588416 六、申請專利範圍層，至露出該半導體表面為止，且該第二平坦化方式對該等相對圖案密度高的溝槽區及相對圖案密度低的溝槽區上方金屬層之移除速率實質上相同。 1 9.如申請專利範圍第1 8項所述之避免圖案密度效應的金屬層平坦化方法，其中該第一平坦化方式為電解拋光法，其所用之電解液係選自由硫酸銅、硫酸、和磷酸所組成的一族群中。 2 0.如申請專利範圍第1 8項所述之避免圖案密度效應的金屬層平坦化方法，其中該第二平坦化方式為化學蝕刻法，其係利用磷酸溶液進行化學蝕刻。0503-8174TW (Nl): TSMC200M764: Renee.ptd Page 14 588416 6. Apply for a patent scope layer until the semiconductor surface is exposed, and the second planarization method is for the trench regions with high relative pattern density and relative The removal rate of the metal layer above the trench region having a low pattern density is substantially the same. 19. The method for planarizing a metal layer to avoid the effect of pattern density as described in item 18 of the scope of the patent application, wherein the first planarization method is an electrolytic polishing method, and the electrolyte used is selected from the group consisting of copper sulfate, sulfuric acid, And phosphoric acid. 20. The method for planarizing a metal layer to avoid a pattern density effect according to item 18 of the scope of the patent application, wherein the second planarization method is a chemical etching method, which uses a phosphoric acid solution for chemical etching.

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