TW530347B

TW530347B - Planarization method of electrolytic polishing metal conductor layer

Info

Publication number: TW530347B
Application number: TW91101922A
Authority: TW
Inventors: Ming-Hsing Tsai; Shih-Wei Chou; Shau-Lin Shue; Mong-Song Liang
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-02-04
Filing date: 2002-02-04
Publication date: 2003-05-01

Abstract

This invention relates a planarization method of electrolytic polishing metal conductor layer, which comprises the following steps: providing a semiconductor substrate containing at least an opening; conformally forming a dopant element containing metal layer on the semiconductor substrate; globally forming a metal conductor layer on the dopant element containing metal layer; performing a thermal annealing step to convert the dopant element containing metal layer into a metal barrier layer and the metal conductor layer into an uniform metal conductor layer on the metal barrier layer; using an electrolytic polishing process to remove a portion of the uniform metal conductor layer to the metal barrier layer so that only the uniform metal conductor layer in the opening is remained; and performing a cleaning step to remove the metal barrier layer on the surface of the semiconductor substrate.

Description

530347 五、發明說明（1) 本發明係有關於一種電解拋光金屬導電層之平坦化方法，特別是有關於一種可輕易去除銅阻障層的電解拋光金屬導電層之平坦化方法。在積體電路的技術上，為了提高元件的積集度以及資料傳輸速度，製程技術已由次微米（sub —micr〇n)進入了四分之一微米（quarter-micron)甚或更細微尺寸的範圍。、然而，當線寬愈來愈小，鋁導線已無法滿足對速度的要求，因此，以具有高導電性之金屬銅做為導線，以降低 RC延遲（RC delay )，係為目前的趨勢。但是，銅金屬無法以乾蝕刻的方式來定義圖案，因為銅金屬與氯氣電漿氣體反應生成的氣化銅（Cuc )的沸點極高（約1 500 °C )，因此銅導線的製作需以鑲2嵌製程 (damascene process )來進行。另外，銅金屬的沈積通常是以電鍍的方式，而在進行電鍍之前，需先於已形成溝槽的介電層上形成一層順應性（conf ormai )阻障層後，於溝槽中的阻障層表面沈積一層活化晶種層（seed Uyer )° 此外，當銅金屬電鍍完成後，需進行化學機械研磨製程將多餘的銅磨除，然而，當化學機械研磨製程進行至一程度時，會因為銅金屬與阻障層之間的研磨速率不同，造成所形成的銅導線有碟化（dishing)、剝離（peeHng)和磨蝕（erosion)現象且有介電層耗損的問題發生，這些問題均會影響内連線的品質。一因上述化學機械研磨製程所產生的缺點，於是在習知530347 5. Description of the invention (1) The present invention relates to a method for planarizing an electrolytically polished metal conductive layer, and more particularly to a method for planarizing an electrolytically polished metal conductive layer that can easily remove a copper barrier layer. In terms of integrated circuit technology, in order to improve the component integration and data transmission speed, the process technology has moved from sub-micron to quarter-micron or even finer size. range. However, as the line width becomes smaller and smaller, aluminum wires can no longer meet the speed requirements. Therefore, it is the current trend to use metal copper with high conductivity as the wire to reduce the RC delay. However, copper metal cannot define the pattern by dry etching, because the vaporized copper (Cuc) produced by the reaction between copper metal and chlorine plasma gas has a very high boiling point (about 1 500 ° C), so the production of copper wires needs to Inlay 2 damascene process. In addition, the copper metal is usually deposited by electroplating. Before plating, a conforming (conf ormai) barrier layer must be formed on the dielectric layer where the trench has been formed, and then the resistance in the trench is formed. A seed seed layer (Seed Uyer) is deposited on the surface of the barrier layer. In addition, after the copper metal plating is completed, a chemical mechanical polishing process is required to remove excess copper. However, when the chemical mechanical polishing process is performed to a certain extent, Because the polishing rate between the copper metal and the barrier layer is different, the resulting copper wires have dishing, peeHng, and erosion problems, and the dielectric layer loss problems occur. These problems are all Will affect the quality of the interconnect. First, due to the disadvantages of the above chemical mechanical polishing process,

0503-6825TWf;TSMC2001-0637;Jerry.ptd 第4頁 530347 五、發明說明（2) ，術中有人發展出電解拋光銅金屬導電層之來避免因化學機械研磨製程時，一方法’ 的研磨诖盎τ η ^ - 因為銅金屬與阻障層之間 )、制離r〗同，^成所形成的銅導線有碟化（dishing L亲〗離（Peeiing)和磨蝕（erosi〇n)的問題發生。銅金屬阻障層仍然無法藉由電解拋光 ^ 機械研磨法，或是傳統㈣法而且再多經由化學機械研磨法或是傳的步驟後’很容易使銅導線發生碟化、剝離和磨握供有匕’為了解決上述問題，本發明主要目的在於 Ϊ:種屬導電層之平坦化方法，特別是有關 =方：：輕易去除銅阻障層的電解抛光金屬導電層之平坦為獲致上述之目的，本發明提出一種電解拋光金電層之平坦化方法’包括下列步驟：提供美有洗步具有至.少一開。;於該半導體基底上順應性形成體雜元素之金屬層；於該摻雜元素之金屬層上全面性形成二金屬導電層’實施一熱回火步驟，使該摻雜元素轉換形成一金屬阻障層’且使該金屬導電層轉換形成一均勻性的金屬導電層於該金屬阻障層上，利用電解拋移除部分該均勻性的金屬導電層至該金屬阻障層，以留^剩餘之該均勻性的金屬導電層於該開口内，實施一法驟，以去除該半導體基底表面的該金屬阻障層。一為使本發明之上述目的、特徵和優點能更明顯易懂0503-6825TWf; TSMC2001-0637; Jerry.ptd Page 4 530347 5. Description of the invention (2), someone developed an electrolytically polished copper metal conductive layer during the operation to avoid the chemical mechanical polishing process, a method of grinding τ η ^-Because the copper metal and the barrier layer are the same, and the separation r is the same, the copper wire formed by the formation has problems of dishing (peeiing) and abrasion (erosi). The copper metal barrier layer still cannot be electropolished ^ mechanical polishing method, or traditional polishing method, and after many chemical mechanical polishing methods or transmission steps, it is easy to cause copper wire to dish, peel and grind. In order to solve the above problems, the main purpose of the present invention is to: a method for planarizing a conductive layer, especially related to the square: the flatness of the electrolytically polished metal conductive layer that easily removes the copper barrier layer For the purpose, the present invention proposes a method for planarizing an electrolytically polished gold electrical layer, which includes the following steps: providing a beautiful washing step with at least one opening .; forming a metal layer of bulk impurity elements on the semiconductor substrate in compliance; A two-metal conductive layer is comprehensively formed on the metal layer of the doped element, and a thermal tempering step is performed to convert the doped element to form a metal barrier layer and the metal conductive layer is converted to form a uniform metal conductive layer. Layer on the metal barrier layer, and use electrolytic polishing to remove part of the uniform metal conductive layer to the metal barrier layer to leave the remaining uniform metal conductive layer in the opening, and implement a method To remove the metal barrier layer on the surface of the semiconductor substrate. One is to make the above-mentioned objects, features, and advantages of the present invention more obvious and easier to understand.

530347 五、發明說明（3) 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：圖示說明：第1圖係顯示本發明之實施例一中，在該半導體基底形成一開口之側視圖。第2圖係顯示本發明之實施例一中，在該半導體基底順應性形成一含有摻雜元素之金屬層之側視圖。 > 第3圖係顯示本發明之實施例一中，於該摻雜元素之銅金屬層上全面性形成一金屬導電層之側視圖。第4圖係顯示本發明之實施例一中，實施一熱回火步驟。第5圖係顯示本發明之實施例一中’利用電解拋光法移除部分該均勻性的銅金屬導電層至該銅金屬阻障層之側視圖。第6圖係顯示本發明之實施例一中’去除該半導體基底表面的該銅金屬阻障層之側視圖。第7圖係顯示本發明之實施例二中，在該半導體基底形成一雙鑲嵌溝渠之侧視圖。第8圖係顯示本發明之實施例二中，在該半導體基底順應性形成一含有摻雜元素之金屬層之側視圖。第9圖係顯示本發明之實施例二中，於該摻雜元素之銅金屬層上全面性形成一金屬導電層之側視圖。第1 0圖係顯示本發明之實施例二中，實施一熱回火步530347 V. Description of the invention (3) The following is a detailed description of a preferred embodiment and the accompanying drawings, which are described in detail as follows: Illustration: Figure 1 shows the first embodiment of the present invention. A side view forming an opening. FIG. 2 is a side view showing a metal layer containing a doping element conformably formed on the semiconductor substrate according to the first embodiment of the present invention. > FIG. 3 is a side view showing a comprehensively forming a metal conductive layer on the copper metal layer of the doping element in the first embodiment of the present invention. Fig. 4 is a diagram showing the implementation of a thermal tempering step in the first embodiment of the present invention. Fig. 5 is a side view showing that the part of the uniform copper metal conductive layer to the copper metal barrier layer is removed by using the electrolytic polishing method in the first embodiment of the present invention. Fig. 6 is a side view showing the first step of removing the copper metal barrier layer on the surface of the semiconductor substrate in the first embodiment of the present invention. FIG. 7 is a side view showing the formation of a double damascene trench in the semiconductor substrate according to the second embodiment of the present invention. Fig. 8 is a side view showing the second embodiment of the present invention, in which a metal layer containing a doping element is conformally formed on the semiconductor substrate. FIG. 9 is a side view showing a comprehensively forming a metal conductive layer on the copper metal layer of the doping element in the second embodiment of the present invention. Fig. 10 shows a second embodiment of the present invention, in which a thermal tempering step is performed.

0503-6825TW f;TSMC2001 -0637;J e r ry.p t d 第6頁 5303470503-6825TW f; TSMC2001 -0637; J e r ry.p t d p. 6 530347

—. 電解拋光法阻障層之側第11圖係顯示本發明之實施例二中，利用移除部分該均勻性的銅金屬導電層至該銅金視圖。臂 I除該半導體基第1 2圖係顯示本發明之實施例二中底表面的該銅金屬阻障層之側視圖。符號說明： 10、24〜半導體基底； "〜一開口； 12、26〜摻雜元素之金屬層；〜雙鑲嵌溝渠； 14、28〜金屬導電層； 16、30〜熱回火步驟； 1 8、3 2〜摻雜元素重新均勻分佈； 2 0、3 4〜銅金屬阻障層； 22、36〜均勻性的銅金屬導電層。實施例： (實施例一）一種電解拋光金屬導電層之平坦化方法，驟。在第1圖中，提供一半導體基底10，其中：括下列步底10為一矽基底，且在該半導體基底1〇包括有一。土在第2圖中，於該半導體基底丨〇上順應性形成^ 一右摻雜7G素之金屬層12，其中該摻雜元素之金屬層12，雜的元素係選自由鈦、錯、鎂、辞和碳其中―，且該^ 元素之金屬層12為一摻雜元素之銅金屬層。 ”—. Electrolytic polishing method side of barrier layer FIG. 11 shows the second embodiment of the present invention by removing part of the uniform copper metal conductive layer to the copper-gold view. Removing the semiconductor substrate from the arm I Fig. 12 is a side view showing the copper metal barrier layer on the bottom surface of the second embodiment of the present invention. Explanation of symbols: 10, 24 ~ semiconductor substrate; " ~ an opening; 12,26 ~ metal layer of doped element; ~ dual damascene trench; 14,28 ~ metal conductive layer; 16,30 ~ thermal tempering step; 1 8, 3 2 ~ doping elements are redistributed uniformly; 20, 3 4 ~ copper metal barrier layer; 22, 36 ~ uniform copper metal conductive layer. Embodiment: (Embodiment 1) A method for planarizing an electropolished metal conductive layer is as follows. In FIG. 1, a semiconductor substrate 10 is provided, in which the following steps are included. The substrate 10 is a silicon substrate, and the semiconductor substrate 10 includes a semiconductor substrate 10. In the second figure, a metal layer 12 doped with 7G element is formed on the semiconductor substrate compliantly, wherein the metal layer 12 of the doped element, the heteroelement is selected from the group consisting of titanium, tungsten, and magnesium Among them, carbon and carbon, and the metal layer 12 of the element is a copper metal layer doped with an element. "

0503-6825TWf;TSMC2001-0637;J e r ry.p td 第7頁 530347 五、發明說明（5) # $ ^第3圖中，於該摻雜元素之銅金屬層上全面性以電 ΐ電；形成一金屬導電層U，其中該金屬導電層14為-銅驟之二中，實施一熱回火步驟16，#中該熱回火步 xu^nn r ^ - v.至5〇 C之間，而该熱回火步驟之溫度又以MO c為取佳溫度❶實施該熱回火步驟16後，會使該摻之銅金屬層内的摻雜元素重新均勻分佈18於該銅導 ==22跟該半導體基幻。之間，自然轉f奐形= 銅金屬阻障層20，而該銅金屬阻障層20可為氧化辞、氧化锆、氧化鎭，或是氧化敍豆由少甘Ψ 乳化 20之戶许的户二其中中該銅金屬阻障層之与度約在ι〇Α〜ΐ〇〇Α之間。 ^5圖中’利用電解拋光法移除部分該均句性的銅金屬導電層22至該銅金屬阻障層2〇，以留下剩餘之該性的銅金屬導電層22於該開π11内。勺勻圖中’實施一簡易清洗步驟，以去除該半基底10表面的該銅金屬阻障層2〇，而不需額”用械研磨法或是傳統蝕刻法，可以有效避免銅導線碟化、^ =和磨蝕的問題發生，並可以控制製程的成本和降低複雜 (實施例二）一種電解拋光金屬導電層之平坦化方法，驟。在第7圖中’提供一半導體基底24，其中下列步底24為一矽基底，且在該半導體基底24包括有一雙鑲嵌%0503-6825TWf; TSMC2001-0637; J ry.p td page 7 530347 V. Description of the invention (5) # $ ^ In Figure 3, the copper metal layer of the doped element is fully electro-galvanized; A metal conductive layer U is formed, wherein the metal conductive layer 14 is-copper step two, a thermal tempering step 16 is performed, and the thermal tempering step ## is between xu ^ nn r ^-v. To 50 ° C. , And the temperature of the thermal tempering step is preferably MO c. After the thermal tempering step 16 is performed, the doping elements in the doped copper metal layer will be redistributed evenly in the copper conductor == 22 with this semiconductor base fantasy. In between, natural transition f 奂 = copper metal barrier layer 20, and the copper metal barrier layer 20 can be oxidized, zirconium oxide, hafnium oxide, or oxidized soybeans by Shaoganxi emulsified 20 The sum of the copper metal barrier layer in Huer is about ι〇Α ～ ι〇〇Α. ^ 5 In the figure, 'the electrolytic copper method is used to remove part of the homogeneous copper metal conductive layer 22 to the copper metal barrier layer 20 to leave the remaining copper metal conductive layer 22 in the opening π11. . A simple cleaning step is performed in the spoon scouring pattern to remove the copper metal barrier layer 20 on the surface of the semi-substrate 10 without the need of "mechanical grinding or traditional etching, which can effectively avoid copper wire dishing." , ^ =, And abrasion problems occur, and can control the cost of the process and reduce complexity (Embodiment 2) A method for planarizing an electrolytically polished metal conductive layer. In FIG. 7, 'a semiconductor substrate 24 is provided, of which the following Step bottom 24 is a silicon substrate, and the semiconductor substrate 24 includes a double damascene%.

530347 五、發明說明（6) 渠13。在第8圖中’於該半導體基底2 4上順應性形成一含有摻雜το素之金屬層26，其中該摻雜元素之金屬層26，可摻雜的元素係選自由鈦、鍅、鎂、鋅和碳其中一，且該摻雜元素之金屬層26為一摻雜元素之銅金屬層。在第9圖中，於該摻雜元素之銅金屬層上全面性以電鍍法來形成一金屬導電層28，其中該金屬導電層28為一銅導電層。熱回火步驟30 ’其中該熱回火步在第1 0圖中，實施驟之溫度在20(TC至45(TC之間，而該熱回火步驟之溫度又以300t為最佳溫度。實施該熱回火步驟3〇後，會使該摻雜元素之銅金屬層内的摻雜元素重新均勻分佈32於該銅導電層内，而轉換形成一均勻性的銅導電層36，並在該均勻性的銅導電層36跟該半導體基底24之間，自然轉換形成一銅金屬阻障層34，而該銅金屬阻障層34可為氧化鋅、 u化鎂，或是氧化鈦其中之一中該銅金屬阻障層 34之厚度約在1〇 A〜1〇〇 A之間。在第11圖中，利用電解拋光法移除部分該均自金屬導電層36至該銅金屬阻障層34，卩留下剩餘之該白性的銅金屬導電層36於該雙鑲嵌溝渠13内。、。二二在第1 2圖中，實施一簡易清洗步驟，以去除基底24表面，該銅金屬阻障層34，而不需額外利用/化風機械研磨法或是傳統蝕刻法，可以有效避免銅導干、離和磨蝕的問題發生，並可以&制f 、、、碟化、剝 I」以徑制I私的成本和降低複雜530347 V. Description of the invention (6) Channel 13. In FIG. 8 ′, a metal layer 26 containing doped το element is formed conformably on the semiconductor substrate 24, wherein the metal layer 26 of the doped element is dopable element selected from titanium, hafnium, and magnesium. , Zinc and carbon, and the doped element metal layer 26 is a doped element copper metal layer. In FIG. 9, a metal conductive layer 28 is formed on the copper metal layer of the doping element by electroplating method, wherein the metal conductive layer 28 is a copper conductive layer. The thermal tempering step 30 ′ wherein the thermal tempering step is shown in FIG. 10, and the temperature of the implementation step is between 20 ° C. and 45 ° C., and the temperature of the thermal tempering step is 300 t as the optimal temperature. After implementing the thermal tempering step 30, the doping elements in the copper metal layer of the doping elements will be redistributed 32 uniformly in the copper conductive layer, and a uniform copper conductive layer 36 will be converted and formed in The uniform copper conductive layer 36 and the semiconductor substrate 24 are naturally converted to form a copper metal barrier layer 34. The copper metal barrier layer 34 may be zinc oxide, magnesium oxide, or titanium oxide. In one, the thickness of the copper metal barrier layer 34 is between 10A and 100A. In FIG. 11, a portion of the copper metal barrier layer from the metal conductive layer 36 to the copper metal barrier is removed by electrolytic polishing. Layer 34, leaving the remaining white copper conductive layer 36 in the double damascene trenches 13. In FIG. 12, a simple cleaning step is performed to remove the surface of the substrate 24, the copper The metal barrier layer 34 can effectively avoid copper without the need for additional utilization / chemical mechanical polishing or traditional etching. The problems of dryness, separation and abrasion occur, and can be used to reduce the cost and complexity of the system.

530347 五、發明說明（7) 度。本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。530347 V. Description of invention (7) Degree. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

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Claims

530347530347

步驟^:-種電解抛光金屬導電層之平坦化方法，包括下列層；提供一半導體基底，具有至少一開口；於該半導體基底上順應性形成一含有摻雜元素之金屬於該摻雜元素之金屬層上全面性形成—金；一 ^施—熱回火步驟，使該摻雜元素之金屬=轉換ς成 :ΐ ί Ϊ障層’且使該金屬導電層轉換形成-均勻性的金屬導電層於該金屬阻障層上；利用電解拋光法移除部分該均勻性的金屬導至該金屬阻障層’卩留下剩餘之該均勻性的金屬導電層；該開口内。 2·如申請專利範圍第1項所述之電解拋光金屬導電層之平坦化方法，其中該半導體基底為一矽基底。 ,3·如申請專利範圍第1項所述之電解拋光金屬導電層之平坦化方法，其中該摻雜元素之金屬層，可摻雜的元素係選自由鈦、鍅、鎂、鋅和碳其中一。 4·如申凊專利範圍第1項所述之電解拋光金屬導電層之平坦化方法，其中該摻雜元素之金屬層為一摻雜元素之銅金屬層。 5·如申請專利範圍第1項所述之電解拋光金屬導電層之平坦化方法，其中該金屬導電層為一銅導電層。 6·如申請專利範圍第1項所述之電解拋光金屬導電層之平坦化方法，其中該熱回火步驟之溫度在20 0 °C至450 °CStep ^: A method of planarizing an electrolytically polished metal conductive layer, including the following layers; providing a semiconductor substrate having at least one opening; and compliantly forming a metal containing a doping element on the semiconductor substrate in the doping element Fully formed on the metal layer-gold; one step-thermal tempering step, so that the metal of the doped element = conversion: ΐ Ϊ barrier layer 'and the metal conductive layer is converted to form-uniform metal conduction Layer on the metal barrier layer; removing part of the uniform metal using the electrolytic polishing method to lead to the metal barrier layer; leaving the remaining conductive metal layer of the uniformity; inside the opening. 2. The method for planarizing an electrolytically polished metal conductive layer as described in item 1 of the scope of patent application, wherein the semiconductor substrate is a silicon substrate. 3. The method for planarizing an electrolytically polished metal conductive layer as described in item 1 of the scope of the patent application, wherein the metal layer of the doped element is a dopable element selected from the group consisting of titanium, hafnium, magnesium, zinc, and carbon. One. 4. The method for planarizing an electro-polished metal conductive layer as described in item 1 of the patent claim, wherein the metal layer of the doping element is a copper metal layer of doping element. 5. The method for planarizing the electrolytically polished metal conductive layer according to item 1 of the scope of the patent application, wherein the metal conductive layer is a copper conductive layer. 6. The method for planarizing the electrolytically polished metal conductive layer as described in item 1 of the scope of the patent application, wherein the temperature of the thermal tempering step is between 20 ° C and 450 ° C.

530347 六、申請專利範圍 —--— ---- 之間。 7.::請專利範圍第6項所述之電解拋光金屬導電芦 ::坦化方法，其中該熱回火步驟之溫度以3〇(pc為“ 8·如申請專利範圍第1項所述化鎂，和氧化鈦其中之一。 ’辛乳化^、氧 9 ·如申請專利範圍第1項所述 ‘ 之平坦化方法，其中該電解抛光電解拋光金屬導電層硫酸銅、硫酸、和磷酸所組成的—族群中Y解液係選自由 10· 一種電解拋光金屬導電層' / 列步驟：一化方法，包括下提供一半導體基底，具有一雙鑲嵌溝严· 於該半導體基底上順應性形成一二雜—、層； 3有摻雜兀素之金屬於該摻雜元素之金屬層上全面實施-熱回火步驟，使該摻雜元導電層；一金屬阻障層’且使該金屬導電層轉換t屬層轉換形成屬導電層於該金屬阻障層上；、乂成一均勻性的金利用電解拋光法移除部分該均勻性金屬阻障層，以留下剩餘之該均勻性^ ^屬導電層至該鑲嵌溝渠内。、金屬導電層於該雙實施一清洗步驟，以去除該半導阻障層。 -暴底表面的該金屬530347 VI. Scope of patent application -----------. 7. :: The electrolytic polishing metal conductive reed described in item 6 of the patent scope :: Tanning method, wherein the temperature of the thermal tempering step is 30 (pc is "8. As described in item 1 of the scope of patent application One of magnesium oxide and titanium oxide. The method of planarization of 'octanolyzed ^, oxygen 9 · as described in item 1 of the scope of patent application', wherein the electrolytic polishing electrolytically polishes a metal conductive layer of copper sulfate, sulfuric acid, and phosphoric acid. Composition—The Y solution in the group is selected from the group consisting of 10 · an electrolytically polished metal conductive layer '/ row of steps: a method comprising the following steps of providing a semiconductor substrate with a double damascene groove · conformable formation on the semiconductor substrate One or two hetero-, layers; 3 a metal-doped element metal layer on the metal layer of the doped element to fully implement the -tempering step to make the doped element conductive layer; a metal barrier layer 'and the metal The conductive layer is converted to a metal layer to form a metal conductive layer on the metal barrier layer; a uniform gold is removed by electrolytic polishing to remove part of the uniform metal barrier layer to leave the remaining uniformity ^ ^ Belong to the conductive layer The inner trench, the bi-metallic conductive layer embodiment a washing step to remove the semiconductive barrier layer - the bottom surface of the metal storm

0503-6825TlVf;TSMC2001-0637;Jerry.ptd 第12頁㈣347 、'申請專 1 -----^ --- 層之^ 如申請專利範圍第1 〇項所述之電解拋光金屬導電 12垣化方法，其中該半導體基底為一矽基底。層之平如申請專利範圍第1 〇項所述之電解拋光金屬導電素係、琴垣化方法，其中該摻雜元素之金屬層，可摻雜的元 =自由鈦、錯、鎂、辞和碳其中一。層之平如申請專利範圍第1 0項所述之電解拋光金屬導電之鋼if化方法，其中該摻雜元素之金屬層為一摻雜元素 J隻屬層。層之申請專利範圍第10項所述之電解拋光金屬導電 i^垣化方法，其中該金屬導電層為一銅導電層。層之·如申請專利範圍第10項所述之電解拋光金屬導電 ^ 垣化方法，其中該熱回火步驟之溫度在2〇〇〇c至45〇 L <間。 1 Ω 層之、/如申請專利範圍第1 5項所述之電解拋光金屬導電 1、、w平垣化方法’其中該熱回火步驟之溫度以300 為最 1主〉皿度。 μ 17·如申請專利範圍第1 0項所述之電解拋光金屬導電二之平坦化方法，其中該金屬阻障層為氧化鋅、氧化錯、氧化鎂，和氧化鈦其中之一。口 1、8 ·如申請專利範圍第丨〇項所述之電解拋光金屬導電層之平坦化方法，其中該電解拋光法所用之電解液係選自由硫酸銅、硫酸、和磷酸所組成的一族群中。、0503-6825TlVf; TSMC2001-0637; Jerry.ptd Page 12 ㈣ 347, 'Application 1 ----- ^ --- Layer of ^ Electrolytically polished metal conductive 12 as described in item 10 of the scope of patent application Method, wherein the semiconductor substrate is a silicon substrate. The level of the layer is the electrolytic polishing metal conductive element system and method described in item 10 of the scope of application patent, wherein the metal layer of the doped element can be doped element = free titanium, tungsten, magnesium, silicon Carbon one. The level of the layer is as described in the electrolytic polishing metal conductive steel if method described in item 10 of the scope of the patent application, wherein the metal layer of the doping element is a doping element J, which is only a layer. The electrolytic polishing metal conductive method described in item 10 of the patent application scope of the layer, wherein the metal conductive layer is a copper conductive layer. Layer-by-electrolytic polishing method as described in item 10 of the scope of patent application, wherein the temperature of the thermal tempering step is between 2000c and 4500L <. The 1 Ω layer is conductive as described in item 15 of the scope of the patent application. 1. The method of flattening w ′, wherein the temperature of the thermal tempering step is 300 ° C. μ 17. The planarization method for electropolished metal conductive as described in item 10 of the scope of the patent application, wherein the metal barrier layer is one of zinc oxide, oxide, magnesium oxide, and titanium oxide. Ports 1, 8 · The method for planarizing an electro-polished metal conductive layer as described in Item No. 0 of the patent application range, wherein the electrolytic solution used in the electrolytic polishing method is selected from the group consisting of copper sulfate, sulfuric acid, and phosphoric acid in. ,

0503-6825TWf;TSMC2001-0637;Jerry.ptd0503-6825TWf; TSMC2001-0637; Jerry.ptd